CN105304611B - A kind of copper nanotube vertical interconnecting structure and preparation method thereof - Google Patents
A kind of copper nanotube vertical interconnecting structure and preparation method thereof Download PDFInfo
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- CN105304611B CN105304611B CN201510868215.XA CN201510868215A CN105304611B CN 105304611 B CN105304611 B CN 105304611B CN 201510868215 A CN201510868215 A CN 201510868215A CN 105304611 B CN105304611 B CN 105304611B
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Abstract
The present invention relates to a kind of production methods of copper nanotube vertical interconnecting structure, belong to microelectronics integrated technology field.The present invention makes vertical long hole on substrate first；Insulating layer is made on the substrate surface, which covers the inner surface of the vertical long hole；In above-mentioned surface of insulating layer attached catalyst；With the help of catalyst, copper nanotube is grown on the surface of insulating layer；In deep hole center fill insulant after the growth of copper nanotube.Compared with the conventional perpendicular interconnection technology based on copper conductor, the present invention is conducive to improve the electric signal transmission performance of perpendicular interconnection and the heat-sinking capability of whole chip by the use of axially having the copper nanotube of high conductivity and high thermal conductivity as transmitting medium.Therefore, the present invention is with a wide range of applications in microelectronics integrated technology field.
Description
Technical field
The present invention relates to a kind of production methods of copper nanotube vertical interconnecting structure, belong to semiconductor and microelectronics integrates skill
Art field.
Background technology
Since Moore's Law proposes, integrated circuit follows Moore's Law rapid development, i.e., when price is constant, integrates
The number of open ended component on circuit can about be doubled every 18-24 months, and performance will also promote one times.However with
Nano grade can be narrowed down to by the size of integrated circuit, and when moving closer to its physics limit, down feature sizes
Method can not further improve the performance and function of integrated circuit.But the demand in microelectronics market is still in sustainable growth,
So as to which the development of integrated circuit is faced with a series of problem and challenge.
Three-dimensional integration technology can solve the problem above-mentioned.Compared to traditional planar circuit, three-dimensional integration technology is hanging down
Nogata carries out the stacking of chip and integrates upwards, under conditions of not needing to further reduce device feature size, improves electricity
The integrated level on road.Three-dimensional integration technology can integrate the chip of multiple material, kinds of processes and multiple functions in one, it will be apparent that
Improve the Electronic Performance of circuit.Perpendicular interconnection technology is the key that three-dimensional integration technology, it only has micron amount using a large amount of, length
The planar metal interconnection of the perpendicular interconnection substitution length centimetres of grade, while circuit level is improved, reduces well
Interference of the interconnection delay problem for circuit, improves the speed of circuit, circuit is made to possess lower power consumption.In general, it realizes
The method of vertical interconnecting structure is the etching through hole on chip, in through-hole surfaces deposition insulating layer, is later filled through-hole.Filling
The conductive material of through-hole includes metals, DOPOS doped polycrystalline silicon, carbon nanotube or the organic conductive materials such as polysilicon, copper, tungsten etc..
The general method filling central supported material using chemical vapor deposition.Chemical vapor deposition polysilicon and tungsten
All there is good conformality, and the hot environment in CMOS technology can be born.But the resistivity of the two is larger, electricity
Poor-performing, process costs are higher.It can be using metallic particles or organic matter filling the central supported material of high conductivity
Improve electric property to a certain extent, but this raising limitation, and CMOS technology compatibility is poor.In using copper as
Heart backing material process costs are relatively low, but it is there are integrity problem, this is because the coefficient of thermal expansion between copper and substrate loses
With larger.In addition, since copper filling perpendicular interconnection can bring larger capacitance and inductive coupling, this will influence high frequency electrical property
Energy.
This patent devises a kind of novel copper nanotube vertical interconnecting structure, and traditional handicraft is replaced using copper nanotube layer
In central supported material.Copper nanotube price is relatively low, is readily synthesized, and technique is relatively simple.It can be with using copper nano tube structure
Make the higher through-silicon via structure of depth-to-width ratio.Copper nanotube has the spies such as high conductivity, high heat conductance, good electromigration resisting property
Point, nano tube structure can also form the air gap, this is by the dielectric constant for reducing medium and alleviates due between copper and substrate
Problem caused by coefficient of thermal expansion mismatch is larger, improves the electric property of vertical interconnecting structure and the reliability of technique.
Invention content
The present invention devises a kind of copper nanotube vertical interconnecting structure, improves the electric property of vertical interconnecting structure, letter
The processing step of vertical interconnecting structure is changed.
The copper nanotube vertical interconnecting structure is as follows：
Copper nanotube vertical interconnecting structure includes substrate, insulating layer, copper nanotube layer, central supported material, metal interconnection
Line.There is vertical long hole structure on the silicon substrate, the vertical long hole penetrates substrate top surface, no perpendicular to substrate top surface
Penetrate substrate lower surface.Insulating layer is made in substrate surface, makes the insulating layer that substrate top surface, vertical long hole side wall be completely covered
And vertical long hole bottom.Surface of insulating layer in the vertical long hole side wall and bottom surface has copper nanotube layer, copper nanotube phase
It connects, forms conductive path.It is filled by insulating materials in the vertical long hole center.The vertical long hole is received by insulating layer, copper
Mitron layer and insulating materials are filled up completely.The copper nanotube layer is connected at vertical long hole upper surface with metal interconnecting wires
It connects.The copper nanotube layer of bottom exposes after substrate bottom is thinned.There is the copper of metal interconnecting wires and vertical long hole bottom
Nanotube layer connects.
The production method of copper nanotube vertical interconnecting structure, its step are as follows：
P01：The vertical long hole structure of vertical substrates upper surface is made on substrate.
The substrate can be element semiconductor material, such as silicon, germanium；May be compound semiconductor materials, such as arsenic
Gallium, indium phosphide；Insulating materials is alternatively, such as quartz, glass；
The vertical long hole is blind hole structure, i.e. deep hole does not penetrate substrate lower surface；
The vertical long hole can use reactive ion etching (RIE) or deep reaction ion etching (DRIE) or laser
Ablation or wet etching method make.
P02:In the inner surface of vertical long hole and upper surface uniform deposition insulating layer
The inner surface of the vertical long hole includes side wall and the bottom surface of vertical long hole；
The production method of the insulating layer is thermal oxide or physical vapor deposition or chemical vapor deposition or original
Sublayer deposit or plasma-reinforced chemical vapor deposition or low-temperature silicon dioxide deposit or spraying or spin coating etc.；
The insulating layer material is silica or aluminium oxide or silicon oxynitride or silicon nitride or high score
Sub- polymer；
The high molecular polymer is benzocyclobutene or polyimides or polyethylene or polydimethylsiloxanes
Alkane or epoxy resin.
P03：One layer of catalyst layer is made in the surface of insulating layer of vertical long hole inner surface.
The production method of the Catalytic Layer for physical vapor deposition or atomic layer deposition or chemical vapor deposition or
Person's plasma-reinforced chemical vapor deposition, material are Pd；
Before the catalyst layer is made, need to make dry film on surface insulation layer on substrate to completely cut off catalyst, make
Catalyst is only attached on the insulating layer of vertical long hole inner surface.
P04:Under the auxiliary of catalyst, copper nanotube is grown in surface of insulating layer
The copper nanotube growing method can be electrochemical deposition method, micropore/mesoporous molecular sieve template, soft template
Method sacrifices one or more of template, gas-liquid-solid growth mechanism method.
P05:After copper nanotube is grown, insulating layer is carried out to vertical long hole and is filled up completely, makes copper nanotube phase
It mutually contacts and is connected, realize the transmission of electric signal.
The fill method of the insulating layer is thermal oxide or physical vapor deposition or chemical vapor deposition or original
Sublayer deposit or plasma-reinforced chemical vapor deposition or low-temperature silicon dioxide deposit or spraying or spin coating；
The vertical long hole is filled using insulating materials, such as silica or aluminium oxide or silicon oxynitride or
Silicon nitride or high molecular polymer；
The high molecular polymer is benzocyclobutene or polyimides or polyethylene or polydimethylsiloxanes
Alkane or epoxy resin；
P06：After vertical long hole is filled up completely by insulating materials, removal remains in the residue of substrate surface.
The substrate surface is substrate top surface；
The residue is in the step for filling central insulating material, remains in the residue of substrate surface；
The method of the removal surface residues is mechanical lapping, reactive ion etching, selective wet chemical etching, chemical machinery
It is one or more in polishing.
P07：Surface making metal interconnect on substrate.
The metal interconnection is connected with copper nanotube；
The interconnection materials are one or more in copper, aluminium, gold, silver, platinum, titanium, tin, indium, bismuth or its alloy；
The implementation method of metal interconnection for reactive ion etching or selective wet chemical etching or metal-stripping or
Person's damascene process.
P08：From substrate lower surface organic semiconductor device, until the copper nanotube layer of vertical long hole bottom is exposed.
The thining method be mechanical lapping, one in reactive ion etching, selective wet chemical etching, chemically mechanical polishing
Kind is a variety of.
P09：In the making metal interconnect of substrate lower surface.
The substrate lower surface metal interconnection is connected with the copper nanotube layer that vertical long hole bottom is exposed；
The interconnection materials are one or more in copper, aluminium, gold, silver, platinum, titanium, tin, indium, bismuth or its alloy；
The implementation method of metal interconnection for reactive ion etching or selective wet chemical etching or metal-stripping or
Person's damascene process.
So far, copper nanotube vertical interconnecting structure making finishes.
Advantageous effect：
The advantage of the invention is that：Provide a kind of copper nanotube vertical interconnecting structure and preparation method thereof.Copper nanotube
Price is relatively low, is readily synthesized, and technique is relatively simple.The higher vertical silicon hole of depth-to-width ratio can be made using copper nano tube structure
(TSV), and copper nanotube has the features such as high conductivity, high heat conductance, good electromigration resisting property, these features can improve vertical
The electric property of straight interconnection structure, reduces between vertical interconnecting structure and the interference to other circuits.
Description of the drawings
Fig. 1 is a kind of production process of copper nanotube vertical interconnecting structure.
Fig. 2 is the schematic diagram for etching vertical through hole on substrate.
Fig. 3 is the schematic diagram in through-hole side wall and substrate top surface deposition insulating layer.
Fig. 4 is the schematic diagram that catalyst layer is made on through-hole side wall insulating layer.
Fig. 5 is under the effect of the catalyst, the schematic diagram of copper nanotube to be grown in lateral wall insulation layer surface.
Fig. 6 is the schematic diagram with insulating materials filling vertical through hole.
Fig. 7 is the schematic diagram after substrate top surface residue is removed.
Fig. 8 is the schematic diagram of substrate top surface making metal interconnect.
Fig. 9 is that thinned schematic diagram is carried out to substrate.
Figure 10 is the schematic diagram of substrate lower surface making metal interconnect.
Label declaration：
101- substrates, 102- substrate top surfaces, 103- substrates lower surface, 201- insulating layers, 202- insulating layers, 203- substrates
Upper surface insulating layer, 204- substrates lower surface insulating layer, 301- copper nanotubes, 302- conductive paths, 401- substrate top surfaces gold
Belong to interconnection, 402- substrate lower surface metal interconnections, 501- dry films, 601- Catalytic Layers, S- circle deep holes, S1- deep hole side walls, S2-
Deep hole side wall, S3- deep hole bottoms.
Specific embodiment
For objects and advantages of the present invention are better described, the present invention is carried out with reference to the accompanying drawings and examples further
Detailed description.
A kind of production method flow of copper nanotube vertical interconnecting structure disclosed in this invention is as shown in Figure 1, specific real
It is as follows to apply step：
First as shown in Fig. 2, providing substrate 101, substrate material can be semi-conducting material, such as silicon, GaAs；It can also
For insulating material, such as glass, quartz.Using reactive ion etching (RIE) or deep reaction ion etching (DRIE), laser
Ablation or wet etching etch vertical through hole S on substrate.The vertical long hole S is blind hole structure, that is, penetrates substrate
Upper surface 102 does not penetrate substrate lower surface 103, and deep hole is perpendicular to substrate top surface.The high-aspect-ratio vertical long hole cross section
For circle, a diameter of 4um；The vertical long hole depth is 70um, but not limited to this depth-to-width ratio.
Surface 102 on substrate, vertical through hole side wall S1, S2, vertical long hole bottom surface S3 make the insulating layer 201 of 200nm,
As shown in Figure 3.201 production method of insulating layer be thermal oxide or physical vapor deposition or chemical vapor deposition,
Or atomic layer deposition or plasma-reinforced chemical vapor deposition or low-temperature silicon dioxide deposit or spraying or
Spin coating.This example uses silica as the insulating layer material, but the insulating layer material is not limited to silica.Institute
It can be silica or aluminium oxide or silicon oxynitride or silicon nitride or high molecular polymerization to state insulating layer material
Object.The high molecular polymer for benzocyclobutene or polyimides or polyethylene or dimethyl silicone polymer or
Person's epoxy resin.
As shown in figure 4, the Catalytic Layer of one layer of 50nm thickness is made on the insulating layer of vertical long hole side wall S1, S2 and bottom surface S3
601, it, can surface insulation layer on substrate in order to which catalyst is made to be only attached to vertical long hole side wall and the surface of insulating layer of bottom surface
It is upper to be laid with dry film 501 to completely cut off catalyst.The production method of the Catalytic Layer is physical vapor deposition, atomic layer deposition, chemistry
Vapor deposition or plasma-reinforced chemical vapor deposition, material can be Pd.
Under the effect of the catalyst, copper nanotube 301 is grown in surface of insulating layer, as shown in figure 5, copper nanotube 301 is grown
It spends for 3um.After copper nanotube is grown, the dry film 501 on 201 surface of insulating layer is removed.
As shown in fig. 6, after copper nanotube is grown, vertical through hole S insulating materials 202 is filled up completely.This example
Using silica as the insulating materials 202, but the insulating materials is not limited to silica, can be titanium dioxide
Silicon or glass or aluminium oxide or silicon oxynitride or silicon nitride or high molecular polymer.The polyphosphazene polymer
Object is closed as benzocyclobutene or polyimides or polyethylene or dimethyl silicone polymer or epoxy resin.It is filling out
During filling, extra insulating materials can form extra insulating layer on 201 surface of silicon dioxide insulating layer, after filling,
Copper nanotube is contacted with each other, forms conductive path 302.
As shown in fig. 7, after vertical through hole is filled, the insulating layer 202 of 201 excess surface of insulating layer is removed.It is described
Remove surface residues method for mechanical lapping, reactive ion etching, selective wet chemical etching, one kind in chemically mechanical polishing or
It is a variety of.
Surface making metal interconnect on substrate, as shown in Figure 8.The present embodiment uses low temperature dioxy first at 350 DEG C
The silicon dioxide insulating layer 203 of SiClx deposition process surface deposition 200nm thickness on substrate；Then, it is carved using reactive ion
The silicon dioxide insulating layer 203 of 200nm thickness above etching method removal vertical through hole, forms contact window；Then, using big
The copper interconnecting line 401 of Ma Shige copper-connection manufacturing methods, on substrate surface manufacture 1um thickness.The copper of the substrate top surface
Interconnection line is connected with the copper nanotube layer in vertical long hole.
Further, it is also possible to make upper surface metal interconnection using the material different from vertical conduction body, for example, aluminium, gold, silver,
It is one or more in platinum, titanium, tin, indium, bismuth or its alloy；Can also use reactive ion etching or selective wet chemical etching,
Or the method for metal-stripping realizes the manufacture of substrate surface metal interconnecting wires.
As shown in figure 9, from substrate lower surface organic semiconductor device, until the copper nanotube layer of vertical long hole inner bottom surface is exposed.
The present embodiment removes most silicon substrate using mechanical grinding method from the back side first, until backing substrate approaches
The bottom of vertical long hole；Then, planarizing process is carried out to silicon substrate lower surface using cmp method until vertical
Deep hole copper nanotube layer is exposed.Further, it is also possible to silicon substrate is thinned using selective wet chemical etching method.
In silicon substrate lower surface making metal interconnect 402, as shown in Figure 10, the present embodiment is first at 350 DEG C using low
Warm silicon dioxide deposition method is in the silicon dioxide insulating layer 204 of substrate surface deposit 200nm thickness；Then, using reaction from
The silicon dioxide insulating layer 204 of 200nm thickness above sub- lithographic method removal vertical through hole, forms contact window；Then, it adopts
With Damascus copper-connection manufacturing method, the copper interconnecting line 402 of 1um thickness is manufactured in substrate surface.The substrate lower surface
Copper interconnecting line is connected with the copper nanotube layer in vertical long hole.
Further, it is also possible to the metal that lower surface is made of the material different from vertical conduction body interconnects, for example, aluminium, gold,
It is one or more in silver, platinum, titanium, tin, indium, bismuth or its alloy；Reactive ion etching or wet chemical can also be used to carve
The method of erosion or metal-stripping realizes the manufacture of metal interconnecting wires.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, that is made any repaiies
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of copper nanotube vertical interconnecting structure, main to include with lower structure：Substrate (101), insulating layer (201) (203)
(204), central supported material (202), copper nanotube layer (302), metal interconnection structure (401) (402), which is characterized in that institute
The copper nanotube layer stated penetrates substrate perpendicular to substrate, and the central supported material penetrates substrate perpendicular to substrate,
It is surrounded by copper nanotube layer, between the copper nanotube layer and substrate, by insulator separation.
A kind of 2. copper nanotube vertical interconnecting structure according to claim 1, which is characterized in that the copper nanotube layer
On substrate, lower surface is connected respectively with metal interconnection structure.
A kind of 3. copper nanotube vertical interconnecting structure according to claim 1, which is characterized in that the central supported material
It can be the mixture of organic matter, inorganic matter or organic matter and inorganic matter.
4. a kind of production method of copper nanotube perpendicular interconnection, step include
P01：On substrate using reactive ion etching or the method for selective wet chemical etching, the depth perpendicular to substrate surface is produced
Pore structure, deep hole do not penetrate substrate,
P02：In above-mentioned substrate top surface and vertical long hole inner surface deposition insulating layer,
P03：Using dry film photoetching technique, substrate surface is protected, the selectively surface of insulating layer deposit in vertical long hole is urged
Agent layer,
P04：Copper nanotube is grown in vertical long hole,
P05：Vertical long hole central part is filled up completely using insulating materials, so as to form central supported material, above-mentioned copper is made to receive
Mitron contacts with each other under the extruding of the central supported material and insulating layer, forms conductive path,
P06：Removal remains in the extra insulation of substrate surface and vertical long hole opening when filling above-mentioned central supported material
Material,
P07：Surface makes metal interconnection on substrate,
P08：Processing is carried out back thinning to above-mentioned substrate, until the copper nanotube layer of above-mentioned vertical long hole is showed from substrate following table
Go out,
P09：Making and a sequence of metal interconnection structure of copper nanotube layer in substrate lower surface,
So far, copper nanotube vertical interconnecting structure making finishes.
A kind of 5. production method of copper nanotube perpendicular interconnection according to claim 4, which is characterized in that the insulating layer
Implementation method deposited for low-temperature silicon dioxide or chemical vapor deposition or thermal oxide or spraying or spin coating side
Method.
A kind of 6. production method of copper nanotube perpendicular interconnection according to claim 4, which is characterized in that the catalysis
Oxidant layer material is Pd, and the deposition process of the catalyst includes physical vapor deposition or atomic layer deposition or chemical gas
Mutually deposit or plasma-reinforced chemical vapor deposition.
A kind of 7. production method of copper nanotube perpendicular interconnection according to claim 4, which is characterized in that the copper nanometer
The production method of tube layer include electrochemical deposition or micropore/mesoporous molecular sieve template or soft template method or gas-
Liquid-solid growth mechanism method.
A kind of 8. production method of copper nanotube perpendicular interconnection according to claim 4, which is characterized in that the center branch
The fill method of timbering material can use physical vapor deposition or atomic layer deposition or chemical vapor deposition or wait from
Son enhancing chemical vapor deposition.
9. the production method of a kind of copper nanotube perpendicular interconnection according to claim 4, which is characterized in that on the substrate
The implementation method of surface metal interconnection and substrate lower surface metal interconnection for reactive ion etching or selective wet chemical etching or
Person's metal-stripping or damascene process, the material of metal interconnection be material be copper, aluminium, gold, silver, platinum, titanium, tin, indium,
It is one or more in bismuth or its alloy.
A kind of 10. production method of copper nanotube perpendicular interconnection according to claim 4, which is characterized in that thinned reality
Existing method is one or more in mechanical lapping, reactive ion etching, selective wet chemical etching, chemically mechanical polishing.
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| CN110491831B (en) * | 2019-07-26 | 2022-06-14 | 福建省福联集成电路有限公司 | Method for manufacturing through hole and manufactured device |
| CN113782595A (en) * | 2020-06-10 | 2021-12-10 | 中国科学院微电子研究所 | Semiconductor device, manufacturing method thereof and electronic equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102130091A (en) * | 2010-12-17 | 2011-07-20 | 天津理工大学 | Composite through-hole interconnecting structure for integrated circuit chip and preparation method thereof |
| CN102569181A (en) * | 2011-12-15 | 2012-07-11 | 中国科学院微电子研究所 | Method for manufacturing vertically interconnecting carbon nanotube bundle |
| CN103311141A (en) * | 2013-07-05 | 2013-09-18 | 北京理工大学 | Manufacturing method of coaxial vertical interconnection conductor |
| CN104900585A (en) * | 2015-04-16 | 2015-09-09 | 北京理工大学 | Preparation method for sidewall insulating layer of vertical interconnection |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102130091A (en) * | 2010-12-17 | 2011-07-20 | 天津理工大学 | Composite through-hole interconnecting structure for integrated circuit chip and preparation method thereof |
| CN102569181A (en) * | 2011-12-15 | 2012-07-11 | 中国科学院微电子研究所 | Method for manufacturing vertically interconnecting carbon nanotube bundle |
| CN103311141A (en) * | 2013-07-05 | 2013-09-18 | 北京理工大学 | Manufacturing method of coaxial vertical interconnection conductor |
| CN104900585A (en) * | 2015-04-16 | 2015-09-09 | 北京理工大学 | Preparation method for sidewall insulating layer of vertical interconnection |
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