CN105262477A - S4R (Series Sequential Switching Shunt Regulator) logic control circuit and logic control implementation method thereof - Google Patents

S4R (Series Sequential Switching Shunt Regulator) logic control circuit and logic control implementation method thereof Download PDF

Info

Publication number
CN105262477A
CN105262477A CN201510820843.0A CN201510820843A CN105262477A CN 105262477 A CN105262477 A CN 105262477A CN 201510820843 A CN201510820843 A CN 201510820843A CN 105262477 A CN105262477 A CN 105262477A
Authority
CN
China
Prior art keywords
gate
logic control
output
charging
drive singal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510820843.0A
Other languages
Chinese (zh)
Other versions
CN105262477B (en
Inventor
王新征
徐泽锋
丁一宁
郑磊
宋楠
瞿诗霞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Institute of Space Power Sources
Original Assignee
Shanghai Institute of Space Power Sources
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Institute of Space Power Sources filed Critical Shanghai Institute of Space Power Sources
Priority to CN201510820843.0A priority Critical patent/CN105262477B/en
Publication of CN105262477A publication Critical patent/CN105262477A/en
Application granted granted Critical
Publication of CN105262477B publication Critical patent/CN105262477B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Charge And Discharge Circuits For Batteries Or The Like (AREA)

Abstract

The present invention relates to an S4R (Series Sequential Switching Shunt Regulator) logic control circuit and a logic control implementation method thereof. The input end of the logic control circuit is connected with a complete modulation control signal FG1 and a charge control signal FG2, and the formulas, G1=FG1&FG2 and G2=FG2 + (^FG1), are realized after logic operation; and a shunt drive signal G1 outputted via the output end of the logic control circuit is connected with a S4R shunt drive circuit, an outputted charge drive signal G2 is connected with a charge drive circuit, and the logic control is realized. The topology of the logic control implementation principle provided by the invention is simple and easy to understand, and the engineering thereof is easy to realize, therefore the logic control implementation principle has an important engineering application value for the solar array regulation technique for satellites.

Description

A kind of S 4r logic control circuit and logic control implementation method thereof
Technical field
The invention belongs to sun battle array regulable control technical field, particularly relate to a kind of S 4r(SeriesSequentialSwitchingShuntRegulator, tandem type sequence switch parallel regulator) logic control circuit and logic control implementation method thereof.
Background technology
On general satellite, sun battle array regulates and adopts S 4r regulating and controlling circuit.Such as CN201310108239 discloses a kind of S 4r type power control, this device comprises: shunting circuit, circuit for generating triangular wave, logic control circuit, charging control circuit, charge switch pipe, diverting switch pipe etc.It realizes logic control method by comparator, triode etc., and the method carries out the conversion of logic level by the conducting of triode and shutoff, realizes S 4the control logic of R.But this logic control method needs device many, is realizing multichannel S 4in R circuit, advantage is not obvious.
Summary of the invention
The object of the present invention is to provide a kind of circuit topological structure simple, be easy to the S of Project Realization 4r logic control circuit and logic control implementation method thereof.
In order to arrive above-mentioned purpose, a technical scheme of the present invention is to provide a kind of S 4r logic control circuit, it comprises:
Four NOR gate, it has two inputs and an output separately;
Wherein, complete two inputs adjusting bus control signal FG1 to be connected to the first NOR gate;
The signal P1 of the output of the first NOR gate is connected to the first input end of the second NOR gate and the first input end of the 3rd NOR gate respectively;
Charging control signal FG2 is connected to the second input of the 3rd NOR gate;
The signal P2 of the output of the 3rd NOR gate is connected to the second input of the second NOR gate respectively, two inputs of four nor gate;
The output output steering drive singal G1 of the second NOR gate;
The output of four nor gate exports charging drive singal G2;
Wherein, G1=^ (P1+P2)=(^P1) & (^P2)=(FG1) & (^FG1+FG2)=(FG1) & (FG2);
G2=^P2=P1+FG2=FG2+^FG1。
Another technical scheme of the present invention is to provide a kind of S 4r logic control circuit, it comprises:
Three NAND gate, it has two inputs and an output separately;
Wherein, the full bus control signal FG1 that adjusts is connected to the first input end of the first NAND gate and the second input of the 3rd NAND gate respectively;
Charging control signal FG2 is connected to the second input of the first NAND gate;
The signal Q1 of the output of the first NAND gate, is connected to two inputs of the second NAND gate and the first input end of the 3rd NAND gate respectively;
The output output steering drive singal G1 of the second NAND gate;
The output of the 3rd NAND gate exports charging drive singal G2;
Wherein, G1=^ (Q1)=(FG1) & (FG2),
G2=^(Q1&FG1)=^((^FG1+^FG2)&FG1)=FG2+^FG1。
Of the present invention also have a technical scheme to be to provide a kind of S 4r logic control implementation method, by any one S above-mentioned 4r logic control circuit, receives tune bus control signal FG1, charging control signal FG2 entirely respectively and carries out logical operation, obtains shunting drive singal G1 and charging drive singal G2;
Wherein, G1=FG1 & FG2, G2=FG2+(^FG1);
Shunting drive singal G1 is delivered to S 4r shunts drive circuit, and charging drive singal G2 is delivered to charging drive circuit.
Preferably, described full tune bus control signal FG1 shows entirely to adjust bus required power for " 0 ", entirely adjusts bus not required power for " 1 " shows;
Described charging control signal FG2 shows batteries required power, for " 1 " shows batteries not required power for " 0 ";
Described shunting drive singal G1 pours off for " 1 " shows that sun battle array power divides Power Groud, does not shunt over the ground for " 0 " shows sun battle array power;
Described charging drive singal G2 shows that sun battle array is to battery charging, for " 1 " shows that sun battle array is not to battery charging for " 0 ".
Compared with prior art, S of the present invention 4r logic control circuit and logic control implementation method, its advantage is: the present invention can realize this logic control method by 4 tunnel 2 in-gate circuits, and adopt chip to be NAND gate or NOR gate, device only needs one, saves cost.Circuit topology is easily understood simultaneously, and Project Realization is easy, has important engineer applied be worth satellite sun battle array regulation technology.
Accompanying drawing explanation
S provided by the invention 4r logic control circuit and logic control implementation method are provided by following examples and accompanying drawing.
Fig. 1 is that the present invention adopts 4 tunnels 2 to input the schematic diagram of logic control circuit in the first example of NOR gate realization;
Fig. 2 is the schematic diagram of logic control circuit in the second example that the present invention adopts 4 tunnel 2 input nand gates realizations;
Fig. 3 is the logic true value table that the present invention realizes.
Embodiment
Describe in detail bright below with reference to Fig. 1 ~ Fig. 3 further to logic control circuit of the present invention and implementation method.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
S provided by the invention 4in R logic control circuit and implementation method, two inputs of described logic control circuit adjust bus control signal FG1 and charging control signal FG2 to be connected respectively with entirely, after logical operation, see the logic true value table of Fig. 3, realize G1=FG1 & FG2, G2=FG2+(^FG1).Wherein, output is made to shunt drive singal G1 and S 4r shunts drive circuit and is connected, and charging drive singal G2 is connected with charging drive circuit.
Described FG1 shows entirely to adjust bus required power for " 0 ", entirely adjusts bus not required power for " 1 " shows; Described FG2 shows batteries required power, for " 1 " shows batteries not required power for " 0 "; Described G1 pours off for " 1 " shows that sun battle array power divides Power Groud, does not shunt over the ground for " 0 " shows sun battle array power; Described G2 shows that sun battle array is to battery charging, for " 1 " shows that sun battle array is not to battery charging for " 0 ".
After described FG1, FG2 enter logical circuit computing, output signal G1, G2 realize S 4the control logic of R.
Embodiment one
Be illustrated in figure 1 the logic control circuit that employing 4 tunnel 2 inputs NOR gate realization, two inputs comprising the first NOR gate connect FG1 respectively, and the signal P1 of its output connects the first input end of the second NOR gate respectively, and the first input end of the 3rd NOR gate; Second input of the second NOR gate connects FG2, and the signal P2 of its output connects the second input of the second NOR gate respectively, and two of four nor gate inputs; Second NOR gate output signal G1, four nor gate output signal G2.
Wherein, after described FG1, FG2 enter logical circuit: P1=^FG1, P2=^ (P1+FG2),
Therefore, G1=^ (P1+P2)=(^P1) & (^P2)=(FG1) & (^FG1+FG2)=(FG1) & (FG2),
G2=^P2=P1+FG2=FG2+^FG1。
There is provided signal G1, G2 to S respectively 4r shunts drive circuit and charging drive circuit, realizes S 4r logic control method.
Embodiment two
Be illustrated in figure 2 the logic control circuit that employing 4 tunnel 2 input nand gate realizes, two inputs comprising the first NAND gate connect FG1, FG2 respectively, the signal Q1 of output connects two inputs of the second NAND gate and the first input end of the 3rd NAND gate respectively, and the second input of the 3rd NAND gate connects FG1; Second NAND gate exports G1, and the 3rd NAND gate exports G2.
Wherein, after described FG1, FG2 enter logical circuit: Q1=^ (FG1 & FG2),
Therefore, G1=^ (Q1)=(FG1) & (FG2),
G2=^(Q1&FG1)=^((^FG1+^FG2)&FG1)=FG2+^FG1。
There is provided signal G1, G2 to S respectively 4r shunts drive circuit and charging drive circuit, realizes S 4r logic control method.

Claims (4)

1. a S 4r logic control circuit, is characterized in that, comprises:
Four NOR gate, it has two inputs and an output separately;
Wherein, complete two inputs adjusting bus control signal FG1 to be connected to the first NOR gate;
The signal P1 of the output of the first NOR gate is connected to the first input end of the second NOR gate and the first input end of the 3rd NOR gate respectively;
Charging control signal FG2 is connected to the second input of the 3rd NOR gate;
The signal P2 of the output of the 3rd NOR gate is connected to the second input of the second NOR gate respectively, two inputs of four nor gate;
The output output steering drive singal G1 of the second NOR gate;
The output of four nor gate exports charging drive singal G2;
Wherein, G1=^ (P1+P2)=(^P1) & (^P2)=(FG1) & (^FG1+FG2)=(FG1) & (FG2);
G2=^P2=P1+FG2=FG2+^FG1。
2. a S 4r logic control circuit, is characterized in that, comprises:
Three NAND gate, it has two inputs and an output separately;
Wherein, the full bus control signal FG1 that adjusts is connected to the first input end of the first NAND gate and the second input of the 3rd NAND gate respectively;
Charging control signal FG2 is connected to the second input of the first NAND gate;
The signal Q1 of the output of the first NAND gate, is connected to two inputs of the second NAND gate and the first input end of the 3rd NAND gate respectively;
The output output steering drive singal G1 of the second NAND gate;
The output of the 3rd NAND gate exports charging drive singal G2;
Wherein, G1=^ (Q1)=(FG1) & (FG2),
G2=^(Q1&FG1)=^((^FG1+^FG2)&FG1)=FG2+^FG1。
3. a S 4r logic control implementation method, is characterized in that,
By the S of claim 1 or 2 4r logic control circuit, receives tune bus control signal FG1, charging control signal FG2 entirely respectively and carries out logical operation, obtains shunting drive singal G1 and charging drive singal G2;
Wherein, G1=FG1 & FG2, G2=FG2+(^FG1);
Shunting drive singal G1 is delivered to S 4r shunts drive circuit, and charging drive singal G2 is delivered to charging drive circuit.
4. S as claimed in claim 3 4r logic control implementation method, is characterized in that,
Described full tune bus control signal FG1 shows entirely to adjust bus required power for " 0 ", entirely adjusts bus not required power for " 1 " shows;
Described charging control signal FG2 shows batteries required power, for " 1 " shows batteries not required power for " 0 ";
Described shunting drive singal G1 pours off for " 1 " shows that sun battle array power divides Power Groud, does not shunt over the ground for " 0 " shows sun battle array power;
Described charging drive singal G2 shows that sun battle array is to battery charging, for " 1 " shows that sun battle array is not to battery charging for " 0 ".
CN201510820843.0A 2015-11-24 2015-11-24 A kind of S4R logic control circuits and its logic control implementation method Active CN105262477B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510820843.0A CN105262477B (en) 2015-11-24 2015-11-24 A kind of S4R logic control circuits and its logic control implementation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510820843.0A CN105262477B (en) 2015-11-24 2015-11-24 A kind of S4R logic control circuits and its logic control implementation method

Publications (2)

Publication Number Publication Date
CN105262477A true CN105262477A (en) 2016-01-20
CN105262477B CN105262477B (en) 2017-12-19

Family

ID=55102014

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510820843.0A Active CN105262477B (en) 2015-11-24 2015-11-24 A kind of S4R logic control circuits and its logic control implementation method

Country Status (1)

Country Link
CN (1) CN105262477B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040095113A1 (en) * 2002-11-14 2004-05-20 Fyre Storm, Inc Power converter circuitry and method
CN103116535A (en) * 2011-11-17 2013-05-22 上海航天测控通信研究所 Satellite-bone dual-redundant computer mainframe working condition monitoring and fault autonomous switching device
CN104319838A (en) * 2014-10-20 2015-01-28 上海空间电源研究所 Overcharge protection circuit and method of series sequential switching shunt regulator
CN104410038A (en) * 2014-10-21 2015-03-11 上海空间电源研究所 Overvoltage protection circuit for discharge regulating circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040095113A1 (en) * 2002-11-14 2004-05-20 Fyre Storm, Inc Power converter circuitry and method
CN103116535A (en) * 2011-11-17 2013-05-22 上海航天测控通信研究所 Satellite-bone dual-redundant computer mainframe working condition monitoring and fault autonomous switching device
CN104319838A (en) * 2014-10-20 2015-01-28 上海空间电源研究所 Overcharge protection circuit and method of series sequential switching shunt regulator
CN104410038A (en) * 2014-10-21 2015-03-11 上海空间电源研究所 Overvoltage protection circuit for discharge regulating circuit

Also Published As

Publication number Publication date
CN105262477B (en) 2017-12-19

Similar Documents

Publication Publication Date Title
CN104112473B (en) A kind of low-power consumption rapid pressure FLASH control electrical appliances for electric charge pump
CN105391301B (en) A kind of PCU control system of the two-way multiport converter based on wide-voltage range
CN105281545B (en) A kind of flexible direct current converter valve and its bridge arm damping module take can circuit
WO2009091474A8 (en) Hybrid on-chip regulator for limited output high voltage
CN106407138B (en) A kind of LVDS interface and DSI interface multiplexing circuit
CN105932873A (en) Low-power and high-output voltage charge pump
CN104796098A (en) GaN power device drain electrode modulation circuit
CN104821782B (en) Software-hardware combined shunting control device and method
CN104917359B (en) A kind of upper switch tube driving circuit and apply its synchronous boost circuits
CN106027008A (en) Shoot-through preventing circuit of high-voltage drive circuit
CN104702181A (en) H-bridge driving circuit and control method thereof
CN102723658A (en) Constant current source power supplying circuit of laser
CN107040250A (en) A kind of voltage mode drive circuit
CN104269915B (en) Multi-solar-array unified regulation and control method
CN105262477A (en) S4R (Series Sequential Switching Shunt Regulator) logic control circuit and logic control implementation method thereof
CN104836548B (en) The input circuit that the Duty Cycle Distortion of input signal can be compensated
CN102324928B (en) Frequency calibration circuit of active RC (Resistor-Capacitor) filter
CN105592605A (en) LED load driving circuit
CN102075177B (en) Method for producing non-overlapping signal with reasonable dead-zone time
CN104393754A (en) Shunting control circuit of spacecraft power supply system and method thereof
CN204578496U (en) The input circuit that can compensate the Duty Cycle Distortion of input signal
CN208739097U (en) Level displacement circuit based on low-voltage tube
CN102769285B (en) PV module parallel array and method for realizing voltage autotracking
CN112838660A (en) Solar charging circuit, charging method, electronic device and storage medium
CN202712849U (en) PV module parallel array

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant