CN105262477A - S4R (Series Sequential Switching Shunt Regulator) logic control circuit and logic control implementation method thereof - Google Patents
S4R (Series Sequential Switching Shunt Regulator) logic control circuit and logic control implementation method thereof Download PDFInfo
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- CN105262477A CN105262477A CN201510820843.0A CN201510820843A CN105262477A CN 105262477 A CN105262477 A CN 105262477A CN 201510820843 A CN201510820843 A CN 201510820843A CN 105262477 A CN105262477 A CN 105262477A
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Abstract
The present invention relates to an S4R (Series Sequential Switching Shunt Regulator) logic control circuit and a logic control implementation method thereof. The input end of the logic control circuit is connected with a complete modulation control signal FG1 and a charge control signal FG2, and the formulas, G1=FG1&FG2 and G2=FG2 + (^FG1), are realized after logic operation; and a shunt drive signal G1 outputted via the output end of the logic control circuit is connected with a S4R shunt drive circuit, an outputted charge drive signal G2 is connected with a charge drive circuit, and the logic control is realized. The topology of the logic control implementation principle provided by the invention is simple and easy to understand, and the engineering thereof is easy to realize, therefore the logic control implementation principle has an important engineering application value for the solar array regulation technique for satellites.
Description
Technical field
The invention belongs to sun battle array regulable control technical field, particularly relate to a kind of S
4r(SeriesSequentialSwitchingShuntRegulator, tandem type sequence switch parallel regulator) logic control circuit and logic control implementation method thereof.
Background technology
On general satellite, sun battle array regulates and adopts S
4r regulating and controlling circuit.Such as CN201310108239 discloses a kind of S
4r type power control, this device comprises: shunting circuit, circuit for generating triangular wave, logic control circuit, charging control circuit, charge switch pipe, diverting switch pipe etc.It realizes logic control method by comparator, triode etc., and the method carries out the conversion of logic level by the conducting of triode and shutoff, realizes S
4the control logic of R.But this logic control method needs device many, is realizing multichannel S
4in R circuit, advantage is not obvious.
Summary of the invention
The object of the present invention is to provide a kind of circuit topological structure simple, be easy to the S of Project Realization
4r logic control circuit and logic control implementation method thereof.
In order to arrive above-mentioned purpose, a technical scheme of the present invention is to provide a kind of S
4r logic control circuit, it comprises:
Four NOR gate, it has two inputs and an output separately;
Wherein, complete two inputs adjusting bus control signal FG1 to be connected to the first NOR gate;
The signal P1 of the output of the first NOR gate is connected to the first input end of the second NOR gate and the first input end of the 3rd NOR gate respectively;
Charging control signal FG2 is connected to the second input of the 3rd NOR gate;
The signal P2 of the output of the 3rd NOR gate is connected to the second input of the second NOR gate respectively, two inputs of four nor gate;
The output output steering drive singal G1 of the second NOR gate;
The output of four nor gate exports charging drive singal G2;
Wherein, G1=^ (P1+P2)=(^P1) & (^P2)=(FG1) & (^FG1+FG2)=(FG1) & (FG2);
G2=^P2=P1+FG2=FG2+^FG1。
Another technical scheme of the present invention is to provide a kind of S
4r logic control circuit, it comprises:
Three NAND gate, it has two inputs and an output separately;
Wherein, the full bus control signal FG1 that adjusts is connected to the first input end of the first NAND gate and the second input of the 3rd NAND gate respectively;
Charging control signal FG2 is connected to the second input of the first NAND gate;
The signal Q1 of the output of the first NAND gate, is connected to two inputs of the second NAND gate and the first input end of the 3rd NAND gate respectively;
The output output steering drive singal G1 of the second NAND gate;
The output of the 3rd NAND gate exports charging drive singal G2;
Wherein, G1=^ (Q1)=(FG1) & (FG2),
G2=^(Q1&FG1)=^((^FG1+^FG2)&FG1)=FG2+^FG1。
Of the present invention also have a technical scheme to be to provide a kind of S
4r logic control implementation method, by any one S above-mentioned
4r logic control circuit, receives tune bus control signal FG1, charging control signal FG2 entirely respectively and carries out logical operation, obtains shunting drive singal G1 and charging drive singal G2;
Wherein, G1=FG1 & FG2, G2=FG2+(^FG1);
Shunting drive singal G1 is delivered to S
4r shunts drive circuit, and charging drive singal G2 is delivered to charging drive circuit.
Preferably, described full tune bus control signal FG1 shows entirely to adjust bus required power for " 0 ", entirely adjusts bus not required power for " 1 " shows;
Described charging control signal FG2 shows batteries required power, for " 1 " shows batteries not required power for " 0 ";
Described shunting drive singal G1 pours off for " 1 " shows that sun battle array power divides Power Groud, does not shunt over the ground for " 0 " shows sun battle array power;
Described charging drive singal G2 shows that sun battle array is to battery charging, for " 1 " shows that sun battle array is not to battery charging for " 0 ".
Compared with prior art, S of the present invention
4r logic control circuit and logic control implementation method, its advantage is: the present invention can realize this logic control method by 4 tunnel 2 in-gate circuits, and adopt chip to be NAND gate or NOR gate, device only needs one, saves cost.Circuit topology is easily understood simultaneously, and Project Realization is easy, has important engineer applied be worth satellite sun battle array regulation technology.
Accompanying drawing explanation
S provided by the invention
4r logic control circuit and logic control implementation method are provided by following examples and accompanying drawing.
Fig. 1 is that the present invention adopts 4 tunnels 2 to input the schematic diagram of logic control circuit in the first example of NOR gate realization;
Fig. 2 is the schematic diagram of logic control circuit in the second example that the present invention adopts 4 tunnel 2 input nand gates realizations;
Fig. 3 is the logic true value table that the present invention realizes.
Embodiment
Describe in detail bright below with reference to Fig. 1 ~ Fig. 3 further to logic control circuit of the present invention and implementation method.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
S provided by the invention
4in R logic control circuit and implementation method, two inputs of described logic control circuit adjust bus control signal FG1 and charging control signal FG2 to be connected respectively with entirely, after logical operation, see the logic true value table of Fig. 3, realize G1=FG1 & FG2, G2=FG2+(^FG1).Wherein, output is made to shunt drive singal G1 and S
4r shunts drive circuit and is connected, and charging drive singal G2 is connected with charging drive circuit.
Described FG1 shows entirely to adjust bus required power for " 0 ", entirely adjusts bus not required power for " 1 " shows; Described FG2 shows batteries required power, for " 1 " shows batteries not required power for " 0 "; Described G1 pours off for " 1 " shows that sun battle array power divides Power Groud, does not shunt over the ground for " 0 " shows sun battle array power; Described G2 shows that sun battle array is to battery charging, for " 1 " shows that sun battle array is not to battery charging for " 0 ".
After described FG1, FG2 enter logical circuit computing, output signal G1, G2 realize S
4the control logic of R.
Embodiment one
Be illustrated in figure 1 the logic control circuit that employing 4 tunnel 2 inputs NOR gate realization, two inputs comprising the first NOR gate connect FG1 respectively, and the signal P1 of its output connects the first input end of the second NOR gate respectively, and the first input end of the 3rd NOR gate; Second input of the second NOR gate connects FG2, and the signal P2 of its output connects the second input of the second NOR gate respectively, and two of four nor gate inputs; Second NOR gate output signal G1, four nor gate output signal G2.
Wherein, after described FG1, FG2 enter logical circuit: P1=^FG1, P2=^ (P1+FG2),
Therefore, G1=^ (P1+P2)=(^P1) & (^P2)=(FG1) & (^FG1+FG2)=(FG1) & (FG2),
G2=^P2=P1+FG2=FG2+^FG1。
There is provided signal G1, G2 to S respectively
4r shunts drive circuit and charging drive circuit, realizes S
4r logic control method.
Embodiment two
Be illustrated in figure 2 the logic control circuit that employing 4 tunnel 2 input nand gate realizes, two inputs comprising the first NAND gate connect FG1, FG2 respectively, the signal Q1 of output connects two inputs of the second NAND gate and the first input end of the 3rd NAND gate respectively, and the second input of the 3rd NAND gate connects FG1; Second NAND gate exports G1, and the 3rd NAND gate exports G2.
Wherein, after described FG1, FG2 enter logical circuit: Q1=^ (FG1 & FG2),
Therefore, G1=^ (Q1)=(FG1) & (FG2),
G2=^(Q1&FG1)=^((^FG1+^FG2)&FG1)=FG2+^FG1。
There is provided signal G1, G2 to S respectively
4r shunts drive circuit and charging drive circuit, realizes S
4r logic control method.
Claims (4)
1. a S
4r logic control circuit, is characterized in that, comprises:
Four NOR gate, it has two inputs and an output separately;
Wherein, complete two inputs adjusting bus control signal FG1 to be connected to the first NOR gate;
The signal P1 of the output of the first NOR gate is connected to the first input end of the second NOR gate and the first input end of the 3rd NOR gate respectively;
Charging control signal FG2 is connected to the second input of the 3rd NOR gate;
The signal P2 of the output of the 3rd NOR gate is connected to the second input of the second NOR gate respectively, two inputs of four nor gate;
The output output steering drive singal G1 of the second NOR gate;
The output of four nor gate exports charging drive singal G2;
Wherein, G1=^ (P1+P2)=(^P1) & (^P2)=(FG1) & (^FG1+FG2)=(FG1) & (FG2);
G2=^P2=P1+FG2=FG2+^FG1。
2. a S
4r logic control circuit, is characterized in that, comprises:
Three NAND gate, it has two inputs and an output separately;
Wherein, the full bus control signal FG1 that adjusts is connected to the first input end of the first NAND gate and the second input of the 3rd NAND gate respectively;
Charging control signal FG2 is connected to the second input of the first NAND gate;
The signal Q1 of the output of the first NAND gate, is connected to two inputs of the second NAND gate and the first input end of the 3rd NAND gate respectively;
The output output steering drive singal G1 of the second NAND gate;
The output of the 3rd NAND gate exports charging drive singal G2;
Wherein, G1=^ (Q1)=(FG1) & (FG2),
G2=^(Q1&FG1)=^((^FG1+^FG2)&FG1)=FG2+^FG1。
3. a S
4r logic control implementation method, is characterized in that,
By the S of claim 1 or 2
4r logic control circuit, receives tune bus control signal FG1, charging control signal FG2 entirely respectively and carries out logical operation, obtains shunting drive singal G1 and charging drive singal G2;
Wherein, G1=FG1 & FG2, G2=FG2+(^FG1);
Shunting drive singal G1 is delivered to S
4r shunts drive circuit, and charging drive singal G2 is delivered to charging drive circuit.
4. S as claimed in claim 3
4r logic control implementation method, is characterized in that,
Described full tune bus control signal FG1 shows entirely to adjust bus required power for " 0 ", entirely adjusts bus not required power for " 1 " shows;
Described charging control signal FG2 shows batteries required power, for " 1 " shows batteries not required power for " 0 ";
Described shunting drive singal G1 pours off for " 1 " shows that sun battle array power divides Power Groud, does not shunt over the ground for " 0 " shows sun battle array power;
Described charging drive singal G2 shows that sun battle array is to battery charging, for " 1 " shows that sun battle array is not to battery charging for " 0 ".
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Citations (4)
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US20040095113A1 (en) * | 2002-11-14 | 2004-05-20 | Fyre Storm, Inc | Power converter circuitry and method |
CN103116535A (en) * | 2011-11-17 | 2013-05-22 | 上海航天测控通信研究所 | Satellite-bone dual-redundant computer mainframe working condition monitoring and fault autonomous switching device |
CN104319838A (en) * | 2014-10-20 | 2015-01-28 | 上海空间电源研究所 | Overcharge protection circuit and method of series sequential switching shunt regulator |
CN104410038A (en) * | 2014-10-21 | 2015-03-11 | 上海空间电源研究所 | Overvoltage protection circuit for discharge regulating circuit |
-
2015
- 2015-11-24 CN CN201510820843.0A patent/CN105262477B/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040095113A1 (en) * | 2002-11-14 | 2004-05-20 | Fyre Storm, Inc | Power converter circuitry and method |
CN103116535A (en) * | 2011-11-17 | 2013-05-22 | 上海航天测控通信研究所 | Satellite-bone dual-redundant computer mainframe working condition monitoring and fault autonomous switching device |
CN104319838A (en) * | 2014-10-20 | 2015-01-28 | 上海空间电源研究所 | Overcharge protection circuit and method of series sequential switching shunt regulator |
CN104410038A (en) * | 2014-10-21 | 2015-03-11 | 上海空间电源研究所 | Overvoltage protection circuit for discharge regulating circuit |
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