CN105261659A - Solar cell and manufacturing method thereof - Google Patents

Solar cell and manufacturing method thereof Download PDF

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Publication number
CN105261659A
CN105261659A CN201510768850.0A CN201510768850A CN105261659A CN 105261659 A CN105261659 A CN 105261659A CN 201510768850 A CN201510768850 A CN 201510768850A CN 105261659 A CN105261659 A CN 105261659A
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solar cell
layer
semiconductor layer
ohmic electrode
expansion
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Inventor
杨美佳
毕京锋
李森林
刘冠洲
李明阳
熊伟平
陈文浚
吴超瑜
王笃祥
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Tianjin Sanan Optoelectronics Co Ltd
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Tianjin Sanan Optoelectronics Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0224Electrodes
    • H01L31/022408Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0216Coatings
    • H01L31/02161Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
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  • Power Engineering (AREA)
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  • Sustainable Energy (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Photovoltaic Devices (AREA)

Abstract

The invention provides a solar cell and a manufacturing method thereof. The solar cell comprises a substrate, a bonding metal layer arranged on the substrate, an ohmic contact metal layer, a stress barrier layer, a solar cell semiconductor layer arranged on the stress barrier layer and an ohmic electrode arranged on an upper surface of the solar cell semiconductor layer. The stress barrier layer is arranged between the solar cell semiconductor layer and the ohmic contact metal layer so that a thermal stress of the ohmic contact metal layer and the bonding metal layer to the solar cell semiconductor layer can be effectively obstructed. Conditions that the thermal stress makes crystalline quality of the solar cell semiconductor layer becomes poor and even a band gap generates offset are avoided.

Description

Solar cell and preparation method thereof
Technical field
The invention belongs to semiconductor solar cell field, relate to upside-down mounting multijunction solar cell chip and preparation method thereof.
Background technology
The multijunction solar cell structural development that Group III-V compound semiconductor GaAs and base system multiple material thereof are formed is rapid, and owing to can substantially realize full spectral absorption, its photoelectric conversion efficiency is far ahead of other solar cells.And this material system possesses excellent radiation-resistant property and heat-resisting quantity, further increase its reliability in space application and useful life, day by day become the main force of space power system.And the multijunction solar cell of inverted structure more reasonably can distribute solar spectrum because of it, and then the current density of each sub-battery is more mated, reduce thermal resistance loss, improve open circuit voltage, be supposed to acquire higher solar energy conversion efficiency.
But photoelectric conversion layer will form back contacts with large-area metal in the chip technology process of upside-down mounting multijunction solar cell, be generally gold or other alloys.In technical process, the thermal volume expansion of metal and cooling meat volume are all greater than thermal volume expansion and the cooling meat volume of photoelectric conversion layer, larger swelling stress can be produced like this in the interface of back contacts, the crystal mass of photoelectric conversion layer is worsened, even band gap offsets, and affects light transfer characteristic.In upside-down mounting multijunction solar cell structure; the opto-electronic conversion performance of the end battery that distance back contacts metal is nearest is very crucial; usual meeting is because the crystal mass of end battery is bad; the short circuit current that end battery provides is on the low side; have impact on the overall performance of battery, so the performance of end battery directly determines the performance of whole multijunction cell.In this case, the effect of stress of back contacts metal pair battery just can not be ignored.At present for the situation that end battery performance in upside-down mounting multijunction cell is poor, most of ameliorative way is all aimed at epitaxial growth aspect, and the research of chip technology aspect is little.
Summary of the invention
For the problems referred to above, the invention provides a kind of solar battery structure and the manufacture method thereof that can avoid the thermal stress that the generation of back contacts interface is larger.
In order to achieve the above object, the structure that the present inventor is conceived to back contacts is studied, and propose the present invention: by arranging stress barrier layer between solar cell semiconductor layer and bonding metal layer, avoid solar cell semiconductor layer to be directly subject to the swelling stress of metal.
The technical scheme that the present invention solves the problem is: solar cell, comprising: substrate, arrange bonding metal layer on the substrate, ohmic electrode layer, stress barrier layer, be arranged on the solar cell semiconductor layer on this stress barrier layer and be arranged on the Ohmic electrode of described solar cell semiconductor layer upper surface.Wherein, described stress barrier layer is arranged between described solar cell semiconductor layer and Ohm contact electrode metal level, prevents because ohmic electrode layer and thermal stress that between bonding metal layer and semiconductor layer, the difference of thermal coefficient of expansion produces make the poor crystal quality of semiconductor layer.
In certain embodiments, described solar cell semiconductor layer is upside-down mounting multijunction structure, comprises successively: the first solar subcells, and it has the first band gap; Second solar subcells, it to be arranged on below described first sub-battery and to have the second band gap being less than described first band gap; Graded buffer layer, being arranged on below described second sub-battery and having multistage interlayer, the lattice constant classification of this multistage interlayer becomes large gradually; 3rd solar subcells, it is arranged on below described graded buffer layer, and it corresponds to described second sub-battery lattice mismatch and has the 3rd band gap being less than described second band gap.In a particular embodiment, described multijunction structure can be the sub-battery of (Al) GaInP first, Ga(In) the sub-battery of As second, InAlGaAs graded buffer layer and InGaAs the 3rd sub-battery.
Preferably, described stress barrier layer is configured to the thin-film material comprising multiple hole, described hole follow-up filling ohmic electrode layer material.
Preferably, the ratio of whole stress barrier layer area shared by the perforated of described stress barrier layer is determined according to the thermal coefficient of expansion ratio of selected stress barrier material and solar cell semiconductor material.
Preferably, the thermal coefficient of expansion setting described solar cell semiconductor layer is T 1, the thermal coefficient of expansion of described stress barrier layer is T 2, the thermal coefficient of expansion of described ohmic electrode layer is T 3, the hole area occupied ratio of described stress barrier layer is X, then meet: T 3* X+T 2(1-X)=T 1.
Preferably, described stress barrier layer is made up of thermal coefficient of expansion and solar cell semiconductor layer similar thermal expansion coefficient or the thin-film material more smaller than solar cell semiconductor material thermal expansion coefficient.
Preferably, described stress barrier layer is made up of the metallic film material of thermal coefficient of expansion and solar cell semiconductor layer similar thermal expansion coefficient, or the dielectric thin-film material more smaller than solar cell semiconductor material thermal expansion coefficient is formed.
Preferably, employing thermal coefficient of expansion and the metal material of solar cell semiconductor layer similar thermal expansion coefficient are if Mo, W, Cr etc. or the dielectric thin-film material more smaller than solar cell semiconductor material thermal expansion coefficient are as SiO 2, Si 3n 4, TiO 2, Al 2o 3deng as described stress barrier layer.
Preferably, described substrate adopts any one in Ge substrate, Si substrate, GaP substrate, SiC substrate or metal substrate.
The present invention also provides a kind of preparation method of solar cell, comprise step: form solar cell semiconductor layer on a substrate, described solar cell semiconductor layer arranges stress barrier layer and Ohm contact electrode, the surface of this solar cell semiconductor layer makes Ohmic electrode.Wherein said stress barrier layer is between described solar cell semiconductor layer and ohmic electrode layer.
Preferably, adopt the method that photoetching combines with evaporation or PECVD etc. combines with photoetching on described solar cell semiconductor layer, prepare the stress barrier layer with multiple hole.
Preferably, on described stress barrier layer and make ohmic electrode layer among hole, its material can be the metal material one wherein such as Ti/Au, Ti/Pt/Au, Pt/Ti/Au, AuBe, AuZn, better selection AuZn.
The solar cell of the present invention, stress barrier layer is set between solar cell semiconductor layer and ohmic contact metal layer, effectively can intercept ohmic contact metal layer and bonding metal layer to the thermal stress of solar cell semiconductor layer, avoid thermal stress that solar cell semiconductor layer poor crystal quality, even band gap are offset.The present invention is particularly useful for upside-down mounting multijunction solar cell, because end battery performance is very crucial in upside-down mounting multijunction solar cell, usually determines the overall performance of solar cell.
Accompanying drawing explanation
Below use accompanying drawing to provide a further understanding of the present invention, application upside-down mounting multijunction solar cell of the present invention and manufacture method thereof together with embodiments of the present invention, but be not construed as limiting the invention.
Figure 1 shows that the schematic cross-section according to upside-down mounting multijunction solar cell of the invention process.
Figure 2 shows that according to the upside-down mounting multijunction solar cell semiconductor layer comprising the first sub-battery, the second sub-battery, graded buffer layer and the 3rd sub-battery formed on growth substrate of the invention process.
Figure 3 shows that the multijunction solar cell of upside-down mounting shown in Fig. 2 is according to the cross-sectional view after subsequent processing of the present invention, begins to take shape the film material of stress barrier layer in this operation.
Figure 4 shows that the multijunction solar cell of upside-down mounting shown in Fig. 3 is according to the cross-sectional view after subsequent processing of the present invention, forms the structure that stress barrier layer has multiple hole in this operation.
Fig. 5 is the vertical view of the stress barrier layer with multiple pore space structure.
Figure 6 shows that the multijunction solar cell of upside-down mounting shown in Fig. 4 is according to the cross-sectional view after subsequent processing of the present invention, forms ohmic electrode layer in this operation.
Figure 7 shows that the multijunction solar cell of upside-down mounting shown in Fig. 6 is according to the cross-sectional view after subsequent processing of the present invention, forms semiconductor layer bonding metallic layer and supporting substrate bonding metallic layer in this operation.
Figure 8 shows that the multijunction solar cell of upside-down mounting shown in Fig. 7 is according to the cross-sectional view after subsequent processing of the present invention, joint support substrate in this operation.
Figure 9 shows that the multijunction solar cell of upside-down mounting shown in Fig. 7 is according to the cross-sectional view after subsequent processing of the present invention, removes growth substrate in this operation.
Figure 10 shows that the multijunction solar cell of upside-down mounting shown in Fig. 9 is according to the cross-sectional view after subsequent processing of the present invention, forms Ohmic electrode in this operation.
Figure 11 shows that another schematic top plan view of upside-down mounting multijunction solar cell stress barrier layer.
In figure, each label represents:
001: growth substrate
002: multijunction solar cell semiconductor layer
003: supporting substrate
004: Ohmic electrode
200: etching cut-off layer
201: ohmic contact layer
202: the first sub-batteries
203: the second sub-batteries
204: graded buffer layer
205: the three sub-batteries
206: heavy doping cap
301: stress barrier layer
302: ohmic electrode layer
303: semiconductor layer is in conjunction with metal level
304: supporting substrate bonding metallic layer
301a: the inwall of stress barrier layer hole
302a: Ohm contact electrode fills the part of the hole of stress barrier layer.
Embodiment
Below, accompanying drawing application upside-down mounting multijunction solar cell structure of the present invention and preparation method thereof is used.The accompanying drawing used in the following description amplifies in order to easy understand feature the part illustrating and become feature sometimes for simplicity, and the dimensional ratios of each inscape etc. may not be identical with reality.In addition, illustrated in the following description material, size etc. are examples, and the present invention is not limited to these, suitably can change and implement in the scope not changing its purport.
[upside-down mounting multijunction solar cell]
Fig. 1 is the schematic cross-section of the example representing upside-down mounting multijunction solar cell of the present invention.
The upside-down mounting multijunction solar cell of present embodiment, comprises supporting substrate 003, multijunction solar cell semiconductor layer 002, Ohmic electrode 004, stress barrier layer 301.Wherein multijunction solar cell semiconductor layer 002 comprises the first solar subcells 202, second solar subcells 203, graded buffer layer 204, the 3rd solar subcells 205.In the upside-down mounting multijunction solar cell structure shown in Fig. 1, from between supporting substrate 003 and multijunction solar cell semiconductor layer 002, from supporting substrate 003 side, be followed successively by supporting substrate binder course 304, semiconductor layer binder course 303, ohmic electrode layer 302, stress barrier layer 301.
< upside-down mounting multijunction solar cell semiconductor layer >
Figure 1 shows that according to upside-down mounting multijunction solar cell structure of the invention process, wherein 002 is solar cell semiconductor layer, comprises etching cut-off layer 200, GaAs ohmic contact layer 201, first solar subcells 202, second solar subcells 203, graded buffer layer 204, the 3rd solar subcells 205.
Growth substrate 001 can be GaAs (GaAs), germanium (Ge) or other suitable materials.
Etching cut-off layer 200, when removing growth substrate, the layer of function is played as limiter, if growth substrate selects GaAs, adopt ammoniacal liquor hydrogen peroxide mixed solution or phosphoric acid hydrogen peroxide mixed solution when then removing GaAs substrate, at this moment the material of etching cut-off layer can be grown to serve as (Al) GaInP.
Ohmic contact layer 201 is layers of the contact resistance for reducing Ohmic electrode, and can be grown to serve as the N-shaped GaAs layer being doped with Si, carrier concentration is 1 × 10 18cm -3.
First solar subcells 202, has the first band gap (about 1.9eV), is preferably (Al) GaInP, specifically comprises n +alInP Window layer 202a, n +(Al) GaInP emitter region 202b, p +(Al) GaInP base 202c and p +alInGaP back surface field layer 202d.Then above back surface field layer (BSF) 202d, heavily doped p is grown ++/ n ++alGaAs tunnel junctions 202e, tunnel junctions 202e are the circuit elements in order to the first sub-battery to be connected to the second sub-battery.Al item in aforementioned Chemistry Figure bracket means that Al is optional member, and spendable in the case amount is the scope from 0 to 30%.
Second solar subcells 203, has the second band gap (about 1.5eV), is preferably Ga(In) As, specifically comprise n +alInP Window layer 203a, n +ga(In) As emitter region 203b, p +ga(In) As base 203c and p-type GaInP back surface field layer 203d, grows heavily doped p above the second sub-battery 203 ++/ n ++gaAs tunnel junctions 203e.In aforementioned Chemistry Figure bracket, In item means that In is optional member, and spendable in the case amount is the scope from 0 to 2%.
Graded buffer layer 204, comprises stress release layer In xal 0.4ga 0.6-xas(is divided into 10 layers, and every layer of In component increases progressively 0.03), stress equilibrium layer In 0.33al 0.4ga 0.27as and target lattice layer In 0.3al 0.4ga 0.3as, its effect realizes changing from the second sub-battery to the lattice constant of the 3rd sub-battery.
3rd solar subcells 205, has the 3rd band gap (about 1.0eV), specifically comprises n +gaInP Window layer 205a, n +in 0.3ga 0.7as emitter region 205b, p +in 0.3ga 0.7as base 205c and p +in 0.3al 0.4ga 0.3as back surface field layer 205d.
Highly doped p is grown above the 3rd sub-battery ++inGaAs cap, to make ohmic contact.
Each layer in above solar battery structure preferably adopts described material, but also can use other any materials meeting lattice constant and band gap requirement.In addition, those skilled in the art should understand, can add in above battery structure without departing from the present invention or delete layer.
< Ohmic electrode >
As shown in Figure 1, Ohmic electrode 004 is that be arranged on upside-down mounting multijunction solar cell semiconductor layer 002 with electrode that is supporting substrate 003 opposition side.The material of Ohmic electrode can use AuGe alloy, AuGeNi alloy, AuSi alloy, AuSiNi alloy, PdGeAu etc.
< ohmic electrode layer >
As shown in Figure 1, ohmic electrode layer 302 is arranged on the electrode between supporting substrate 003 and upside-down mounting multijunction solar cell semiconductor layer 002.The material of ohmic electrode layer can be Ti/Au, Ti/Pt/Au, Ti/Au/Ag/Au, AuBe, AuZn etc.
< bonding metallic layer >
In conjunction with the layer that metal level is for upside-down mounting multijunction solar cell semiconductor layer 002 grade and supporting substrate being joined together, comprise supporting substrate jointing metal 304 and semiconductor layer jointing metal 303.As bonding metallic layer, can be chemical stabilization, combine very firmly, Au system eutectic metal that fusing point is lower.Such as AuGe, AuSn, AuIn etc. also can be only use Au.In addition, in order to suppress the metal contained by jointing metal to be diffused into semiconductor layer, barrier layer can be set simultaneously, such as, can use the wherein alloy of two or more metal or the stepped construction such as Ni, Ti, Pt, Cr, W, Mo.
< stress barrier layer >
Stress barrier layer 301, be arranged between solar cell semiconductor layer 002 and ohmic electrode layer 302, prevent because ohmic electrode layer and thermal stress that between bonding metal layer and semiconductor layer, the difference of thermal coefficient of expansion produces make the poor crystal quality of semiconductor layer.
Stress barrier layer 301 is configured to the thin-film material comprising multiple hole, described hole follow-up filling Ohm contact electrode material 302a.The ratio of whole stress barrier layer area shared by the perforated of stress barrier layer is complied with the thermal coefficient of expansion ratio of selected stress barrier material and solar cell semiconductor material and determines.Such as our metallic film material Cr(thermal coefficient of expansion=4.9ppm/K of selecting thermal coefficient of expansion close with solar cell semiconductor layer thermal coefficient of expansion (as GaAs thermal coefficient of expansion=6.0ppm/K)) as stress barrier material, AuZn alloy (thermal coefficient of expansion=14.1ppm/K with reference to Au) is selected to be Ohm contact electrode material, then the hole area occupied ratio of stress barrier layer is 11.95%(14.1x+4.9 (1-x)=6.0, asks x).Other can select molybdenum (thermal coefficient of expansion=5.1ppm/K), tungsten (thermal coefficient of expansion=4.3ppm/K), and computational methods are similar.More preferably, the dielectric thin-film material that thermal coefficient of expansion is less than solar cell semiconductor material thermal expansion coefficient is selected, as SiO 2(thermal coefficient of expansion=0.5ppm/K), its refractive index is about 1.48, can form ODR full reflected system with solar cell semiconductor layer and metal ohmic contact (Au system alloy), then have the effect of the absorption of the light increasing end battery wave band further.
In the present embodiment, owing to being provided with stress blocking part between solar cell semiconductor functional layer and ohmic contact metal layer and bonding metal layer, so can prevent because ohmic electrode layer and thermal stress that between bonding metal layer and semiconductor layer, the difference of thermal coefficient of expansion produces make the poor crystal quality of semiconductor layer, even energy gap changes, improve the light transfer characteristic of end battery thus, the output characteristic of solar cell can be improved thus.
[manufacture method of upside-down mounting multijunction solar cell]
In the manufacture method of the upside-down mounting multijunction solar cell of present embodiment, make with the following method: upside-down mounting growth multijunction solar cell semiconductor layer 002 on growth substrate; The method that upside-down mounting multijunction solar cell semiconductor function layer 002 adopts photoetching combine with evaporation or PECVD etc. combines with photoetching prepares the thin-film material with multiple hole on described solar cell semiconductor layer, forms described stress barrier layer 301; On described stress barrier layer and among hole, evaporation metal ohmic contact material forms Ohm contact electrode 302; At the described Ohm contact electrode side engagement supporting substrate 003 of solar cell semiconductor functional layer, and remove described growth substrate; Ohmic electrode 004 is formed with Ohm contact electrode opposition side in solar cell semiconductor functional layer; Antireflective coating is covered in the Ohmic electrode side of upside-down mounting multijunction solar cell semiconductor function layer.
The formation process > of < upside-down mounting multijunction solar cell semiconductor layer
First prepare semiconductor growing substrate 001, what such as select N-shaped to adulterate is the GaAs substrate of 9 ° to (111) crystal face drift angle, and thickness is at about 350um, and doping content is 1 × 10 18cm -3~ 4 × 10 18cm -3between.
In MOCVD system, semiconductor substrate 001 forms multijunction solar cell epitaxial loayer.
Grow InGaP etching cut-off layer 200 and GaAs ohmic contact layer 201 on this substrate successively, such as InGaP etching cut-off layer 200 doping is about 1 × 10 18cm -3, thickness 200nm.GaAs ohmic contact layer 201 doping is about 1 × 10 18cm -3, thickness 300nm.
Then on GaAs ohmic contact layer 201, upside-down mounting growth has the sub-battery 202 of (Al) GaInP first of the first band gap (about 1.9eV), specifically comprises n +alInP Window layer 202a, is doped to 1 × 10 18cm -3, thickness 25nm; n +(Al) GaInP emitter region 202b is doped to 2 × 10 18cm -3, thickness 100nm; p +(Al) GaInP base 202c is doped to 5 × 10 17cm -3, thickness 1000nm; And p +alInGaP back surface field layer 202d is doped to 1 × 10 18cm -3, thickness 100nm.Then above back surface field layer (BSF) 202d, heavily doped p is grown ++/ n ++alGaAs tunnel junctions 202e, is doped to 2 × 10 19cm -3, thickness 50nm.
Then, above tunnel junctions 202e, upside-down mounting growth has the Ga(In of the second band gap (about 1.5eV)) the sub-battery 203 of As second, specifically comprise n +alInP Window layer 203a is doped to 1 × 10 18cm -3, thickness 25nm; n +ga(In) As emitter region 203b adulterates 21 × 10 18cm -3, thickness 150nm; p +ga(In) As base 203c is doped to 5 × 10 17cm -3, thickness 1250nm; 1 × 10 is doped to p-type GaInP back surface field layer 203d 18cm -3, thickness 100nm.Then above the second sub-battery 203, heavily doped p is grown ++/ n ++gaAs tunnel junctions 203e is doped to 2 × 10 19cm -3, thickness 50nm.
Above tunnel junctions 203e, grow graded buffer layer 204, comprise stress release layer In xal 0.4ga 0.6-xas(is divided into 10 layers, and every layer of In component increases progressively 0.03, and every layer of 250nm, is doped to 1 × 10 18cm -3; Stress equilibrium layer In 0.33al 0.4ga 0.27as, thickness is preferably 1000nm, is doped to 1 × 10 18cm -3; With target lattice layer In 0.3al 0.4ga 0.3as, its thickness is 250nm, is doped to 1 × 10 18cm -3.
Above graded buffer layer 204, upside-down mounting growth has the 3rd sub-battery 205 of the 3rd band gap (about 1.0eV), specifically comprises n +gaInP Window layer 205a is doped to 1 × 10 18cm -3, thickness 25nm; n +in 0.3ga 0.7as emitter region 205b is doped to 2 × 10 18cm -3, thickness 250nm; p +in 0.3ga 0.7as base 205c is doped to 5 × 10 17cm -3, thickness 3000nm and p +in 0.3al 0.4ga 0.3as back surface field layer 205d is doped to 1 × 10 18cm -3, thickness 50nm.
Highly doped p is grown above the 3rd sub-battery ++inGaAs cap, is doped to 2 × 10 19cm -3, thickness 500nm is as ohmic contact layer.
Fig. 2 is the cross-sectional view comprising the upside-down mounting multijunction solar cell semiconductor layer of the first sub-battery, the second sub-battery, graded buffer layer and the 3rd sub-battery formed on growth substrate.
The formation process > of < stress barrier layer
Fig. 3 is the cross-sectional view of the upside-down mounting multijunction solar cell of Fig. 2 after next processing step.
In one embodiment, photoetching process is adopted to make figure on solar cell semiconductor layer surface, adopt electron-beam vapor deposition method at solar cell semiconductor layer surface evaporation Cr film, thickness 100nm ~ 300nm, then make to form the Cr film with multiple hole on solar cell semiconductor layer surface through peeling off.Diameter 6um ~ the 20um of hole, is preferably not more than 10um, forms described stress barrier layer 301, and as shown in Figure 4, vertical view as shown in Figure 5.The ratio that the hole that Cr film film etches accounts for whole rete area asks x to obtain by formula 14.1x+4.9 (1-x)=6.0.Electron-beam vapor deposition method is adopted to fill ohmic electrode layer in the hole of Cr film.Thus, ohmic electrode layer is configured to multiple undersized independently unit and contacts with solar cell semiconductor layer.The thermal coefficient of expansion being arranged so that this tunic like this and the thermal coefficient of expansion comparability of solar cell semiconductor layer are intended, and therefore in follow-up heat treatment process, the thermal expansion stress of ohmic contact metal layer to solar cell semiconductor layer reduces greatly.
In another embodiment, adopt PECVD method at solar cell semiconductor layer surface deposition SiO 2as stress barrier layer, thickness 100nm ~ 300nm.Adopt photoetching process, at SiO 2rete produces figure, adopts the HF solution of dilution, at SiO 2rete etches multiple hole, the diameter 6um ~ 20um of hole, is preferably not more than 10um, and the ratio that hole accounts for whole rete area asks x to obtain by formula 14.1x+0.5 (1-x)=6.0.Adopt electron-beam vapor deposition method at SiO 2ohm contact electrode is filled in the hole of film.Adopt SiO 2film also has another to act on, it and solar cell semiconductor layer and jointly form an ODR full reflected system as the metal level of Ohm contact electrode, light through end battery can be reflected back, increase end battery to the absorption of light, be conducive to the light transfer characteristic improving end battery.
The formation process > of < Ohm contact electrode
Fig. 6 is the cross-sectional view of the upside-down mounting multijunction solar cell of Fig. 4 after next processing step, at heavy doping cap 206 disposed thereon Ohm contact electrode material 302 in described processing step.Here use electron-beam vapor deposition method, described Ohm contact electrode metal can be Ti/Au, Ti/Pt/Au, Ti/Au/Ag/Au, AuBe, AuZn etc., preferably AuZn.
The bonding process > of < supporting substrate
Fig. 7 is the cross-sectional view of the upside-down mounting multijunction solar cell of Fig. 6 after next processing step, uses vapour deposition method to deposit bond wire 303 in described processing step on ohmic electrode layer 302.Described bond wire 303 can be Au, AuIn, AuSn etc., preferred Au in the present embodiment.Certainly, bonding metal layer also comprises known barrier layer here, combinations as wherein two or more in Ni, Ti, Pt etc.
Fig. 8 is the cross-sectional view of the upside-down mounting multijunction solar cell of Fig. 7 after next processing step, in described processing step, make part shown in Fig. 6 engage with substrate 003, substrate 003 can be any one in Si substrate, GaP substrate, SiC substrate or metal substrate, preferred Si substrate in the present embodiment; Joint method can use known any technology such as eutectic bonding, diffusion interlinked, normal temperature bonding.Specifically, the upside-down mounting multijunction solar cell epitaxial wafer forming bonding metal layer and the Si substrate forming bond wire face to face overlapping in the present embodiment, then put into the cavity that reduces pressure, be evacuated to 10 -1more than Pa, applies the load of 12000kg, keeps certain hour under being heated to 360 DEG C of states, makes both be joined together.
< growth substrate removing step >
Fig. 9 is the cross-sectional view of the upside-down mounting multijunction solar cell of Fig. 8 after next processing step, uses ammoniacal liquor, hydrogen peroxide mixed solution optionally to etch away growth substrate 001 in described processing step; Then, the hydrochloric acid solution of dilution is used optionally to etch away etching cut-off layer 200.
The formation process > of < Ohmic electrode
Figure 10 is the cross-sectional view of the upside-down mounting multijunction solar cell of Fig. 9 after next processing step, forms Ohmic electrode 004 at upside-down mounting multijunction solar cell semiconductor function layer in described processing step with Ohm contact electrode opposition side.Specifically, the formation photoresistance of the regioselectivity of photoetching technique beyond Ohmic electrode is used with Ohm contact electrode opposition side such as at upside-down mounting multijunction solar cell semiconductor function layer, then use vapour deposition method evaporation Ohmic electrode, selected ohmic electrode material can be AuGe, AuGeNi or PaGeAu etc.Then use vapour deposition method evaporation Ag, Ohmic electrode is thickeied.Then peel off, form the Ohmic electrode 004 shown in Figure 10 thus.
Next, use the mixed liquor of citric acid, hydrogen peroxide and water to take Ohmic electrode as metal mask to what remove ohmic contact layer 201 and overlook part beyond overlapping part with Ohmic electrode 004.
The formation process > of < antireflective coating
Cover antireflective coating in the Ohmic electrode side of upside-down mounting multijunction solar cell semiconductor layer, selected antireflective coating can be TiO 2, Al 2o 3, SiO 2, Si 3n 4, MgF 2deng individual layer, bilayer, three layers or more tunics that one or more in material are formed, select TiO here 2/ Al 2o 3double-layer reflection-decreasing membrane structure.
Next step, form the metal level of good adhesion, chemical proofing excellence with it, such as according to Si substrate, then can select Ti/Ag/Au or TiAu in supporting substrate 003 multijunction solar cell semiconductor layer opposition side.
Utilize above operation, supporting substrate 003 is formed multiple upside-down mounting many knots concentrating solar battery.
< singualtion operation >
Then, the multiple upside-down mounting many knots concentrating solar batteries be formed on supporting substrate 003 are carried out singualtion.Specifically, can adopt wet etching, dry etching or both combine the semiconductor layer of removing predetermined cuts road part, use cutting machine to cut off at predetermined intervals.
Figure 11 shows that the schematic top plan view of the another example of stress barrier layer of upside-down mounting multijunction solar cell of the present invention.Specifically, in the formation process of the hole of stress barrier layer, use photoetching technique can form the figure of arbitrary shape, as long as meet the requirement of area proportion, and be uniformly distributed as far as possible.

Claims (12)

1. solar cell, comprise successively from bottom to top: substrate, bonding metal layer, ohmic electrode layer, stress barrier layer, solar cell semiconductor layer and Ohmic electrode, it is characterized in that: described stress barrier layer is arranged between described solar cell semiconductor layer and ohmic electrode layer, prevent because ohmic electrode layer and thermal stress that between bonding metal layer and semiconductor layer, the difference of thermal coefficient of expansion produces make the poor crystal quality of semiconductor layer.
2. solar cell according to claim 1, is characterized in that: the thermal coefficient of expansion of described stress barrier layer and described solar cell semiconductor layer similar thermal expansion coefficient or smaller.
3. solar cell according to claim 2, is characterized in that: described stress barrier layer is made up of the metallic film material of thermal coefficient of expansion and solar cell semiconductor layer similar thermal expansion coefficient.
4. solar cell according to claim 2, is characterized in that: described stress barrier layer is made up of the dielectric thin-film material that thermal coefficient of expansion is more smaller than solar cell semiconductor material thermal expansion coefficient.
5. solar cell according to claim 2, is characterized in that: described stress barrier layer is configured to the film with multiple perforated.
6. solar cell according to claim 5, is characterized in that: the ratio of whole stress barrier layer area shared by the perforated of described stress barrier layer is complied with the thermal coefficient of expansion ratio of selected stress barrier material and solar cell semiconductor material and determines.
7. solar cell according to claim 5, it is characterized in that: the contact interface of described ohmic electrode layer and described solar cell semiconductor layer is discontinuous, described ohmic electrode layer material component is filled among the perforated of described stress barrier layer.
8. solar cell according to claim 6, is characterized in that: the thermal coefficient of expansion setting described solar cell semiconductor layer is T 1, the thermal coefficient of expansion of described stress barrier layer is T 2, the thermal coefficient of expansion of described ohmic electrode layer is T 3, the hole area occupied ratio of described stress barrier layer is X, then meet: T 3* X+T 2(1-X)=T 1.
9. solar cell according to claim 2, is characterized in that: described solar cell semiconductor layer is upside-down mounting multijunction cell structure.
10. the preparation method of solar cell, comprise step below: form bonding metal layer, ohmic electrode layer on a substrate, this ohmic electrode layer is formed solar cell semiconductor layer, the surface of this solar cell semiconductor layer makes Ohmic electrode, it is characterized in that: be also included between described solar cell semiconductor layer and ohmic electrode layer and stress barrier layer is set, prevent because ohmic electrode layer and thermal stress that between bonding metal layer and semiconductor layer, the difference of thermal coefficient of expansion produces make the poor crystal quality of semiconductor layer.
The preparation method of 11. solar cells according to claim 10, it is characterized in that: adopt the method that photoetching combines with evaporation or PECVD combines with photoetching to prepare the thin-film material with multiple hole on described solar cell semiconductor layer, form described stress barrier layer.
The preparation method of 12. solar cells according to claim 10, is characterized in that: described stress barrier layer selects thermal coefficient of expansion and solar cell semiconductor layer similar thermal expansion coefficient or smaller material.
CN201510768850.0A 2015-11-12 2015-11-12 Solar cell and manufacturing method thereof Pending CN105261659A (en)

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CN112259615A (en) * 2020-09-24 2021-01-22 华南理工大学 GaAs solar cell laminated antireflection film for space and preparation method and application thereof
CN112447859A (en) * 2019-08-29 2021-03-05 阿聚尔斯佩西太阳能有限责任公司 Multi-junction solar cell in the form of a stack with metallization layers comprising a multilayer system
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CN112447859A (en) * 2019-08-29 2021-03-05 阿聚尔斯佩西太阳能有限责任公司 Multi-junction solar cell in the form of a stack with metallization layers comprising a multilayer system
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