CN105261644A

CN105261644A - Semiconductor device and manufacturing method thereof

Info

Publication number: CN105261644A
Application number: CN201410337867.6A
Authority: CN
Inventors: 宋建宪
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp; Vanguard International Semiconductor America
Priority date: 2014-07-16
Filing date: 2014-07-16
Publication date: 2016-01-20

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a semiconductor layer, a groove, a source region and a drain region, wherein the groove is formed in the top surface of the semiconductor layer and comprises a bottom surface and a side wall; and one of the source region and the drain region can be arranged on the bottom surface of the groove and the other one can be arranged on the top surface of the semiconductor layer, and vice versa. Or, both the source region and the drain region can be arranged on the bottom surface of the groove. The semiconductor device can comprise a first insulator; the first insulator is arranged in the groove and between the source region and the drain region. The semiconductor device can also comprise a second insulator; and the second insulator is arranged between the first insulator and the source region. The semiconductor can also comprise a conducting element; and the conducting element is arranged on the first insulator or is located between the first insulator and the second insulator. According to the semiconductor device, the efficiency of the device can be enhanced under the premise of not increasing the occupied space of the device.

Description

Semiconductor device and manufacture method thereof

Technical field

The invention relates to a kind of semiconductor device, and particularly about a kind of, there is the less semiconductor device of floor space and manufacture method thereof.

Background technology

Puncture voltage is the important parameter of many semiconductor devices, and it is usually in order to determine the permissible operating voltage range of semiconductor device.At present, there are many methods can in order to increase the puncture voltage of semiconductor device, such as: the doping content reducing the region between two electrical terminals (such as source electrode and drain electrode, anode and negative electrode or grid and drain electrode etc.) or the distance increased between two electrical terminals.

When designing semiconductor device, usually can fix some parameter to reach some performance goals, and some other parameter of adjustable are with the overall efficiency of enhanced device.Such as, the doping content of stationary conduit district (between source electrode and drain electrode), has specific critical voltage to make mos field effect transistor (MOSFET).Puncture voltage then increases by the distance (such as increase between drain region and channel region and extend drain region) increased between two terminals, and does not affect critical voltage in fact.

But if the distance between two terminals increases, also can increase the floor space (devicefootprint) of device, it may make the device quantity that wafer can manufacture in per unit area reduce, and therefore increases manufacturing cost.

Summary of the invention

Therefore, the technical problem to be solved in the present invention is to provide a kind of semiconductor device, and it can reduce distance between two terminals with enhanced device usefulness (such as, having higher puncture voltage), and can not increase in fact the floor space of device.

According to some embodiments of the present invention, semiconductor device can comprise semi-conductor layer and one first groove, and this first channel shaped is formed in one first end face of this semiconductor layer, and this first groove has one first bottom surface and a first side wall.Semiconductor device also can comprise this first bottom surface that this first groove is located in one first drain region, and this first end face of this semiconductor layer is located in one first source area.This first source area therewith the first drain region has interval.Moreover this semiconductor device can comprise one first insulator and be located in this groove and between this drain region and this source area, and this bottom surface of groove and this first side wall contact therewith.In addition, this semiconductor device can comprise one second insulator and be located at this first drain region therewith between the first source area, and is positioned on this first end face of this semiconductor layer.

In various embodiments, this semiconductor device can comprise one or more following features: the first side wall of this first groove is arc; 90 degree are greater than in the first side wall of this first groove and the angle of the first bottom surface; And one first conducting element be located on this second insulator, or one first conducting element is located on this first insulator and this second insulator.

According to some embodiments of the present invention, semiconductor device also can comprise one second channel shaped and be formed in one second end face of this semiconductor layer, and this second groove has one second bottom surface and one second sidewall; The second bottom surface of this second groove is located in one second drain region; The second end face of this second groove of this semiconductor layer is located in one second source area.One the 3rd insulator is located in this second groove and between this second drain region and the second source area, and is positioned on the second bottom surface of this second groove.One the 4th insulator is located in this second groove and between this second source area and this 3rd insulator, and is positioned on the second bottom surface of this second groove.

In various embodiments, this semiconductor device also can comprise one or more following features: the second sidewall of this second groove is arc; Second sidewall of this second groove and the angle of the second bottom surface are greater than 90 degree; One second conducting element is located on this 4th insulator, or one second conducting element is located on this 3rd insulator and this 4th insulator; This first insulator and this 3rd insulator are formed by same material; And this first insulator and this 3rd insulator have different-thickness.

Or in certain embodiments, semiconductor device also can comprise one second channel shaped and be formed in one second end face of this semiconductor layer, and this second groove has one second bottom surface and one second sidewall.This semiconductor device also can comprise the second bottom surface that this second groove is located in one second drain region, and the second bottom surface of this second groove is located in one second source area.In addition, this semiconductor device also can comprise one the 3rd insulator and be located in this second groove, between this second drain region and this second source area, and contacts with in the second bottom surface of this second groove and the second sidewall.In addition, this semiconductor device can comprise one the 4th insulator and be located in this second groove, between this second source area and this 3rd insulator, and is positioned on this second bottom surface of this second groove.

In various embodiments, this semiconductor device can comprise one or more following features: the second sidewall of this second groove is arc; Second sidewall of this second groove and the angle of the second bottom surface are greater than 90 degree; One second conducting element is located on this 4th insulator, or one second conducting element is located on this 3rd insulator and this 4th insulator; This first insulator and this 3rd insulator are formed by same material; And this first insulator and this 3rd insulator have different-thickness.

According to some embodiments of the present invention, semiconductor device can comprise semi-conductor layer and one first channel shaped is formed in an end face of this semiconductor layer, and this first groove has one first bottom surface and a first side wall.Semiconductor device also can comprise one first source area and be located at this first end face that this semiconductor layer is located in this first bottom surface of this first groove and one first drain region, and this first drain region therewith the first source area has interval.In addition, semiconductor device can comprise one first insulator and be located in this first groove and between this first source area and this first drain region, and this first bottom surface of the first groove and this first side wall contact therewith.In addition, semiconductor device can comprise one second insulator and be located at this first source area therewith between the first insulator, and is positioned on the first bottom surface of this first groove.

In various embodiments, this semiconductor device also can comprise one or more following features: the first side wall of this first groove is arc; The first side wall of this first groove and the angle of the first bottom surface are greater than 90 degree; And one first conducting element be located on this second insulator, or one first conducting element is located on this first insulator and this second insulator.

In certain embodiments, semiconductor device also can comprise one second channel shaped and be formed in one second end face of this semiconductor layer, and this second groove has one second bottom surface and one second sidewall.This semiconductor device also can comprise one second drain region and be located at the second bottom surface that this second groove is located in this second bottom surface of this second groove and one second source area.In addition, this semiconductor device comprises one the 3rd insulator and is located in this second groove, between this second drain region and this second source area, and is positioned on the second bottom surface of this second groove.In addition, this semiconductor device comprises one the 4th insulator and is located in this second groove, between this second source area and this 3rd insulator, and is positioned on the second bottom surface of this second groove.

Or in certain embodiments, this semiconductor device also can comprise one second channel shaped and be formed in one second end face of this semiconductor layer, and this second groove has one second bottom surface and one second sidewall.This semiconductor device also can comprise this second bottom surface that this second groove is located in one second drain region, and this second bottom surface of this second groove is located in one second source area.In addition, this semiconductor device can comprise one the 3rd insulator and be located in this second groove, between this second drain region and this second source area, and contacts with in the second bottom surface of this second groove and the second sidewall.In addition, this semiconductor device can comprise one the 4th insulator and be located between this second source area and this 3rd insulator, and is positioned on this second bottom surface of this second groove.

In various embodiments, this semiconductor device can comprise one or more following features: the second sidewall of this second groove is arc; Second sidewall of this second groove and the angle of the second bottom surface are greater than 90 degree; One second conducting element is located on this 4th insulator, or the second conducting element is located on this 3rd insulator and this 4th insulator; This first insulator and this 3rd insulator are formed by same material; And this first insulator and this 3rd insulator have different-thickness.

According to some embodiments of the present invention, semiconductor device can comprise semi-conductor layer and a channel shaped is formed in an end face of this semiconductor layer, and this groove has a bottom surface and a sidewall.This semiconductor device also can comprise the bottom surface that this groove is located in a drain region, and one source pole district is located at the bottom surface of this groove.In addition, this semiconductor device can comprise one first insulator and be located in this groove, between this drain region and this source area, and is positioned on the bottom surface of this groove.In addition, this semiconductor device can comprise one second insulator and establish in this groove, at this first insulator therewith between source area, and is positioned on this bottom surface of this groove.

In various embodiments, this semiconductor device can comprise one or more following features: the sidewall of this groove is arc; The sidewall of this first groove and the angle of bottom surface are greater than 90 degree; And one conducting element be located on this second insulator, or a conducting element is located on this first insulator and this second insulator.

According to some embodiments of the present invention, semiconductor device can comprise semi-conductor layer; And one first and 1 second doped region be located on this semiconductor layer.This semiconductor device also can comprise an insulator and be located between this first doped region and this second doped region, to define this semiconductor device when initiate mode, current conducting path in this semiconductor layer is between this first doped region and this second doped region, and this current conducting path arranges along the girth of this insulator in fact and has a vertical component and a horizontal component.

In certain embodiments, the manufacture method of semiconductor device can comprise formation one first insulator on one first end face of semi-conductor layer, one first trench intersection that this first insulator extends so far in below the first end face and therewith the first end face touches, this first groove has one first bottom surface and a first side wall, and this first bottom surface and this first side wall therewith the first insulator contact.The method also comprises the hard mask of formation one first on this first insulator.In addition, the method can comprise formation one first opening and penetrate this first hard mask and this first insulator, and this first opening extends this first bottom surface of so far the first groove.Moreover the method comprises this first insulator removing this first hard mask and a part, and to make a remainder of this first insulator, the first bottom surface and this first side wall contact therewith.In addition, the method comprises formation one second insulator on the first end face of this semiconductor layer, and the first insulator is adjacent therewith for this second insulator.Moreover the method comprises formation one first drain region in the first bottom surface of this first groove; And formed one first source area in the first end face of this semiconductor layer, this first source area therewith the second insulation layer is adjacent, and by this first and this second insulator be separated by the first drain region therewith.

In various embodiments, the method can comprise one or more following features: form one first conducting element on this second insulator; Form one first conducting element on this first insulator and this second insulator; This first insulator is formed with a silicon location oxidation of silicon process; This first insulator is formed with a shallow ditch groove separation process; And the step of this first insulator removing this first hard mask and a part also comprise with relative to a second area faster speed remove a first area, wherein this first area one is adjacent to this hard mask, and this second area therewith hard mask there is interval.

In certain embodiments, this method for making semiconductor also comprises formation 1 the 3rd insulator on one second end face of this semiconductor layer, one second trench intersection that this 3rd insulator extends so far in below the second end face and therewith the second end face touches, and this second groove has one second bottom surface and one second sidewall.The method also can comprise the hard mask of formation one second on this 3rd insulator; And form one second opening and one the 3rd opening and penetrate this second hard mask and this 3rd insulator, this second opening and the extension of this 3rd opening be the second bottom surface of the second groove and the second sidewall so far.Moreover the method can comprise this 3rd insulator removing this second hard mask and a part, contact to make this second bottom surface of a remainder of this 3rd insulator the second groove therewith.Moreover the method can comprise formation 1 the 4th insulator on the second bottom surface of this second groove, and this 4th insulator therewith the 3rd insulator is adjacent.In addition, the method comprises formation one second drain region in the second bottom surface of this second groove.Moreover the method comprises formation one second source area in the second bottom surface of this second groove, and this second source area therewith the 4th insulator is adjacent, and by this 3rd and this 4th insulator be flatly separated by the second drain region therewith.

In various embodiments, the method can comprise one or more following features: form one second conducting element on this 4th insulator; Formed one second conducting element in this 3rd and this 4th insulator on; This 3rd insulator of this first insulator is formed in a single processing step; Form this 3rd insulator with a silicon location oxidation of silicon process, or form this 3rd insulator with a shallow ditch groove separation process; And the step of this first insulator removing this first hard mask and a part also comprises: with relative to a second area faster speed remove a first area, wherein this first area one is adjacent to this hard mask, and this second area therewith hard mask there is interval.

Or, in certain embodiments, the method also can comprise formation 1 the 3rd insulator on one second end face of this semiconductor layer, one second trench intersection that this 3rd insulator extends so far in below the second end face and therewith the second end face touches, and this second groove has one second bottom surface and one second sidewall.The method also comprises the hard mask of formation one second on this 3rd insulator; And form one second opening and one the 3rd opening and penetrate this second hard mask and this 3rd insulator, this second opening and the extension of this 3rd opening be this second bottom surface of the second groove and this second sidewall so far.Moreover the method can comprise this 3rd insulator removing this second hard mask and a part, contact to make the second bottom surface of a remainder of this 3rd insulator the second groove therewith.Moreover the method can comprise formation 1 the 4th insulator on the second bottom surface of this second groove, and this 4th insulator therewith the 3rd insulator is adjacent.In addition, the method comprises formation one second drain region in the second bottom surface of this second groove.Moreover the method comprises formation one second source area in the second bottom surface of this second groove, and this second source area is adjacent with the 4th insulator, and by this 3rd and this 4th insulator be separated by the second drain region therewith.

In various embodiments, the method can comprise one or more following features: formed one second conducting element on this 4th insulator, or formed one second conducting element in this 3rd and this 4th insulator on; This 3rd insulator of this first insulator is formed in a single processing step; This 3rd insulator is formed with a silicon location oxidation of silicon process; This 3rd insulator is formed with a shallow ditch groove separation process.

According to some embodiments of the present invention, the manufacture method of semiconductor device can comprise formation one first insulator on one first end face of semi-conductor layer, this first insulator extends so far one first trench contact in below the first end face and therewith the first end face, this first groove has one first bottom surface and a first side wall, and this first bottom surface and this first side wall therewith the first insulator contact.The method also can comprise the hard mask of formation one first on this first insulator; And formation one first opening penetrates this first hard mask and this first insulator, this first opening extends this first bottom surface of so far the first groove.The method also comprises this first insulator removing this first hard mask and a part, and to make a remainder of this first insulator, the first bottom surface and this first side wall contact therewith.Moreover the method can comprise formation one second insulator on this first bottom surface of the first groove, and this second insulator therewith the first insulator is adjacent.In addition, the method can comprise formation one first drain region in this first end face of this semiconductor layer.In addition, the method can comprise formation one first source area in this first bottom surface of this first groove, and this first source area therewith the second insulator is adjacent.

In various embodiments, the method can comprise one or more following features: form one first conducting element on this second insulator; Formed one first conducting element in this first and this second insulator on; Form this first insulator with a silicon location oxidation of silicon process, or form this first insulator with a shallow ditch groove separation process; And the step of this first insulator removing this first hard mask and a part also comprises: with relative to a second area faster speed remove a first area, wherein this first area one is adjacent to this hard mask, and this second area therewith hard mask there is interval.

In certain embodiments, the method also comprises formation 1 the 3rd insulator on one second end face of this semiconductor layer, this the 3rd insulator extends so far one second trench contact in below the second end face and therewith the second end face, and this second groove has one second bottom surface and one second sidewall.The method also can comprise the hard mask of formation one second on this 3rd insulator; And form one second opening and one the 3rd opening and penetrate this second hard mask and this 3rd insulator, this second opening and the extension of this 3rd opening be the second bottom surface of the second groove and the second sidewall so far.In addition, the method comprises this 3rd insulator removing this second hard mask and a part, with this second bottom surface contact of the remainder making this 3rd insulator the second groove therewith.Moreover the method can comprise formation 1 the 4th insulator on this second bottom surface of this second groove, the 3rd insulator is adjacent therewith for this 4th insulator.In addition, the method can comprise formation one second drain region in the second bottom surface of this second groove.In addition, the method can comprise formation one second source area in this second bottom surface of this second groove, and this second source area therewith the 4th insulator is adjacent, and by this 3rd and this 4th insulator be separated by the second drain region therewith.

In certain embodiments, the method can comprise one or more following features: formed one second conducting element on this 4th insulator, or formed one second conducting element in this 3rd and this 4th insulator on; Form this 3rd insulator with a silicon location oxidation of silicon process, or form this 3rd insulator with a shallow ditch groove separation process.

According to some embodiments of the present invention, the manufacture method of semiconductor device comprises: form one first insulator on an end face of semi-conductor layer, this first insulator to extend below so far end face and a trench contact therewith in end face, and this groove has a bottom surface and a sidewall.The method also comprises the hard mask of formation one on this first insulator; And form one first opening and one second opening and penetrate this hard mask and this first insulator, this first opening and this second opening extend this bottom surface and this sidewall of so far groove.Moreover the method can comprise this first insulator removing this hard mask and a part, contact to make this bottom surface of a remainder of this first insulator groove therewith.Moreover the method can comprise formation one second insulator on this bottom surface of this groove, and the first insulator is adjacent therewith for this second insulator.In addition, the method can comprise formation one drain region in the bottom surface of this groove.Moreover the method can comprise formation one source pole district in the bottom surface of this groove, and this source area therewith the second insulator is adjacent, and is separated by drain region therewith by this first insulator and this second insulator.

In various embodiments, the method can comprise one or more following features: form a conducting element on this second insulator, or forms a conducting element on this first insulator and this second insulator; Form this first insulator with a silicon location oxidation of silicon process, or form this first insulator with a shallow ditch groove separation process; And the step of this first insulator removing this first hard mask and a part also comprises: with relative to a second area faster speed remove a first area, wherein this first area one is adjacent to this hard mask, and this second area therewith hard mask there is interval.

According to some embodiments of the present invention, the manufacture method of semiconductor device comprises: form an insulator on an end face of semi-conductor layer, this insulator to extend below so far end face and a trench contact therewith in end face, this groove has a bottom surface and a sidewall, the insulator contact therewith of this bottom surface and this sidewall.The method also comprises the hard mask of formation one on this insulator; And formation one opening penetrates this hard mask and this insulator, this opening extends this bottom surface and this sidewall of so far groove.In addition, the method comprises this insulator removing this hard mask and a part, with the remainder making this insulator this bottom surface of groove and this sidewall contact therewith, wherein a thickness of a remainder of this first insulator is by the Position Control of the width or this opening that adjust this opening.

The invention provides a kind of semiconductor device and manufacture method thereof, can not increase under the prerequisite that device takes up room, reduce distance between two terminals with enhanced device usefulness (such as, there is higher puncture voltage).

For above and other object of the present invention, feature and advantage can be become apparent, cited below particularly go out preferred embodiment, and coordinate appended accompanying drawing, be described in detail below:

Accompanying drawing explanation

Figure 1A and 1B is shown as the embodiment of the semiconductor device corresponding to some embodiments of the present invention.

Fig. 2 A and 2B is shown as the embodiment of the semiconductor device corresponding to some embodiments of the present invention.

Fig. 3 A and 3B is shown as the embodiment of the semiconductor device corresponding to some embodiments of the present invention.

Fig. 4 A to 4H shows the embodiment of the manufacture method of the semiconductor device of Figure 1A.

Fig. 5 A to 5H shows the embodiment of the manufacture method of the semiconductor device of Figure 1B.

Fig. 6 A to 6F shows the embodiment of the manufacture method of the semiconductor device of Fig. 2 A.

Fig. 7 A to 7F shows the embodiment of the manufacture method of the semiconductor device of Fig. 2 B.

Fig. 8 A to 8D shows the embodiment of the manufacture method of the semiconductor device of Fig. 3 A.

Fig. 9 A to 9D shows the embodiment of the manufacture method of the semiconductor device of Fig. 3 B.

Figure 10 A to 10C shows the embodiment of the manufacture method of the semiconductor device corresponding to some embodiments of the present invention.

Symbol description:

102 semiconductor layers;

The end face of 104 semiconductor layers;

106 grooves;

The bottom surface of 108 grooves;

The sidewall of 110 grooves;

120 drain regions;

122 source areas;

130 first insulators;

132 second insulators;

140 conducting elements;

150 current conducting path;

202 semiconductor layers;

The end face of 204 semiconductor layers;

206 grooves;

The bottom surface of 208 grooves;

The sidewall of 210 grooves;

220 drain regions;

222 source areas;

230 first insulators;

232 second insulators;

240 conducting elements;

302 semiconductor layers;

The end face of 304 semiconductor layers;

306 grooves;

The bottom surface of 308 grooves;

The sidewall of 310 grooves;

320 drain regions;

322 source areas;

330 first insulators;

332 second insulators;

340 conducting elements;

350 current conducting path;

402 semiconductor layers;

The end face of 404 semiconductor layers;

406 grooves;

The bottom surface of 408 grooves;

The sidewall of 410 grooves;

420 drain regions;

422 source areas;

430 first insulators;

432 second insulators;

440 conducting elements;

460 hard masks;

470 openings;

502 semiconductor layers;

The end face of 504 semiconductor layers;

506 grooves;

The bottom surface of 508 grooves;

The sidewall of 510 grooves;

520 drain regions;

522 source areas;

530 first insulators;

532 second insulators;

540 conducting elements;

560 hard masks;

570 openings;

602 semiconductor layers;

The end face of 604 semiconductor layers;

606 grooves;

The bottom surface of 608 grooves;

The sidewall of 610 grooves;

620 drain regions;

622 source areas;

630 first insulators;

632 second insulators;

640 conducting elements;

660 hard masks;

670a first opening;

670b second opening;

702 semiconductor layers;

The end face of 704 semiconductor layers;

706 grooves;

The bottom surface of 708 grooves;

The sidewall of 710 grooves;

720 drain regions;

722 source areas;

730 first insulators;

732 second insulators;

740 conducting elements;

760 hard masks;

770a first opening;

770b second opening;

802 semiconductor layers;

The end face of 804 semiconductor layers;

806 grooves;

The bottom surface of 808 grooves;

The sidewall of 810 grooves;

820 drain regions;

822 source areas;

830 first insulators;

832 second insulators;

840 conducting elements;

902 semiconductor layers;

The end face of 904 semiconductor layers;

906 grooves;

The bottom surface of 908 grooves;

The sidewall of 910 grooves;

920 drain regions;

922 source areas;

930 first insulators;

932 second insulators;

940 conducting elements;

1006 grooves;

The sidewall of 1010 grooves;

1030 first insulators;

1070 openings.

Embodiment

Below with accompanying drawing, embodiments of the invention will be described in detail.

Figure 1A is shown as an embodiment of semiconductor device 10A.Device 10A comprises semi-conductor layer 102.Groove 106 is formed in the end face 104 of semiconductor layer 102.Groove 106 has bottom surface 108 and sidewall 110.The bottom surface 108 of groove 106 is located in drain region 120.The end face 104 of semiconductor layer 102 is located in source area 122, and and drain region 120 there is interval.First insulator 130 is arranged in groove 106 and between drain region 120 and source area 122.Bottom surface 108 and the sidewall 110 of the first insulator 130 and groove 106 contact.Second insulator 132 is arranged between drain region 120 and source area 122, and is positioned on the end face 104 of semiconductor layer 102.In certain embodiments, the sidewall 110 of groove 106 is arcuation.In certain embodiments, device 10A comprises conducting element 140 and is located on the second insulator 132.Conducting element 140 can such as gate electrode, to control or to adjust the electrical conductivity of the semiconductor layer 102 be positioned under the second insulator 132.In certain embodiments, conducting element 140 to be arranged on the second insulator 132 and to extend on the first insulator 130.The part on insulator 130 of being arranged at of conducting element 140 can such as field effect electroplax (fieldplate), to reduce internal field and to increase the puncture voltage of device 10A.

In certain embodiments, semiconductor device 10B as shown in Figure 1B, it is similar to semiconductor device 10A, and the angle between the sidewall 110 of groove 106 and bottom surface 108 is greater than 90 degree.

Bestowing suitable voltage to each terminal of device 10A or 10B during starting drive 10A or 10B, current conducting path 150 can be formed by the semiconductor layer 102 between source area 122 and drain region 120.Current conducting path 150 extends along the girth of the first insulator 130, comprises vertical component and horizontal component to make current conducting path 150.The vertical component of current conducting path 150 provides an extra size to adjust or improve the parameter of semiconductor device, such as puncture voltage or on-state resistance (on-stateresistance), and does not increase in fact the area occupied of device.Therefore, compared with traditional device with horizontal current guiding path in fact, embodiment described herein can have under less area occupied, reaches identical or better device usefulness.

Fig. 2 A is shown as an embodiment of semiconductor device 20A.Device 20A comprises semi-conductor layer 202.One groove 206 is formed in the end face 204 of semiconductor layer 202.Groove 206 has bottom surface 208 and sidewall 210.The bottom surface 208 of groove 206 is located in drain region 220.The bottom surface 208 of groove 206 is also located in source area 222.First insulator 230 is located in groove 206, between drain region 220 and source area 222, and is positioned on the bottom surface 208 of groove 206.Second insulator 232 is located in groove 206 and between source area 222 and the first insulator 230, and is positioned on the bottom surface 208 of groove 206.In certain embodiments, the sidewall 210 of groove 206 is arc.In certain embodiments, device 20A comprises conducting element 240 and is located on the second insulator 232.Conducting element 240 can such as gate electrode, to control or to adjust the electrical conductivity of the semiconductor layer 202 be positioned under the second insulator 232.In certain embodiments, conducting element 240 to be located on the second insulator 232 and to be extended on the first insulator 230.The conducting element 240 being located at the part on the first insulator 230 such as can imitate electroplax as field, to reduce the puncture voltage of internal field and increase device 20A.

In certain embodiments, semiconductor device 20B as shown in Figure 2 B, it is similar to semiconductor device 20A, and the angle between the sidewall 210 of groove 206 and bottom surface 208 is greater than 90 degree.

Fig. 3 A is shown as an embodiment of semiconductor device 30A.Device 30A comprises semiconductor layer 302.Groove 306 is formed in the end face 304 of semiconductor layer 302.Groove 306 has bottom surface 308 and sidewall 310.The bottom surface 308 of groove 306 is located in source area 322.The end face 304 of semiconductor layer 302 is located in drain region 320, and and source area 322 there is interval.First insulator 330 is arranged in groove 306, between source area 322 and drain region 320, and contacts with the bottom surface 308 of groove 310 and sidewall 310.Second insulator 322 is located between source area 322 and the first insulator 330, and is positioned on the bottom surface 308 of groove 306.In certain embodiments, the sidewall of groove 306 is arc.In certain embodiments, device 30A comprises a conducting element 340 and is located on the second insulator 332.Conducting element 340 can such as gate electrode, to control or to regulate the electrical conductivity of the semiconductor layer 302 be positioned under the second insulator 332.In certain embodiments, conducting element 340 is located on the second insulator 332, and extends on the first insulator 330.The conducting element 340 being located at the part on the first insulator 330 can be used as field effect electroplax, to reduce the puncture voltage of internal field and increase device 30A.

In certain embodiments, semiconductor device 30B as shown in Figure 3 B, it is similar to semiconductor device 30A, and the angle between the sidewall 310 of groove 306 and bottom surface 308 is greater than 90 degree.

Bestowing suitable voltage to each terminal of device 30A or 30B during starting drive 30A or 30B, current conducting path 350 can be formed by the semiconductor layer 302 between source area 322 and drain region 320.Current conducting path 350 is arranged along the girth of the first insulator 330 in fact, comprises vertical component and horizontal component to make current conducting path 350.The vertical component of current conducting path 350 provides an extra size to adjust or improve the parameter of semiconductor device, such as puncture voltage or on-state resistance (on-stateresistance), and does not increase in fact the area occupied of device.Therefore, compared with traditional device with horizontal current guiding path in fact, embodiment described herein can have under less area occupied, reaches identical or better device usefulness.

Following examples are by the manufacture method with Fig. 4 A to 4H tracing device 10A.See Fig. 4 A, form the first insulator 430 on the end face 404 of semiconductor layer 402, to make the first insulator 430 extend to below end face 404, and the first insulator 430 is contacted with the groove 406 in end face 404.Groove 406 comprises a bottom surface 408 and sidewall 410, and this bottom surface 408 and sidewall 410 contact with the first insulator 430.The rete that semiconductor layer 402 can be such as silicon layer, silicon-containing layer, silicon substrate or wafer or be made up of element or compound semiconductor materials.First insulator 430 and groove 406 can such as be formed by silicon selective oxidation (LOCOS) technique simultaneously.This LOCOS technique is the prior art in semiconductor manufacturing, is not discussed further in this invention.

See Fig. 4 B, hard mask 460 is formed on the first insulator 430, and hard mask 460 also can cover end face 404.In certain embodiments, resilient coating (not shown) can be formed between hard mask 460 and the first insulator 430, or be formed between hard mask 460 and end face 404, to reduce any stress caused by hard mask 460.Hard mask 460 can be such as silicon nitride, silicon oxynitride, silicon nitride comprising material, metal or other suitable materials.Hard mask 460 can be formed by low-pressure chemical vapor deposition process, ion enhanced chemical vapor deposition processes or other suitable chemical vapor deposition methods.Hard mask 460 also can be formed by physical gas-phase deposition, such as, sputter, evaporate or the formation of other Desirable physical gas-phase depositions.

See Fig. 4 C, form opening 470 and penetrate hard mask 460 and the first insulator 430.Opening 470 extends to the bottom surface 408 of groove 406.The formation of opening 470 can be completed by the combination such as carrying out photoetching and etching technics.By using photoetching process, the photoresist layer patterning that can will be deposited on hard mask 460, forms an opening, and the region of this opening corresponds in fact the hatch region of opening 470.Then, by using etching technics, the patterning opening by photoresist layer removes the hard mask 460 of a part and the first insulator 430 of a part.By controlling the parameter of etching technics, such as time, temperature or etch chemistries thing, can control or modify the degree of depth and the side wall profile of opening.

See Fig. 4 D, remove the first insulator 430 of hard mask 460 and a part, still contact with the bottom surface 408 of groove and sidewall 410 to make the remainder of the first insulator 430.Such as wet-etching technology, dry etch process can be used or effectively can be removed hard mask 460 by the hybrid technique of wet etching and dry etch process or other and not exclusively be removed the technique of the first insulator 430, removing the first insulator 430 of hard mask 460 and a part.In certain embodiments, the part that the first insulator 430 is removed comprise contiguous hard mask 460 first area and with the spaced second area of hard mask 460 tool.During the manufacturing process of the first insulator 460 removing hard mask 460 and part, the speed that removes of first area (contiguous hard mask 460) removes speed higher than second area (and hard mask 460 has interval).The speed that removes faster of first area caused by the torsion being imparted to first area (strain).This torsion may be caused by the internal stress of hard mask 460.

In certain embodiments, this torsion adjusts by the formation process adjusting hard mask 460.Such as, if hard mask 460 is silicon nitride layer, hard mask 460 can be formed by ion enhanced chemical vapor deposition processes.By using ion enhanced chemical vapor deposition processes, the internal stress of silicon nitride layer can by gas source (the such as NH used in the hard mask formation process of adjustment (such as depositing the technique of hard mask 460 on the first insulator 430) ₃, SiH ₄, H ₂) bias voltage, to control the torsion being imparted to the first insulator 430.In certain embodiments, hard mask 460 and the first insulator 430 remove speed by between the Formation period of hard mask layer 460 and the first insulator 430, control the density of hard mask layer 460 and the first insulator 430, stoichiometry or quality and adjust.By adjustment speed is removed to hard mask 460 and the first insulator 430, thickness or the shape of the remainder of the first insulator 430 can be controlled.

See Fig. 4 E, form the second insulator 432 on the end face 404 of semiconductor layer 402.Second insulator 432 is adjacent to the first insulator 430.Second insulator 432 can be formed by being such as oxidized by the end face 404 of semiconductor layer 402, or is formed by chemical vapor deposition method, atom layer deposition process, molecular beam epitaxial process, physical gas-phase deposition or other suitable deposition processes deposition.Second insulator 432 can via carrying out the combination of photoetching and etching technics and patterning.

See Fig. 4 F, form conducting element 440 on the second insulator 432.In certain embodiments, see Fig. 4 G, conducting element 440 is formed on the first insulator 430 and the second insulator 432.Conducting element 440 can by such as using chemical vapour deposition (CVD), ald, molecular beam epitaxy, physical vapour deposition (PVD) or other appropriate technologies, and deposited semiconductor material or electric conducting material are formed.Conducting element 440 can via the combination of such as photoetching and etching technics patterning.

See Fig. 4 H, form a drain region 420 in the bottom surface 408 of groove 406.Form one source pole district 422 in the end face 404 of semiconductor layer 402.Adjacent second insulator 432 in source area 422, and separated with drain region 420 by the first insulator 430 and the second insulator 432.Source area 422 or drain region 420 can being combined to form by such as photoetching and doping process.Such as, can be defined by photoetching process or the region of patterned source district 422 or drain region 420.Then, injection technology can be used to adulterate, to reach specific dopant species or concentration to the lithographic definition region of source area 422 or drain region 420.In certain embodiments, the injection technology of source area 422 and drain region 420 can comprise dopant implant in conducting element 440, with the electrical conductivity of modified conducting element 440.

See Fig. 5 A, in certain embodiments, the first insulator 530 is formed with shallow ditch groove separation process.Processing step described in Fig. 5 A to Fig. 5 H, it is similar to the content described by Fig. 4 A to Fig. 4 H, can be applicable to manufacturing installation 10B.

Then, the method for manufacturing installation 20A is described with corresponding diagram.From the structure described in Fig. 6 A, two or more openings can be formed, different from the only formation single opening shown in Fig. 4 C.As shown in Figure 6A, form the first opening 670a and the second opening 670b and penetrate hard mask 660 and the first insulator 630.First opening 670a and the second opening 670b extends to bottom surface 608 and the sidewall 610 of groove 606.First opening 670a and the second opening 670b can be formed by the combination such as carrying out photoetching and etching technics.By using photoetching process, patterning can be made to the photoresist layer be located on hard mask 660,

To form opening, the region of this opening corresponds to the hatch region of the first opening 670a and the second opening 670b.Then, by using etching technics, the hard mask 660 of a part and the first insulator 630 of a part is removed by the patterning opening of photoresist layer.The degree of depth and the side wall profile of the first opening 670a and the second opening 670b can be controlled and modify by the parameter (such as time, temperature or etch chemistries thing) controlling etching technics.

See Fig. 6 B, remove the first insulator 630 of hard mask 660 and a part, contact with the bottom surface 608 of the remainder with groove 606 that make the first insulator 630.Such as wet-etching technology, dry etch process can be used or effectively can be removed hard mask 660 by the hybrid technique of wet etching and dry etch process or other and not exclusively be removed the technique of the first insulator 630, removing the first insulator 630 of hard mask 660 and a part.In certain embodiments, the part that the first insulator 630 is removed comprise contiguous hard mask 660 first area and with the spaced second area of hard mask 660 tool.During the technique of the first insulator 630 removing hard mask 660 and part, the speed that removes of first area (contiguous hard mask 660) removes speed higher than second area (and hard mask 660 has interval).The speed that removes faster of first area caused by the torsion being imparted to first area (strain).This torsion may be caused by the internal stress of hard mask 660.

In certain embodiments, this torsion adjusts by the formation process adjusting hard mask 660.Such as, if hard mask 660 is silicon nitride layer, hard mask 660 can be formed by ion enhanced chemical vapor deposition processes.By using ion enhanced chemical vapor deposition processes, the internal stress of silicon nitride layer can by gas source (the such as NH used in the hard mask formation process of adjustment (such as depositing the technique of hard mask 660 on the first insulator 630) ₃, SiH ₄, H ₂) bias voltage, to control the torsion being imparted to the first insulator 630.In certain embodiments, hard mask 660 and the first insulator 630 remove speed by between the Formation period of hard mask layer 660 and the first insulator 630, control the density of hard mask layer 660 and the first insulator 630, stoichiometry or quality and adjust.Remove speed by what adjust hard mask 660 and the first insulator 630, thickness or the shape of the remainder of the first insulator 630 can be controlled.

See Fig. 6 C, form the second insulator 632 on the bottom surface 608 of groove 606.Second insulator 632 can be formed by being such as oxidized the bottom surface 608 of groove 606 or using such as chemical vapor deposition method, atom layer deposition process, molecular beam epitaxial process, physical gas-phase deposition or other suitable deposition processes to be formed.Second insulator 632 can via carrying out the combination of photoetching and etching technics and patterning.

See Fig. 6 D, form conducting element 640 on the second insulator 632.In certain embodiments, see Fig. 6 E, conducting element 640 is formed on the first insulator 630 and the second insulator 632.Conducting element 640 can by such as using chemical vapour deposition (CVD), ald, molecular beam epitaxy, physical vapour deposition (PVD) or other appropriate technologies, and deposited semiconductor material or electric conducting material are formed.Conducting element 640 can via the combination of such as photoetching and etching technics patterning.

See Fig. 6 F, form drain region 620 in the bottom surface 608 of groove 606.Source area 622 is also formed at the bottom surface of groove 606.Adjacent second insulator 632 in source area 622, and separated with drain region 620 by the first insulator 630 and the second insulator 632.Source area 622 or drain region 620 can being combined to form by such as photoetching and doping process.Such as, can be defined by photoetching process or the region of patterned source district 622 or drain region 620.Then, injection technology can be used to adulterate, to reach specific dopant species or concentration to the lithographic definition region of source area 622 or drain region 620.In certain embodiments, the injection technology of source area 622 and drain region 620 can comprise dopant implant to conducting element 640, with the electrical conductivity of modified conducting element 640.

See Fig. 7 A, in certain embodiments, the first insulator 730 is formed with shallow ditch groove separation process.Processing step described in Fig. 7 A to Fig. 7 F, it is similar to the content described by Fig. 6 A to Fig. 6 F, can be applicable to manufacturing installation 20B.

Then, the method for manufacturing installation 30A is described according to corresponding diagram.From the structure described in Fig. 8 A, based on structure as shown in Figure 4 D, form the second insulator 832 and be formed on the bottom surface 808 of groove 806.Second insulator 832 is adjacent to the first insulator 830.

See Fig. 8 B, form conducting element 840 on the second insulator 832.In certain embodiments, see Fig. 8 C, conducting element 840 is formed on the first insulator 830 and the second insulator 832.The semi-conducting material that conducting element 840 can be deposited by chemical vapour deposition (CVD), ald, molecular beam epitaxy, physical vapour deposition (PVD) or other appropriate technologies or electric conducting material are formed.Conducting element 840 can make patterning by the combination of such as photoetching and etching technics.

See Fig. 8 D, drain region 820 is formed at the end face 804 of semiconductor layer 802.Source area 822 is also formed at the bottom surface of groove 808.Source area 822 is adjacent to the second insulator 832, and is separated with drain region 820 by the first insulator 830 and the second insulator 832.Source area 822 or drain region 820 can being combined to form by such as photoetching and doping process.Such as, can be defined by photoetching process or the region of patterned source district 822 or drain region 820.Then, injection technology can be used to adulterate, to reach specific dopant species or concentration to the lithographic definition region of source area 822 or drain region 820.In certain embodiments, the injection technology of source area 822 or drain region 820 can comprise dopant implant to conducting element 840, with the electrical conductivity of modified conducting element 840.

See Fig. 9 A, in certain embodiments, the first insulator 930 is formed with shallow ditch groove separation process.Processing step described in Fig. 9 A to Fig. 9 D, it is similar to the content described by Fig. 8 A to Fig. 8 D, can be applicable to manufacturing installation 30B.

See Figure 10 A and Figure 10 B, in certain embodiments, by controlling the width of opening 1070 or the width by controlling groove 1006, the thickness of the first insulator 1030 is adjusted.In certain embodiments, see Figure 10 C, opening 1070 can be formed in sidewall 1010 place near groove 1006, adjust the thickness of the first insulator 1030.

In certain embodiments, combination in any in the group of selecting and forming from device 10A, 20A and 30A can be formed on identical semiconductor layer.In certain embodiments, these devices can share the processing step of some or all, and use same material, make these devices can manufacture in same steps.Such as, first insulator of device 10A and 20A can be formed on identical semiconductor layer simultaneously, and uses identical insulating material.

Combination in any in the group of selecting and forming from device 10B, 20B and 30B can be formed on identical semiconductor layer.In certain embodiments, these devices can share the fabrication steps of some or all, and use same material, make these devices can manufacture in same steps.Such as, first insulator of device 10B and 20B can be formed on identical semiconductor layer simultaneously, and uses identical insulating material.

In certain embodiments, device 10A, 10B, 20A, 20B, 30A or 30B, can be and such as have the field-effect transistor (FET) of conducting element as gate electrode.Conducting element also can be used as field effect electroplax, to reduce the puncture voltage of internal field and increase field-effect transistor.Aforesaid method can be used to form source area and drain region.Can use such as to inject and form extra doped region, with the conducting value of controlling filed effect transistor and conductivity.Such as, form source electrode and drain region by doped N-type doping, and the region doping P type doping under the second insulator is to form the FET with N-type channel region.In addition, can adulterate at the trench region contacted with the first insulator (it is also the region of semiconductor layer) doped N-type, using the drain extension regions such as FET, with the puncture voltage of source area to the drain region of the operating voltage or increase FET that increase FET.In above embodiment, by using the doping of contrary kenel, the FET with P type passage that there is drain electrode and extend can be formed.

In certain embodiments, device 10A, 10B, 20A, 20B, 30A or 30B can be such as diode, and wherein source area and drain region can be mixed with contrary dopant profile, to form P-N or P-I-N diode.In addition, can the trench region contacted with the first insulator be adulterated, to control conducting value or the puncture voltage of diode.

Embodiment of the present invention can do suitable reorganization or modification.Therefore, the above embodiments should be considered to be to illustrate, and are not used to limit the present invention.

Claims

1. a semiconductor device, is characterized in that, this semiconductor device comprises:

Semi-conductor layer;

One channel shaped is formed in an end face of this semiconductor layer, and this groove has:

One bottom surface; And

One sidewall;

This bottom surface of this groove is located in one drain region;

One source pole district is located at this end face of this semiconductor layer, and and this drain region there is interval;

One first insulator is located in this groove, between this drain region and this source area, and contacts with this bottom surface of this groove and this sidewall; And

One second insulator is located between this drain region and this source area, and is positioned on this end face of this semiconductor layer.

2. semiconductor device as claimed in claim 1, it is characterized in that, this semiconductor device also comprises one first conducting element, is located on this second insulator.

3. semiconductor device as claimed in claim 1, it is characterized in that, this semiconductor device also comprises one first conducting element, is located on this first insulator and this second insulator.

4. semiconductor device as claimed in claim 1, it is characterized in that, the end face of this groove, this drain region, this source area and this semiconductor layer is one first end face of one first groove, one first drain region, one first source area and this semiconductor layer separately, and this semiconductor device also comprises:

One second channel shaped is formed in one second end face of this semiconductor layer, and this second groove has:

One second bottom surface; And

One second sidewall;

This second bottom surface of this second groove is located in one second drain region;

This second bottom surface of this second groove is located in one second source area;

One the 3rd insulator is located in this second groove, between this second drain region and this second source area, and is positioned on this second bottom surface of this second groove; And

One the 4th insulator is located in this second groove, between this second source area and the 3rd insulator, and is positioned on this second bottom surface of this second groove.

5. semiconductor device as claimed in claim 4, it is characterized in that, this semiconductor device also comprises one second conducting element, is located on the 4th insulator.

6. semiconductor device as claimed in claim 4, it is characterized in that, this semiconductor device also comprises one second conducting element, is located on the 3rd insulator and the 4th insulator.

7. semiconductor device as claimed in claim 4, it is characterized in that, this first insulator and the 3rd insulator are formed by same material.

8. semiconductor device as claimed in claim 4, it is characterized in that, this first insulator and the 3rd insulator have different-thickness.

9. semiconductor device as claimed in claim 1, it is characterized in that, this end face of this groove, this drain region, this source area and this semiconductor layer is one first end face of one first groove, one first drain region, one first source area and this semiconductor layer separately, and this semiconductor device also comprises:

One second bottom surface; And

One second sidewall;

This second end face of this second groove is located in one second drain region;

One the 4th insulator is located in this second groove, is positioned on this second source area and the 3rd insulator, and is positioned on this second bottom surface of this second groove.

10. semiconductor device as claimed in claim 9, it is characterized in that, this semiconductor device also comprises one second conducting element, is located on the 4th insulator.

11. semiconductor devices as claimed in claim 9, it is characterized in that, this semiconductor device also comprises one second conducting element, is located on the 3rd insulator and the 4th insulator.

12. semiconductor devices as claimed in claim 9, is characterized in that, this first insulator and the 3rd insulator are formed by same material.

13. semiconductor devices as claimed in claim 9, is characterized in that, this first insulator and the 3rd insulator have different-thickness.

14. 1 kinds of semiconductor devices, is characterized in that, this semiconductor device comprises:

Semi-conductor layer;

One bottom surface; And

One sidewall;

One source pole district is located at this bottom surface of this groove;

This end face of this semiconductor layer is located in one drain region, and and this source area there is interval;

One first insulator is located in this groove, between this source area and this drain region, and contacts with the bottom surface of this groove and this sidewall; And

One second insulator is located between this source area and this first insulator, and is positioned on this bottom surface of this groove.

15. semiconductor devices as claimed in claim 14, it is characterized in that, this semiconductor device also comprises one first conducting element, is located on this second insulator.

16. semiconductor devices as claimed in claim 14, it is characterized in that, this semiconductor device also comprises one first conducting element, is located on this first insulator and this second insulator.

17. semiconductor devices as claimed in claim 14, it is characterized in that, this end face of this groove, this drain region, this source area and this semiconductor layer is one first end face of one first groove, one first drain region, one first source area and this semiconductor layer separately, and this semiconductor device also comprises:

One second bottom surface; And

One second sidewall;

18. semiconductor devices as claimed in claim 17, it is characterized in that, this semiconductor device also comprises one second conducting element, is located on the 4th insulator.

19. semiconductor devices as claimed in claim 17, it is characterized in that, this semiconductor device also comprises one second conducting element, is located on the 3rd insulator and the 4th insulator.

20. semiconductor devices as claimed in claim 17, is characterized in that, this first insulator and the 3rd insulator are formed by same material.

21. semiconductor devices as claimed in claim 17, is characterized in that, this first insulator and the 3rd insulator have different-thickness.

22. semiconductor devices as claimed in claim 14, it is characterized in that, this end face of this groove, this drain region, this source area and this semiconductor layer is one first end face of one first groove, one first drain region, one first source area and this semiconductor layer separately, and this semiconductor device also comprises:

One second bottom surface; And

One second sidewall;

23. semiconductor devices as claimed in claim 22, it is characterized in that, this semiconductor device also comprises one second conducting element, is located on the 4th insulator.

24. semiconductor devices as claimed in claim 22, it is characterized in that, this semiconductor device also comprises one second conducting element, is located on the 3rd insulator and the 4th insulator.

25. semiconductor devices as claimed in claim 22, is characterized in that, this first insulator and the 3rd insulator are formed by same material.

26. semiconductor devices as claimed in claim 22, is characterized in that, this first insulator and the 3rd insulator have different-thickness.

27. 1 kinds of semiconductor devices, is characterized in that, this semiconductor device comprises:

Semi-conductor layer;

One bottom surface; And

One sidewall;

This bottom surface of this groove is located in one drain region;

One source pole district is located at this bottom surface of this groove;

One first insulator is located in this groove, between this drain region and this source area, and is positioned on this bottom surface of this groove; And

One second insulator is established in this groove, between this first insulator and this source area, and is positioned on this bottom surface of this groove.

28. semiconductor devices as claimed in claim 27, it is characterized in that, this semiconductor device also comprises a conducting element, is located on this second insulator.

29. semiconductor devices as claimed in claim 27, it is characterized in that, this semiconductor device also comprises a conducting element, is located on this first insulator and this second insulator.

30. 1 kinds of semiconductor devices, is characterized in that, this semiconductor device comprises:

Semi-conductor layer;

One first and 1 second doped region is located on this semiconductor layer; And

One insulator is located between this first doped region and this second doped region, to define this semiconductor device when initiate mode, current conducting path in this semiconductor layer is between this first doped region and this second doped region, and this current conducting path arranges along the girth of this insulator and has a vertical component and a horizontal component.

The manufacture method of 31. 1 kinds of semiconductor devices, is characterized in that, this manufacture method comprises:

Form one first insulator on one first end face of semi-conductor layer, this first insulator to extend to below this first end face and with one first trench contact in this first end face, this first groove has:

One first bottom surface; And

One the first side wall, this first bottom surface and this first side wall contact with this first insulator;

Form one first hard mask on this first insulator;

Form one first opening penetrating this first hard mask and this first insulator, this first opening extends to this first bottom surface of this first groove;

Remove this first insulator of this first hard mask and a part, contact with this first bottom surface and this first side wall to make a remainder of this first insulator;

Form one second insulator on this first end face of this semiconductor layer, this second insulator is adjacent with this first insulator;

Form one first drain region in this first bottom surface of this first groove; And

Form one first source area in this first end face of this semiconductor layer, this first source area is adjacent with this second insulation layer, and by this first and this second insulator and this first drain region be separated by.

The manufacture method of 32. semiconductor devices as claimed in claim 31, is characterized in that, this manufacture method also comprises formation one first conducting element on this second insulator.

The manufacture method of 33. semiconductor devices as claimed in claim 31, is characterized in that, this manufacture method also comprises formation one first conducting element on this first insulator and this second insulator.

The manufacture method of 34. semiconductor devices as claimed in claim 31, is characterized in that, the step forming this first insulator comprises and forms this first insulator with a silicon location oxidation of silicon process or a shallow ditch groove separation process.

The manufacture method of 35. semiconductor devices as claimed in claim 31, it is characterized in that, the part that this first insulator is removed comprises:

One first area being adjacent to this hard mask; And

One with the spaced second area of this hard mask tool;

This first insulator wherein removing this first hard mask and this part also comprise with relative to this second area faster speed remove this first area.

The manufacture method of 36. semiconductor devices as claimed in claim 31, it is characterized in that, this manufacture method also comprises:

Form one the 3rd insulator on one second end face of this semiconductor layer, the 3rd insulator to extend to below this second end face and touches with one second trench intersection in this second end face, and this second groove has:

One second bottom surface; And

One second sidewall;

Form one second hard mask on the 3rd insulator;

Form one second opening and one the 3rd opening penetrates this second hard mask and the 3rd insulator, this second opening and the 3rd opening extend to this second bottom surface and this second sidewall of this second groove;

Remove the 3rd insulator of this second hard mask and a part, contact with this second bottom surface of this second groove to make a remainder of the 3rd insulator;

Form one the 4th insulator on this second bottom surface of this second groove, the 4th insulator is adjacent with the 3rd insulator;

Form one second drain region in this second bottom surface of this second groove; And

Form one second source area in this second bottom surface of this second groove, this second source area is adjacent with the 4th insulator, and is flatly separated by by the 3rd and the 4th insulator and this second drain region.

The manufacture method of 37. semiconductor devices as claimed in claim 36, is characterized in that, this manufacture method also comprises formation one second conducting element on the 4th insulator.

The manufacture method of 38. semiconductor devices as claimed in claim 36, is characterized in that, this manufacture method also comprises formation one second conducting element on the 3rd and the 4th insulator.

The manufacture method of 39. semiconductor devices as claimed in claim 36, is characterized in that, this first insulator and the 3rd insulator are formed in a single processing step.

The manufacture method of 40. semiconductor devices as claimed in claim 36, is characterized in that, the step forming the 3rd insulator comprises and forms the 3rd insulator with a silicon location oxidation of silicon process or a shallow ditch groove separation process.

The manufacture method of 41. semiconductor devices as claimed in claim 31, it is characterized in that, this manufacture method also comprises:

Form one the 3rd insulator on one second end face of this semiconductor layer, the 3rd insulator to extend to below this second end face and with one second trench contact in this second end face, this second groove has:

One second bottom surface; And

One second sidewall;

Form one second hard mask on the 3rd insulator;

Form one second opening and penetrate this second hard mask and the 3rd insulator, this second opening extends to this second bottom surface of this second groove;

Remove the 3rd insulator of this second hard mask and a part, contact with this second bottom surface and this second sidewall to make a remainder of the 3rd insulator;

Form one second drain region in this second end face of this second semiconductor layer; And

Form one second source area in this second bottom surface of this second groove, this second source area is adjacent with the 4th insulator, and is separated by by the 3rd and the 4th insulator and this second drain region.

The manufacture method of 42. semiconductor devices as claimed in claim 41, is characterized in that, this manufacture method also comprises formation one second conducting element on the 4th insulator.

The manufacture method of 43. semiconductor devices as claimed in claim 41, is characterized in that, this manufacture method also comprises formation one second conducting element on the 3rd insulator and the 4th insulator.

The manufacture method of 44. semiconductor devices as claimed in claim 41, is characterized in that, this first insulator and the 3rd insulator are formed in a single processing step.

The manufacture method of 45. semiconductor devices as claimed in claim 41, is characterized in that, the step forming the 3rd insulator comprises and forms the 3rd insulator with a silicon location oxidation of silicon process or a shallow ditch groove separation process.

The manufacture method of 46. 1 kinds of semiconductor devices, is characterized in that, this manufacture method comprises:

One first bottom surface; And

Form one first hard mask on this first insulator;

Form one first opening and penetrate this first hard mask and this first insulator, this first opening extends to this first bottom surface of this first groove;

Form one second insulator on this first bottom surface of this first groove, this second insulator is adjacent with this first insulator;

Form one first drain region in this first end face of this semiconductor layer; And

Form one first source area in this first bottom surface of this first groove, this first source area is adjacent with this second insulator.

The manufacture method of 47. semiconductor devices as claimed in claim 46, is characterized in that, this manufacture method also comprises formation one first conducting element on this second insulator.

The manufacture method of 48. semiconductor devices as claimed in claim 46, is characterized in that, this manufacture method also comprise formation one first conducting element in this first and this second insulator on.

The manufacture method of 49. semiconductor devices as claimed in claim 46, is characterized in that, the step forming this first insulator comprises and forms this first insulator with a silicon location oxidation of silicon process or a shallow ditch groove separation process.

The manufacture method of 50. semiconductor devices as claimed in claim 46, it is characterized in that, this part that this first insulator is removed comprises:

One first area being adjacent to this hard mask; And

One away from the second area of this hard mask;

The manufacture method of 51. semiconductor devices as claimed in claim 46, it is characterized in that, this manufacture method also comprises:

One second bottom surface; And

One second sidewall;

Form one second hard mask on the 3rd insulator;

The manufacture method of 52. semiconductor devices as claimed in claim 51, is characterized in that, this manufacture method also comprises formation one second conducting element on the 4th insulator.

The manufacture method of 53. semiconductor devices as claimed in claim 51, is characterized in that, this manufacture method also comprises formation one second conducting element on the 3rd and the 4th insulator.

The manufacture method of 54. semiconductor devices as claimed in claim 51, is characterized in that, this first insulator and the 3rd insulator are formed in a single processing step.

The manufacture method of 55. semiconductor devices as claimed in claim 54, is characterized in that, the step forming the 3rd insulator comprises and forms the 3rd insulator with a silicon location oxidation of silicon process or a shallow ditch groove separation process.

The manufacture method of 56. 1 kinds of semiconductor devices, is characterized in that, this manufacture method comprises:

Form one first insulator on an end face of semi-conductor layer, this first insulator to extend to below this end face and with the trench contact in this end face, this groove has:

One bottom surface; And

One sidewall;

Form a hard mask on this first insulator;

Form one first opening and one second opening penetrates this hard mask and this first insulator, this first opening and this second opening extend to this bottom surface and this sidewall of this groove;

Remove this first insulator of this hard mask and a part, contact with this bottom surface of the remainder with this groove that make this first insulator;

Form one second insulator on this bottom surface of this groove, this second insulator is adjacent with this first insulator;

Form a drain region in this bottom surface of groove; And

Form one source pole district in this bottom surface of this groove, this source area is adjacent with this second insulator, and is separated by by this first insulator and this second insulator and this drain region.

The manufacture method of 57. semiconductor devices as claimed in claim 56, is characterized in that, this manufacture method also comprises formation one conducting element on this second insulator.

The manufacture method of 58. semiconductor devices as claimed in claim 56, is characterized in that, this manufacture method also comprises formation one conducting element on this first insulator and this second insulator.

The manufacture method of 59. semiconductor devices as claimed in claim 56, is characterized in that, the step forming this first insulator comprises and forms this first insulator with a silicon location oxidation of silicon process or a shallow ditch groove separation process.

The manufacture method of 60. semiconductor devices as claimed in claim 56, it is characterized in that, this part that this first insulator is removed comprises:

One first area being adjacent to this hard mask; And

One away from the second area of this hard mask;

The manufacture method of 61. 1 kinds of semiconductor devices, is characterized in that, this manufacture method comprises:

Form an insulator on an end face of semi-conductor layer, this insulator to extend to below this end face and with the trench contact in this end face, this groove has:

One bottom surface; And

One sidewall, this bottom surface and this sidewall contact with this insulator;

Form a hard mask on this insulator;

Form an opening and penetrate this hard mask and this insulator, this opening extends to this bottom surface and this sidewall of this groove; And

Remove this insulator of this hard mask and a part, with this bottom surface of the remainder and this groove that make this insulator and this sidewall contact, wherein a thickness of a remainder of this first insulator is by the Position Control of the width or this opening that adjust this opening.