CN105261328A - ARM and FPGA-based LED display screen control system - Google Patents
ARM and FPGA-based LED display screen control system Download PDFInfo
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Abstract
The invention relates to the LED display technical field and relates to an ARM and FPGA-based LED display screen control system. The LED display screen control system includes an embedded microprocessor, an FPGA chip, a driving circuit, a display screen, a Flash, an SDRAM, an X-system RAM, a Y-system RAM, an Ethernet interface and an upper computer; the embedded microprocessor is connected with the FPGA chip; the FPGA chip is connected with the display screen through the driving circuit; the X-system RAM and the Y-system RAM are both connected with the FPGA; the Flash and the SDRAM are both connected with the embedded microprocessor; and the embedded microprocessor is connected with the upper computer through the Ethernet interface. With the system of the invention adopted, an excellent solution is provided for A large-display area and frequent-display content switching large-screen LED display control system.
Description
Technical field
The present invention relates to technical field of LED display, particularly relate to a kind of LED display control system based on ARM and FPGA.
Background technology
In recent years, along with flat panel display constantly progress, people's screen LED display oneself be widely used in stadiums, airport, the places such as station, for showing word, figure, the multimedia messages rivers such as animation and dynamic video image are larger for meeting viewing area, displaying contents switches frequent application scenario of waiting relatively complexity, be at present the LED screen control system of core with FPGA and be that the LED display control system of core has been applied to people and shields LED and control with 32-bit microprocessor, but with FPGA be core LED display control system design implement more complicated, and needs are the LED display control system underaction of core with 32-bit microprocessor based on high performance fpga chip, when changing LED screen display size, need significantly to revise system.
Summary of the invention
The invention provides a kind of LED display control system based on ARM and FPGA, this system is that viewing area is comparatively large, displaying contents switches Large LED-screen Display Control System frequently and provides good solution.
To achieve these goals, the present invention adopts following technical scheme: a kind of LED display control system based on ARM and FPGA, comprises embedded microprocessor, fpga chip, driving circuit, display screen, Flash, SDRAM, X body RAM, Y body RAM, Ethernet interface and host computer; Described embedded microprocessor is connected with fpga chip, described fpga chip is connected with display screen by driving circuit, described X body RAM is connected with fpga chip respectively with Y body RAM, described Flash with SDRAM is connected with embedded microprocessor respectively, and described embedded microprocessor is connected with host computer by Ethernet interface.
Preferably, described embedded microprocessor adopts 32 Embedded RISC microprocessors based on ARM core.
Preferably, the model of described 32 Embedded RISC microprocessors based on ARM core is S3C2440.
Preferably, the model of described SDRAM is K4S561632D.
Preferably, the model RTL8019AS of described Ethernet interface.
Preferably, the model of described Flash is K9F1208.
Preferably, the model of described X body RAM and Y body RAM is IDT71V3577.
Compared with traditional LED screen control system based on common single-chip microcomputer, this system, when significantly not increasing system cost, can be supported the display of the full-color graph text information of 256 gray levels, can play full-color animation; The data (64MB) of larger capacity can be stored; By Ethernet quick data transfering, all right constructing local network, realizes Long-distance Control and management.This system is that viewing area is comparatively large, displaying contents switches Large LED-screen Display Control System frequently and provides good solution.
Accompanying drawing explanation
Fig. 1 is structural representation of the present invention;
Fig. 2 is the circuit diagram of the interface of S3C2440 and ADRAM;
Fig. 3 is the interface circuit figure of S3C2440 and NANDFLASH;
Fig. 4 is scanning memory circuit schematic diagram.
Embodiment
Below in conjunction with embodiment, the present invention is described in detail.
Based on a LED display control system of ARM and FPGA, comprise embedded microprocessor, fpga chip, driving circuit, display screen, Flash, SDRAM, X body RAM, Y body RAM, Ethernet interface and host computer; Described embedded microprocessor is connected with fpga chip, described fpga chip is connected with display screen by driving circuit, described X body RAM is connected with fpga chip respectively with Y body RAM, described Flash with SDRAM is connected with embedded microprocessor respectively, and described embedded microprocessor is connected with host computer by Ethernet interface.
Described embedded microprocessor adopts 32 Embedded RISC microprocessors based on ARM core.
The model of described 32 Embedded RISC microprocessors based on ARM core is S3C2440.
The model of described SDRAM is K4S561632D.
The model RTL8019AS of described Ethernet interface.
The model of described Flash is K9F1208.
The model of described X body RAM and Y body RAM is IDT71V3577.
The design proposal program that the present invention proposes a kind of novel embedded LED colorful display screen controller adopts ARM9 chip to be main control unit fpga chip to be circuit structure that scan control unit adopts this scheme effectively can simplify display screen to improve dirigibility and the reliability of whole control system.
The composition of system and principle of work: this system adopts based on a new generation's 32 Embedded RISC microprocessors of ARM core and SDRAM composition control center, scan control module is formed by fpga chip and binary RAM, using FLASH as memory module, adopt the control system of Ethernet transmission data composition LED screen.System chart as shown in Figure 1.Picture programming program roughly process is: main frame passes through TFTP agreement by picture transfer to system ethernet interface module, ethernet interface module analysis protocol receives image data, then transfer data to S3C2440, the data received write memory module NANDFLASH S3C2440 when showing is read data in FLASH and transfers data to scan control module by SPI interface and be transferred in LED screen after scan control resume module and show by S3C2440.
The type selecting of ARM microprocessor: S3C2440 is a processor based on ARM920T core.Its feature is specific as follows:
(1) ARM920T core is made up of ARM9TDMI memory management unit (MMU) and high-speed cache three part.Wherein MMU can managing virtual internal memory, and high-speed cache is made up of independently 16KB address 16KB data high-speed Cache.
(2) sheet there is a lcd controller, the UART of 3 passages, the SPI of 2 passages and the DMA of 4 passages.
(3) NANDFLASH System guides is supported, system administration manager (chip selection logic and sdram controller).
(4) processor working frequency is the highest can reach 400MHz.
Comprehensive These characteristics, the frequency of operation of S3C2440 processor greatly improves the travelling speed of system, this frequency can make processor run on WindowsCE easily, and the operating systems such as Linux and comparatively complicated information processing, when can greatly reduce software development; The internal interrupt that S3C2440 is powerful, the poll being convenient to TCP/IP calls; S3C2440 has 117 multi-functional I/O ports of general programmable to be conveniently connected with ethernet controller RTL8019AS; S3C244C has abundant peripheral hardware resource, can expansion in everybody peripheral circuits, reduces the complexity of system, so selected S3C2440 is the CPU of this system.
The design of sdram interface circuit: SDRAM (SynchronousDRAM) i.e. synchronous dram) SDRAM is mainly used as the running space of program in systems in which, upon power-up of the system, first MCU reads start-up code from reseting address 0x0, after the initialization of completion system, program code is called in SDRAM and is run, to improve the travelling speed of system simultaneously, system and user stack, service data are also all placed in SDRAM.
In native system, SDRAM selects the K4S561632D of SAMSUNC company, and it is the synchronous dram of 4Mxl6bitx4bank, and capacity is 32MB.32 SDRAM accumulator systems are built with 2 K4S561632D parallel connections, wherein a slice is high 16, another sheet is low 16, data-bus width is made to reach 32bit, total volume reaches 64MB, by the bank6 of its Address space mappinD at S3C2440, the bank6 chip selection signal by S3C2440 is connected to the CS end of two panels K4S561632D.The connection of S3C2440 and wherein a slice SDRAM as shown in Figure 2.
Ethernet interface circuit designs: for solving the remote transmission problem of data, devise Ethernet interface.Ethernet circuit module adopt that RealTek company produces, with the FDX Ethernet controller RTL8019AS of plug-and-play feature, Ethernet expansion is carried out to S3C2440, its principal character comprises: support IEEE802.3; Full duplex transmitting-receiving can reach 10Mb/s simultaneously; The SRAM for receiving and dispatching buffering of built-in 16KB; Support that 8/16 bit data bus, 8 interruption application lines and 16 I/O base address are selected; Support 10Base5,10Base2,10BaseT and connected medium RTL8019AS and S3C2440 can be detected automatically to select wire jumper pattern, do not use EEPROM, also do not use isa bus, each pin mode of connection is that JP connects high level, BS [4..0] ground connection, only uses BROM; IOS [2..0] ground connection internal register base address is from 300H; IRQ2/9 is used to do interrupt request pin; AUI connects low level, and interface adopts BNC mode, uses twisted-pair feeder or concentric cable; PL1PLO connects low level, automatically detects Ethernet interface type; TPIN and TPOUT signal, after coupling mechanism FB202, is connected to external ethernet by RJ45.
The design of memory module: screen control system needs to store binary executable code, it requires that data are not lost after system power failure also to need to store the data such as a large amount of word and picture, and need larger memory capacity, therefore system select FLASH memory to consider jumbo NORFLASH cost is higher and NANDFLASH has good cost performance and system interface, and S3C2440 supports NANDROM Starting mode, so native system memory module has selected the Large Copacity of Samsung, highly reliable NANDFLASH storer K9F1208.This device memory capacity is 64MB, and in addition also have the free storage of 2048KB, its I/O mouth is the multiplexing port of data line and address wire.The interface circuit of S3C2440 and NANDFLASH as shown in Figure 3.
The design of scan control module: scan control module is the important component part in LED display control program, because LED screen display is that continuous high speed carries out, new data to be received while the high-velocity scanning completing image in real time, to upgrade screen, therefore data cache treatment circuit to be had, formed by a slice fpga chip and binary RAM the RGB data realized S3C2440 exports to prevent this module of obliterated data in scanning process to cushion, then under control of the synchronization signal, table tennis read-write operation is carried out to binary RAM.So-called ping-pong operation is exactly when fpga chip reads the data in X body RAM, in Y body RAM, write data simultaneously, the read operation of Y body RAM is carried out when FPGA writes X body RAMI conversely, which enhance the speed of fpga chip process data, receive while achieving the high-velocity scanning of image and new data.
Wherein, that the fpga chip in module is selected is CycloneEP1C6, it is the high performance-cost ratio fpga chip that Altera releases, its density is 5980 logical blocks (LE), comprise the RAM block (M4K module) of 20 128x36 positions, total ram space reaches 92160.Embedded 2 phaselocked loop (PLL) circuit are with one for being connected the specific double data rate (DDR) interface of SDRAM, and frequency of operation is up to 200MHz.User can be 185 with I/O pin, meets system needs well.
The display resolution 128*64 of system led display screen, every two field picture needs capacity to be 192k, and the model of Systematic selection Integrated Device Technology, Inc. is the high-speed SRAM of IDT71V3577, and its capacity is 128Kx32bit, so need 2 IDT71V3577 can store a two field picture.Therefore system adopts 4 IDT71V357 to form binary RAM and deposits display data.
Scan control logic circuit design structure as shown in Figure 4.Address control unit produces and writes the writing address of display-memory and the reading address of storer, decided to connect with storer or read data and read address and connect the needs shown for meeting this screen image with storer, display control circuit is designed to gray scale display mode writing data and write address by read-write controller.4 bit parallel data are converted to the serial data having half-tone information needed for 16 LED display through gray scale decoding.
Because X, Y two groups of storeies carry out ping-pong operation, within the time of reception one frame parallel data, 16 bit-serial data streams after decoding are sent to LED display, the valid data flow rate of input is 2Mbit/s, and the speed of sense data stream just reaches 32Mbit/s.If directly give display screen by the serial data stream of 32Mbit/s, then speed is too high and make to process.The display screen of this system is that 128 row X64 arrange, and system adopts 8 line scanning modes, and the scanning element that whole scanning area is arranged by 16 8 row X64 forms.16 scanning elements scan simultaneously, then can reduce the speed of data stream.Data write storer chronologically, become the serial data stream of red, green, blue three 32Mbit/s after reading through gray scale decoding, for scanning display.The speed of the serial data stream after process is 32/16=2 (Mbit/s), for display circuit when after sequential write storer, can not can sequentially read by raw address.Control readout sequence, allow address beat ground sense data, namely reading order be: the 1st character in the 1st scanning element, the 1st character of the 2nd unit ..., the 1st character of the 16th unit; Then the 2nd the word instrument reading Unit 1 ~ 16 again read the 3rd word bamboo of Unit 1 ~ 16, by that analogy, till running through.These operations are all completed by read-write controller and address control unit.Isochronous controller is clocking, latch signal and line scan signals simultaneously.
Design of System Software: the software of whole system comprises two parts, the data message that host computer application software and embedded control unit software upper computer software editor show in LED display, and realize the communication with slave computer; Embedded control unit software simulating data receiver and storage, data export and image display pattern conversion thus the control that achieves LED display.
Host computer application software: host computer application software visual c++ is write, mainly realizes the editor of display information and the function of communication.This running software under Windows98/NT environment, have friendly graphical user circle and, the function be user-friendly to has:
(1) display information is edited, modify feature also directly can call 256 look picture file (* in WINDOWS.bmp)。
(2) on host computer, preview is carried out to ensure good display effect to the content of display.
(3) information transmission is realized the renewal of aobvious not data to system ethernet interface module by the agreement according to host computer and ethernet interface module.
The software of embedded control unit: the following three zones of software simulating of embedded control unit: data receiver and storage, data export and image display pattern conversion.
(1) according to the communications protocol between display screen and host computer, carry out communication with host computer, receive display data, stored in flash storage.
(2) colourful image display effects such as data to be shown being taken out from flash storage, data are processed, realization moves, move down, move to left, move to right.
(3) transfer data to scan control module by SPI interface, data are converted to the data of applicable LED display driving circuit form by serioparallel exchange etc. by fpga chip, and the screen then passing to LED display shows.
Compared with traditional LED display control system based on common single-chip microcomputer, this system, when significantly not increasing system cost, can be supported the display of the full-color graph text information of 256 gray levels, can play full-color animation; The data (64MB) compared with people's capacity can be stored; By Ethernet quick data transfering, all right constructing local network, realizes Long-distance Control and management.This system is that viewing area is comparatively large, displaying contents switches Large LED-screen Display Control System frequently and provides good solution.
Claims (7)
1. based on a LED display control system of ARM and FPGA, it is characterized in that: comprise embedded microprocessor, fpga chip, driving circuit, display screen, Flash, SDRAM, X body RAM, Y body RAM, Ethernet interface and host computer; Described embedded microprocessor is connected with fpga chip, described fpga chip is connected with display screen by driving circuit, described X body RAM is connected with fpga chip respectively with Y body RAM, described Flash with SDRAM is connected with embedded microprocessor respectively, and described embedded microprocessor is connected with host computer by Ethernet interface.
2. the LED display control system based on ARM and FPGA according to claim 1, is characterized in that: described embedded microprocessor adopts 32 Embedded RISC microprocessors based on ARM core.
3. the LED display control system based on ARM and FPGA according to claim 2, is characterized in that: the model of described 32 Embedded RISC microprocessors based on ARM core is S3C2440.
4. the LED display control system based on ARM and FPGA according to claim 1, is characterized in that: the model of described SDRAM is K4S561632D.
5. the LED display control system based on ARM and FPGA according to claim 1, is characterized in that: the model RTL8019AS of described Ethernet interface.
6. the LED display control system based on ARM and FPGA according to claim 1, is characterized in that: the model of described Flash is K9F1208.
7. the LED display control system based on ARM and FPGA according to claim 1, is characterized in that: the model of described X body RAM and Y body RAM is IDT71V3577.
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| CN107256200A (en) * | 2017-07-13 | 2017-10-17 | 北京无线电测量研究所 | The system and method for one kind of multiple EDID data selectively output |
| CN107452322A (en) * | 2016-05-30 | 2017-12-08 | 深圳市赛菲姆科技有限公司 | A kind of LED erects row curtain-type display control method |
| CN107799056A (en) * | 2017-12-13 | 2018-03-13 | 太仓鼎诚电子科技有限公司 | A kind of LED display control system based on FPGA |
| CN108419336A (en) * | 2018-04-09 | 2018-08-17 | 横店集团得邦照明股份有限公司 | A kind of LED lamplight screen control system and its implementation |
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| CN107452322A (en) * | 2016-05-30 | 2017-12-08 | 深圳市赛菲姆科技有限公司 | A kind of LED erects row curtain-type display control method |
| CN107256200A (en) * | 2017-07-13 | 2017-10-17 | 北京无线电测量研究所 | The system and method for one kind of multiple EDID data selectively output |
| CN109920365A (en) * | 2017-12-11 | 2019-06-21 | 上海航空电器有限公司 | A kind of system and method for display human eye vision evaluation sighting target |
| CN107799056A (en) * | 2017-12-13 | 2018-03-13 | 太仓鼎诚电子科技有限公司 | A kind of LED display control system based on FPGA |
| CN108419336A (en) * | 2018-04-09 | 2018-08-17 | 横店集团得邦照明股份有限公司 | A kind of LED lamplight screen control system and its implementation |
| CN108665847A (en) * | 2018-05-17 | 2018-10-16 | 深圳市灵星雨科技开发有限公司 | A kind of dark bright method of LED display elimination |
| CN108665847B (en) * | 2018-05-17 | 2020-10-23 | 深圳市灵星雨科技开发有限公司 | Method for eliminating dark and bright of LED display screen |
| CN109548236A (en) * | 2018-12-05 | 2019-03-29 | 大峡谷照明***（苏州）股份有限公司 | A kind of master controller of LED illumination System and its layout designs on PCB |
| CN110264945A (en) * | 2019-06-27 | 2019-09-20 | 上海灵信视觉技术股份有限公司 | A kind of vehicle mounted LED screen control system |
| CN112346679A (en) * | 2019-08-07 | 2021-02-09 | 西安诺瓦星云科技股份有限公司 | Multi-display screen control system, display system and multi-display screen control method |
| CN112346679B (en) * | 2019-08-07 | 2024-01-09 | 西安诺瓦星云科技股份有限公司 | Multi-display control system, display system and multi-display control method |
| CN114822385A (en) * | 2022-05-27 | 2022-07-29 | 中科芯集成电路有限公司 | Write protection circuit of LED display driving chip |
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Application publication date: 20160120 |