CN105260983B - 5/3 small wave converting method based on HyperX platforms - Google Patents
5/3 small wave converting method based on HyperX platforms Download PDFInfo
- Publication number
- CN105260983B CN105260983B CN201510765015.1A CN201510765015A CN105260983B CN 105260983 B CN105260983 B CN 105260983B CN 201510765015 A CN201510765015 A CN 201510765015A CN 105260983 B CN105260983 B CN 105260983B
- Authority
- CN
- China
- Prior art keywords
- data
- block
- hyperx
- parallel processing
- platforms
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Compression Or Coding Systems Of Tv Signals (AREA)
- Compression Of Band Width Or Redundancy In Fax (AREA)
Abstract
A kind of 5/3 small wave converting method of the platform based on multi-core processor HyperX, step are：Conversion raw image format, data are read by row, send left and right edges extension after data segment, judge whether be receive for the first time data block, judge to receive line number whether be equal to 34, judge to receive line number whether equal to 32, composition data block, extend lower edges, 5/3 wavelet transformation, send data to receiving unit, global memory is entered by row write, judging whether all video data blocks and be written global memory, by the data copy in global memory to host hard drive.The present invention reduces Data duplication transmission by the Data expansion edge of pre-stored image block；Initial data is read by pressing row, address saltus step is reduced and improves reading speed；By improving the access speed of data to 5/3 wavelet transformation of carry out of image block, avoid image data repeatedly with the interaction of global memory.
Description
Technical field
The present invention relates to technical field of image processing, one kind in Image Compression field is further related to based on more
The method that core processor HyperX platforms realize 5/3 wavelet transformation.The present invention is unique using multi-core processor HyperX platforms
The processing framework of communication pattern and highly-parallel realizes 5/3 wavelet transformation with low power parallel, solves wavelet transformation speed
Slowly, development difficulty is high, and the big problem of power consumption, the present invention can be used for the image compression encoding and video data to various digital devices
The fields such as network transmission.
Background technology
Wavelet transformation has been widely used for signal analysis, image procossing, pattern-recognition, medical imaging and diagnosis, number
The fields such as watermark, especially play a significant role in image compression algorithm.The JPEG2000 images that joint photographic experts group is released
The CCSDS Standard of image compression that compression standard and Space Data Systems Advisory Committee are released all employs the change of Discrete lifting small echo
It changes.Image compression system based on Discrete lifting Wavelet Transformation Algorithm appears in the fields such as academic, scientific research and industry, and studies
Efficient one of the vital task for realizing always each field face of these algorithms.Graphics processing unit GPU, general signal processing
Device DSP, on-site programmable gate array FPGA etc. all have been used for realizing efficient wavelet transformation.Graphics processing unit GPU and
The speed of general purpose signal processor DSP is high, and development difficulty is low, but power consumption is higher；On-site programmable gate array FPGA is low in energy consumption,
But development difficulty is high, in order to fast implement high speed, the low-power consumption processing of wavelet transformation, the present invention, which uses, is based on multi-core processor
The platform of HyperX accelerates wavelet transformation.
Patent " the multistage multiplexing wavelet transformer based on the FPGA " (patent application of Xian Electronics Science and Technology University in its application
Number：CN201310476968.7, publication number：CN103533357A a kind of multistage multiplexing small echo change based on FPGA is disclosed in)
Parallel operation.The wavelet transformer includes first order row converter, first order rank transformation device, time division multiplexing row converter, time division multiplexing
Rank transformation device, wavelet coefficient separator and intermediate buffer.When the wavelet transformer technology mainly solves converter major part
Between it is idle, the problem of not making full use of.The deficiency that the patented technology still has is that the row conversion process of data terminates it
Afterwards, column processing could be carried out, data will be interacted repeatedly with global memory, and processing speed is slow, and existing FPGA device works
Frequency is higher, and stability is poorer, and development difficulty is high, and the development cycle is long.
Xian Electronics Science and Technology University is in a kind of patent " side realizing fast wavelet transform by piecemeal with GPU of its application
Method " (number of patent application：CN201310055242.6, publication number：CN103198451A it is disclosed in) and a kind of passing through piecemeal with GPU
The method for realizing fast wavelet transform.This method is by deblocking parallel processing, including copies original image, deblocking, number
According to data after extension, copy data to shared drive, row transformation, rank transformation, cancellation Data expansion, copy transformation to host memory
The step of.This method mainly solves the problems, such as that prior art wavelet transformation is slow-footed, by by deblocking, avoiding data
With the interaction of global memory, the speed of image Parallel Processing is improved.But the deficiency that the patented technology still has is, it will
Data are read by block from memory, and frequent address saltus step causes data reading to slow, and real using graphics processing unit GPU
Existing wavelet transformation, development difficulty is higher, and power consumption is larger.
Invention content
It is an object of the invention to overcome the shortcomings of above-mentioned prior art, propose a kind of flat based on multi-core processor HyperX
The method that platform realizes 5/3 wavelet transformation is read former using the processing framework of platform unique communication pattern and highly-parallel by row
Beginning data are sent to multiple parallel processing elements after segment extension, form that carry out 5/3 after image block small in parallel processing element
Wave conversion, the development cycle is short, and complexity is low.
The present invention reduces the repetition transmission of data, improves transmission by the Data expansion edge for the upper image block that prestores
Speed；Initial data is read by pressing row, address saltus step is reduced and improves data reading speed；By in each parallel processing element
In PE to 5/3 wavelet transformation of carry out of video data block improve data access speed, avoid image data repeatedly with the overall situation
The interaction of memory；Pass through the parallel processing speed for improving entire image of image block and image block.
To achieve the above object, step of the invention includes as follows：
(1) format of original image is converted：
(1a) chooses the original image that a width suffix is .png formats from image set, converts the original image to suffix
For the file of .txt formats；
(1b) distributes Liang Kuai global memories A and B in Double Data Rate synchronous DRAM DDR；
Suffix is copied to for the raw image data in the file of .txt formats in global memory A by (1c)；
(2) it presses row and reads data：
(2a) creates an array C in the data-reading unit of multi-core processor HyperX platforms；
The data-reading unit of (2b) multi-core processor HyperX platforms, data line is successively read from global memory A,
It will be in read row data deposit array C；
(3) data segment after left and right edges extension is sent：
Row data in array C are divided into M data segment by (3a), and the length of each data segment is N, and wherein M indicates that 5/3 is small
The sum of wave conversion parallel processing element；
Each data segment is respectively extended two pixels by (3b) to the left and right, to being in the inductile data in former row data both ends
Section, then centered on the pixel at edge, image copying pixel extends two pixels, and the data segment, length after extension becomes (N+
4)；
Data segment after extension is sent to each parallel processing element of multi-core processor HyperX platforms by (3c) successively,
Each data segment is sent to a corresponding parallel processing element；
(4) judge whether it is to receive data block for the first time, if so, thening follow the steps (5), otherwise, execute step (6)；
(5) judge to receive whether line number is equal to 34, if so, thening follow the steps (7), otherwise, execute step (2)；
(6) judge to receive whether line number is equal to 32, if so, thening follow the steps (7), otherwise, execute step (2)；
(7) composition data block：
Each parallel processing element of (7a) multi-core processor HyperX platforms, sequence receiving data segment composition data block；
(7b) creates an array E in the parallel processing element of multi-core processor HyperX platforms, for storing data
The last four rows edge data of block；
(8) lower edges are extended：
(8a) if data block be multi-core processor HyperX platforms parallel processing element receive first data block,
Then symmetric extension top edge；
(8b) is if the last one data that the parallel processing element that data block is multi-core processor HyperX platforms receives
Block, then symmetric extension lower edge；
(8c) is if first data that the parallel processing element that data block is not multi-core processor HyperX platforms receives
Data in array E are then added to the foremost of data block by block and the last one data block, realize the upper and lower of growth data block
Edge；
(8d) uses the last four rows data update array E of data block after extension；
(9) 5/3 wavelet transformations：
The parallel processing element of (9a) multi-core processor HyperX platforms carries out at 5/3 small echo the image block after extension
Reason；
(9b) deletes the two row data each up and down of image block, two column datas of each deletions in left and right, obtains after 5/3 wavelet transformation greatly
The small video data block for being divided into four subband blocks for N*32 pixel, wherein N indicates that the columns of video data block, * indicate to be multiplied
Operation；
(10) receiving unit is sent data to：
(10a) sends out the data line of each first subband block of parallel processing element of multi-core processor HyperX platforms
It send to the receiving unit in multi-core processor HyperX platforms；
(10b) sends first subband data line in the block of all parallel processing elements successively；
(10c) sends first subband of all parallel processing elements remaining row data in the block successively；
(10d) sends the row data of the other three subband block successively；
(11) enter global memory by row write：
(11a) creates array F on multi-core processor HyperX platform receiving units；
(11b) multi-core processor HyperX platform receiving units receive first subband sent from parallel processing element
First data segment, by the data segment of reception write-in array F；
(11c) receives first data segment of first subband that all parallel processing elements are sent successively, by reception
Array F is written in data segment；
(11d) will be in the data write-in global memory B in array F；
(11e) successively will be in the remainder data section write-in global memory B of first subband；
(11f) all data segments of its excess-three height band are written in global memory B successively；
(12) judge whether that global memory is written in all video data blocks, if so, (13) are thened follow the steps, otherwise,
Execute step (2)；
(13) by the data copy in global memory to host hard drive：
(13a) is by the data write-in suffix in global memory B in the file of .txt formats；
(13b) is by suffix in the file copy to host hard drive of .txt formats.
The present invention compared with prior art, has the following advantages that：
First, since the present invention utilizes the platform based on multi-core processor HyperX, high-performance low-power-consumption may be implemented
Parallel data processing, overcomes and utilizes graphics processing unit GPU to realize the higher problem of wavelet transformation power consumption in the prior art, make
It is of the invention on multi-core processor HyperX platforms the power consumption of each parallel processing element be only 25mW, reduce 5/3 small echo
The power consumption of transformation；It overcomes simultaneously and realizes that wavelet transformation development difficulty is big using on-site programmable gate array FPGA, the development cycle
It is long, the low problem of complexity so that development difficulty of the invention is low, and the development cycle is short.
Second, since the present invention passes through step (3), step (4), step (5), step (6), step (7), step (8), step
Suddenly each row of data of original image is cut into data segment by (9), is sent to each parallel on multi-core processor HyperX platforms
In processing unit, video data block is formed in each parallel processing element, 5/3 wavelet transformation is carried out to video data block, gram
It has taken and row transformation first is carried out again into row-column transform to data using on-site programmable gate array FPGA in the prior art, led to data
The problem interacted repeatedly with global memory so that the present invention improves the access speed of data, to improve overall process speed
Degree.
Third, the present invention pass through step (3), step (4), step (5), step (6), step (7), step (8), step
(9) each row of data of original image is cut into data segment, is sent to each parallel place on multi-core processor HyperX platforms
It manages in unit, video data block is formed in each parallel processing element, 5/3 wavelet transformation is carried out to video data block, is overcome
5/3 wavelet transformation is carried out to entire image using on-site programmable gate array FPGA in the prior art, causes the degree of parallelism not high
The problem of so that the present invention improves the degree of parallelism of image block and image block, to improve the processing speed of entire image.
4th, since the present invention reads initial data from Double Data Rate synchronous DRAM DDR by row, overcome
Frequent saltus step address causes initial data to read when reading initial data by block using graphics processing unit GPU in the prior art
Slow problem so that the present invention improves the reading speed of initial data.
5th, since the present invention stores the partial data of image block in parallel processing element, to extend next data
The lower edges of block overcome and realize that wavelet transformation needs to repeat transmitting extended using graphics processing unit GPU in the prior art
Lower edges data the problem of so that the invention avoids the repetition of growth data transmission, improve transmission speed.
Description of the drawings
Fig. 1 is the flow chart of the present invention；
Fig. 2 is the data sectional and growth data section left and right edges figure of the present invention；
Fig. 3 is that each growth data section of the present invention is sent to the schematic diagram of each parallel processing element；
Fig. 4 is the schematic diagram of the data block and raw image data in each parallel processing element of the present invention；
Fig. 5 is the schematic diagram of the different data block relationship of the same parallel processing element processing of the present invention.
Specific implementation mode
The present invention is described in detail below in conjunction with the accompanying drawings.
With reference to attached drawing 1, the realization step of the present invention is described in detail.
Step 1, the format of original image is converted.
The original image that a width suffix is .png formats is chosen from image set, converting the original image to suffix is
.txt the file of format.
Liang Kuai global memories A and B are distributed in Double Data Rate synchronous DRAM DDR.
Suffix is copied to global memory A for the raw image data in the file of .txt formats.
Step 2, it presses row and reads data.
In the data-reading unit of multi-core processor HyperX platforms, two array C are created, and be initialized as 0.
The data-reading unit of multi-core processor HyperX platforms, using function MPX_DDR2_Read from global memory A
It is successively read data line, it will be in read row data deposit array C.
Step 3, the data segment after left and right edges extension is sent.
Row data in array C are equally divided into M data segment, the length of each data segment is N, and calculation formula is as follows：
Wherein, W indicates that the width of original image, M indicate the sum of wavelet transformation parallel processing element.
Each data segment picture or so is respectively extended into two pixels, to being in the inductile data segment in former row data both ends,
Then centered on the pixel at edge, image copying pixel extends two pixels, and the data segment, length after extension becomes (N+4).
With reference to attached drawing 2, the data line that length is W is equally divided into M data segment, every section of length is N, by left and right
Border extended, the data segment, length after extension become (N+4).
M data segment after extension is sequentially sent to M parallel processing element successively, each data segment is sent to correspondence
A parallel processing element.It is corresponding to be divided into M data segment to be sent to the sequence of M parallel processing element per data line
, first data segment of the first row is sent to first parallel processing element, and second data segment of the first row is sent to
Two parallel processing elements, and so on, k-th of data segment of the first row is sent to k-th of parallel processing element；Second row
First data segment is sent to first parallel processing element, and second data segment of the second row is sent to second parallel processing
Unit, and so on, k-th of data segment of the second row is sent to k-th of parallel processing element.
With reference to attached drawing 3, it is sent to first parallel processing element after first data segment extension of c rows, the of c rows
It is sent to second parallel processing element after two data segment extensions；And so on, it is sent out after k-th of data segment extension of c rows
Give k-th of parallel processing element.
Step 4, for each parallel processing element, judge whether it is first time receiving data segment, if so, thening follow the steps
(5), step (6) otherwise, is executed；
Step 5, judge to receive whether line number is equal to 34, if so, thening follow the steps (7), otherwise, execute step (2).
Step 6, judge to receive whether line number is equal to 32, if so, thening follow the steps (7)；Otherwise, it thens follow the steps (2).Such as
Fruit data accepted section is the data segment in original image last column, then need not receive 32 rows, so that it may directly execute step
(7)。
Step 7, composition data block.
For each parallel processing element of multi-core processor HyperX platforms, if it is first receiving data segment,
Then sequence receives 34 data segment sections and forms a data block, if not first time receiving data segment, then receives 32 data
Mono- data block of Duan Zucheng.
An array E is created in the parallel processing element of multi-core processor HyperX platforms, and is initialized as 0, is used for
Store the last four rows edge data of data block.Array only is created when handling first data block for parallel processing element,
When handling second data block, it is no longer necessary to repeat to create array.
Step 8, lower edges are extended.
If first data block that the parallel processing element that data block is multi-core processor HyperX platforms receives, right
Claim extension top edge；If the last one data that the parallel processing element that data block is multi-core processor HyperX platforms receives
Block, then symmetric extension lower edge；First data block and last number that if data block, which is not parallel processing element, to be received
According to block, then the data in array E are added to the foremost of data block, realize the lower edges of growth data block.If extension
The line number of data block afterwards is less than 36 rows, then centered on lower edge, image copying pixel, and symmetric extension data block to 36 rows.
The data block for being sent to multiple data segments composition of the same parallel processing element corresponds to one in original image and schemes
As data block.
With reference to attached drawing 4, the image block in first parallel processing element corresponds to the data of the expressions of the X11 in original image
Block, the image block in second parallel processing element correspond to the data block of the expressions of the X12 in original image, m-th of parallel processing
Image block in unit corresponds to the data block of the expressions of the X1m in original image, and so on figure in m-th of parallel processing element
As block corresponds to the data block of the expressions of the X1m in original image.Image block in m-th of parallel processing element and the incomplete phases of X1m
Together, identical as image blocks of the X1m after border extended, the width (N+4) of image block, height are (K+4) after extension.
The same parallel processing element receives K row data segments and forms a data block every time, after the completion of data block processing,
Receive K row data segment composition data blocks again, each data segment of each row of data be sent to each parallel processing element to acting in accordance with
Sequence is the same, therefore the row range that all data blocks of same parallel processing element receiving correspond in original image is phase
With.
With reference to attached drawing 4, X11, all handled in first parallel processing element after the data block extension that X21, Xr1 are indicated,
After the data block that X11 is indicated extends in first parallel processing element, 5/3 wavelet transformation is realized, and so on, until Xr1
After the data block of expression extends in first parallel processing element, 5/3 wavelet transformation is realized.The last two rows data of X11 can
It is extended for the top edge of X21, therefore the top edge by the storage of last two rows data for next data block extends.
The last two rows data for the data block that each parallel processing element receives are extended for lower edge.
With reference to attached drawing 5, each parallel processing element has received (K+2) data segment when first time receiving data block, without
It is K row data segments, lower edge of the last multiple two row data sent for data block extends, and top edge passes through symmetric extension reality
Existing, the line number of data block is (K+4) after finally extending.(K+3) and (K+4) row data of data block after lower edges extension
Identical with next non-front two row data of data block of lower edges extension, (K+1) row and (K+2) row of data block can
Top edge for next data extends, therefore this (K+1) rows that can prestore to (K+4) row data, use by totally four row data
In 5/3 wavelet transformation of second data block, avoid repeating to transmit this four rows data.From second data BOB(beginning of block), connect every time
K row data are received, the last two rows in this K row data are used for the lower edge of data block, and the extension of top edge is then with upper one to prestore
Front two row data in four row data of a data block, the line number of data block is (K+4) after extension.
With the last four rows data update array E of data block after extension.
Step 9,5/3 wavelet transformation.
The parallel processing element of multi-core processor HyperX platforms carries out 5/3 small echo processing to the image block after extension, often
It is independently to convert that a parallel processing element carries out 5/3 wavelet transformation to image block, accesses respective memory DMR, arbitrarily
Data access between two parallel processing elements is independent of each other, therefore can to carry out 5/3 parallel small for multiple parallel processing elements
Wave conversion.
5/3 wavelet transformation of two dimension that 5/3 wavelet transformation of the present invention is realized, data block is only promoted in conversion process,
It is operated without symmetric extension.
Two row data each up and down, two column datas of each deletion in left and right of image block are deleted, size is after obtaining 5/3 wavelet transformation
N*K pixel is divided into the video data block of four subband blocks, wherein N indicates that the columns of video data block, K indicate image data
The line number of block, * indicate multiplication operations.
Step 10, receiving unit is sent data to.
By the data line of each first subband block of parallel processing element of multi-core processor HyperX platforms, it is sent to more
Receiving unit in core processor HyperX platforms.
First subband data line in the block of all parallel processing elements is sent successively.
First subband of all parallel processing elements remaining row data in the block are sent successively.
The row data of the other three subband block are sent successively.
After the data line of a subband block in each parallel processing element is sent to receiving unit, a signal is sent
To next parallel processing element, next parallel processing element could transmission data.
Step 11, enter global memory by row write.
Array F is created on multi-core processor HyperX platform receiving units.
Multi-core processor HyperX platform receiving units receive the first of first subband sent from parallel processing element
A data segment, by the data segment write-in array F of reception.
First data segment for receiving first subband that all parallel processing elements are sent successively, by the data segment of reception
Array F is written.
It will be in the data write-in global memory B in array F；
Step 12, judge whether that global memory is written in all video data blocks, if so, (13) are thened follow the steps, it is no
Then, step (2) is executed.
Step 13, by the data copy in global memory to host hard drive.
Data in global memory B are written in the file that suffix is .txt formats, by the file that suffix is .txt formats
It copies in host hard drive.
Claims (2)
1. a kind of 5/3 small wave converting method based on HyperX platforms, is realized on the platform based on multi-core processor HyperX
5/3 wavelet transformation, specific steps include as follows：
(1) format of original image is converted：
(1a) chooses the original image that a width suffix is .png formats from image set, and converting the original image to suffix is
.txt the file of format；
(1b) distributes Liang Kuai global memories A and B in Double Data Rate synchronous DRAM DDR；
Suffix is copied to for the raw image data in the file of .txt formats in global memory A by (1c)；
(2) it presses row and reads data：
(2a) creates an array C in the data-reading unit of multi-core processor HyperX platforms；
The data-reading unit of (2b) multi-core processor HyperX platforms, data line is successively read from global memory A, by institute
In the row data deposit array C of reading；
(3) data segment after left and right edges extension is sent：
Row data in array C are divided into M data segment by (3a), and the length of each data segment is N, and wherein M indicates that 5/3 small echo becomes
Change the sum of parallel processing element；
Each data segment is respectively extended two pixels by (3b) to the left and right, to being in the inductile data segment in former row data both ends,
Then centered on the pixel at edge, image copying pixel extends two pixels, and the data segment, length after extension becomes (N+4)；
Data segment after extension is sent to each parallel processing element of multi-core processor HyperX platforms by (3c) successively, each
Data segment is sent to a corresponding parallel processing element；
(4) judge whether it is to receive data block for the first time, if so, thening follow the steps (5), otherwise, execute step (6)；
(5) judge to receive whether line number is equal to 34, if so, thening follow the steps (7), otherwise, execute step (2)；
(6) judge to receive whether line number is equal to 32, if so, thening follow the steps (7), otherwise, execute step (2)；
(7) composition data block：
Each parallel processing element of (7a) multi-core processor HyperX platforms, sequence receiving data segment composition data block；
(7b) creates array E in the parallel processing element of multi-core processor HyperX platforms, for storing data block
Last four rows edge data；
(8) lower edges are extended：
(8a) is right if first data block that the parallel processing element that data block is multi-core processor HyperX platforms receives
Claim extension top edge；
(8b) if data block be multi-core processor HyperX platforms parallel processing element receive the last one data block,
Symmetric extension lower edge；
(8c) if data block be not multi-core processor HyperX platforms parallel processing element receive first data block and
Data in array E are then added to the foremost of data block by the last one data block, realize the upper following of growth data block
Edge；
(8d) uses the last four rows data update array E of data block after extension；
(9) 5/3 wavelet transformations：
The parallel processing element of (9a) multi-core processor HyperX platforms carries out 5/3 small echo processing to the image block after extension；Institute
Stating the processing of 5/3 small echo refers to, carries out two-dimentional 5/3 small echo processing to the image block after extension, promotion operation is only carried out, without right
Claim extended operation；
(9b) deletes the two row data each up and down of image block, two column datas of each deletion in left and right, and size is after obtaining 5/3 wavelet transformation
N*32 pixel is divided into the video data block of four subband blocks, wherein N indicates that the columns of video data block, * indicate the behaviour that is multiplied
Make；
(10) receiving unit is sent data to：
The data line of each first subband block of parallel processing element of multi-core processor HyperX platforms is sent to by (10a)
Receiving unit in multi-core processor HyperX platforms；
(10b) sends first subband data line in the block of all parallel processing elements successively；
(10c) sends first subband of all parallel processing elements remaining row data in the block successively；
(10d) sends the row data of the other three subband block successively；
(11) enter global memory by row write：
(11a) creates array F on multi-core processor HyperX platform receiving units；
(11b) multi-core processor HyperX platform receiving units receive the of first subband sent from parallel processing element
One data segment, by the data segment write-in array F of reception；
(11c) receives first data segment of first subband that all parallel processing elements are sent successively, by the data of reception
Section write-in array F；
(11d) will be in the data write-in global memory B in array F；
(11e) successively will be in the remainder data section write-in global memory B of first subband；
(11f) all data segments of its excess-three height band are written in global memory B successively；
(12) judge whether that global memory is written in all video data blocks, if so, thening follow the steps (13), otherwise, execute
Step (2)；
(13) by the data copy in global memory to host hard drive：
(13a) is by the data write-in suffix in global memory B in the file of .txt formats；
(13b) is by suffix in the file copy to host hard drive of .txt formats.
2. 5/3 small wave converting method according to claim 1 based on HyperX platforms, it is characterised in that：Step (3a)
Described in each data segment length be N calculation formula it is as follows：
Wherein, W indicates that the width of original image, M indicate the number of the parallel processing element used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510765015.1A CN105260983B (en) | 2015-11-11 | 2015-11-11 | 5/3 small wave converting method based on HyperX platforms |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510765015.1A CN105260983B (en) | 2015-11-11 | 2015-11-11 | 5/3 small wave converting method based on HyperX platforms |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105260983A CN105260983A (en) | 2016-01-20 |
| CN105260983B true CN105260983B (en) | 2018-07-17 |
Family
ID=55100658
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510765015.1A Active CN105260983B (en) | 2015-11-11 | 2015-11-11 | 5/3 small wave converting method based on HyperX platforms |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105260983B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108921767B (en) * | 2018-06-06 | 2023-06-13 | 国网四川省电力公司信息通信公司 | Image digital watermark processing system and processing method based on FPGA |
| CN113573072B (en) | 2021-09-22 | 2021-12-17 | 苏州浪潮智能科技有限公司 | Image processing method and device and related components |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101516031A (en) * | 2008-02-19 | 2009-08-26 | 索尼株式会社 | Image processing apparatus, image processing method, and program |
| EP2202980A1 (en) * | 2008-12-23 | 2010-06-30 | Sagem Communications SAS | Image processing method for multi-function printer |
| CN104462358A (en) * | 2014-12-05 | 2015-03-25 | 中国联合网络通信集团有限公司 | Data distribution type storage method and system |
-
2015
- 2015-11-11 CN CN201510765015.1A patent/CN105260983B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101516031A (en) * | 2008-02-19 | 2009-08-26 | 索尼株式会社 | Image processing apparatus, image processing method, and program |
| EP2202980A1 (en) * | 2008-12-23 | 2010-06-30 | Sagem Communications SAS | Image processing method for multi-function printer |
| CN104462358A (en) * | 2014-12-05 | 2015-03-25 | 中国联合网络通信集团有限公司 | Data distribution type storage method and system |
Non-Patent Citations (1)
| Title |
|---|
| 5/3提升小波变换及逆变换的FPGA设计方法;陈大科等;《东南大学学报 自然科学版》;20051130;第35卷;第211-214页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105260983A (en) | 2016-01-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8989509B2 (en) | Streaming wavelet transform | |
| US8378859B2 (en) | Memory compression technique with low latency per pixel | |
| CN101129063B (en) | Encoding device and method, decoding device and method, and transmission system | |
| BRPI0606733A2 (en) | encoding device for encoding image data, encoding method for encoding image data, decoding device for decoding encoded data where image data was encoded, decoding method for decoding encoded data where image data was encoded, and, streaming | |
| US20140086309A1 (en) | Method and device for encoding and decoding an image | |
| KR20150095825A (en) | Lossless image compression using differential transfer | |
| CN102158694B (en) | Remote-sensing image decompression method based on GPU (Graphics Processing Unit) | |
| CN105578190A (en) | Lossless compression method and system for video hard decoding | |
| CN101867809A (en) | High-speed image compression VLSI coding method based on systolic array, and encoder | |
| CN103152573A (en) | Method and system for transmitting image frame between mobile terminal and intelligent television set | |
| CN103796018B (en) | A kind of remote sensing image Real Time Compression and progressive transmission system | |
| CN105260983B (en) | 5/3 small wave converting method based on HyperX platforms | |
| CN104952088A (en) | Method for compressing and decompressing display data | |
| CN101599167B (en) | Access method of memory | |
| CN111028136B (en) | Method and equipment for processing two-dimensional complex matrix by artificial intelligence processor | |
| EP2787738B1 (en) | Tile-based compression for graphic applications | |
| GB2552136A (en) | Accessing encoded blocks of data in memory | |
| CN102123275A (en) | Video component data information acquiring and extracting method | |
| CN115221102A (en) | Method for optimizing convolution operation of system on chip and related product | |
| CN104954749B (en) | A kind of information recording method | |
| CN104902207A (en) | High speed signal collection method | |
| CN104113759A (en) | Video system and method and device for buffering and recompressing/decompressing video frames | |
| CN111052742A (en) | Image processing | |
| CN104883573B (en) | A kind of signal high-efficient treatment method | |
| CN1322414C (en) | Frame buffer storage control device and image data transmission system and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |