CN1052562A - Primary memory plate with single-bit set and reset function - Google Patents
Primary memory plate with single-bit set and reset function Download PDFInfo
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- CN1052562A CN1052562A CN90109923A CN90109923A CN1052562A CN 1052562 A CN1052562 A CN 1052562A CN 90109923 A CN90109923 A CN 90109923A CN 90109923 A CN90109923 A CN 90109923A CN 1052562 A CN1052562 A CN 1052562A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
Abstract
A kind of data processing network comprises a plurality of memory cards and a shared interface of a plurality of treatment facilities, primary memory.Each memory card comprises that memory array, one are used for temporarily depositing a data word and a logical circuit of reading from memory array.When a treatment facility when a memory card sends set or reset command, this processor is also sent a data mask.The data word of a needs modification is taken out from memory array and is latched into internal register.Logical circuit is added to data mask on the data word that has an internal register, and revises this data word, is sent to address selected in the array again.
Description
The present invention relates to a kind of information handling system that comprises the multiprocessor that links to each other with some multi-memory plates of primary memory by a shared interface, more particularly, relate to a kind of be used for revising the data that are stored in the primary memory and docking port involve very few device.
In recent years, in whole computer industry, the performance of messaging device, special aspect the quick performance of data processing operation, had considerable improvement.More and more many data handling systems adopt multiprocessing facility, and this multiprocessing facility is shared a common interface that is used for carrying out data transmission between the primary memory of all processors and common a plurality of memory card compositions.Yet, the improvement of memory sub-system aspect fails to catch up with the improvement of processor connection, especially all the more so when considering a plurality of parallel processor of employing, to such an extent as in order to yield to the structure of comparing the relative slow primary memory of its speed with processor device and having changed system or network.In order to attempt to make processor to separate mutually, cache memory and other technology have been adopted already with memory card in primary memory.
With regard to data in the primary memory are left in correction in, traditional method comprise with data from memory array take out and send deposit the processor in deposit storage, in processor, revise data bit then as requested, at last revised data are written to memory array.This operation relates to sizable system overhead.For example, must twice arbitration also use main memory interface, once be used to get data, once be used for data are deposited and get back to storer.If this interface is shared by all multiprocessors with by many memory cards of primary memory, then consume and waiting the time on this interface to be used to increase.In other words, processor that has obtained an addressable specific memory plate must waited for the anti-storage array of asking it of this plate revise can data to take out.
Worked out the technology of the data of some more efficiently corrections in storer.For example, U.S. Patent No. 4,570 222(oguchi) discloses a kind of data handling system with a kind of information debugging functions, and it comprises a dynamic random storer, an amending unit, allocation units and a controller.Amending unit receives data from RAM.And according to the input signal from these allocation units, the data to selected portion in amending unit are revised.
Relevant colour pattern demonstration aspect, U.S. Patent No. 4,016,544(Morita etcal) disclose a kind of storer and write control system, it comprises a memory buffer that is used to every separate storage red, green and blue information of a large amount of points.Each colour cell separately receives a color distribution input signal and a mask input signal from one by a processor control module.If mask bit is a logical one, then revise content; And if be logical zero, then content corresponding remains unchanged.Yet, still require the data bus that more effectively utilizes processor device and connect multiprocessing facility and primary memory.
Therefore, the objective of the invention is to provide a kind of data handling system, in this system, when the data in the primary memory are made an amendment, can significantly reduce the use of the interface between primary memory and multiprocessor.
Another object of the present invention is that some information that is included in the data modification operation is transferred on the main memory store plate from processor.
A further object of the present invention is to comprise set and the speed of these data modification functions that reset in order to improve to carry out.
Of the present invention to also have a purpose be for a kind of like this data system is provided: in this system, data selected in the memory array are carried out set and resetted, only need once promptly be enough to finish these functions to this array accesses.
In order to reach above-mentioned and other purpose, the present invention has provided a kind of data handling system, and this system comprises a kind of processing configuration equipment in order to the control bit coded data; One has the storer that is used for storing as the array of data of the bits of encoded of data word, and wherein each data word comprises a plurality of bits; And one link to each other with storer with processing configuration equipment, is used for the interface of between processing configuration equipment and storer transmission encoded data pit.Processing configuration equipment comprises that one is used for producing an order so that revise the device of a data designated word selectively.Processing configuration equipment also comprises an address date that is used for producing corresponding to have the data designated word in data array one selected storage unit position.
The improvement of this system is that a mask device is arranged in above-mentioned processing configuration equipment, is used for producing one and corresponding to the data mask of data designated and by interface this data mask is transferred in the storer.Data control unit in storer is revised the data designated word selectively according to data mask after receiving this mask and order.Data control unit comprises: an intermediate data save set; A latch means, it is according to order and address date, the word of determining appointment in array the position and the word of appointment is transferred to this intermediate data save set from selected position; One is used for receiving data mask and this mask is added to this data designated word when this word is included in this intermediate data save set, so that revise the device of these data selectively; And a write device, be used for after the word modification finishes, the data designated word being delivered in the array.
Above-mentioned processing configuration equipment preferably includes a plurality of treatment facilities, and each treatment facility is suitable for the control bit coded data and produces order.Storer can comprise a plurality of memory cards, and each plate has the data array that is used for storing encoded data pit.Interface preferably includes the data bus of a transmission data mask and the command line of transmission command and address information.Data bus and command line are parallel work-flows, and each is all shared by all treatment facilities and all memory cards.Each memory card all has its oneself interior RS array.Interior register cooperation provides the intermediate data save set.
Each memory card also can comprise with its in the corresponding logical circuit of register, the data word that will revise according to a set order together with data mask as input signal deliver to one " or " logic gate, and the input signal of this OR-gate is sent back in the data array of plate.According to reset command, with the mask paraphase, then mask after the paraphase and data word are delivered to together the input end of AND gate, the output signal of AND gate then is sent back in the data array.
Data word preferably has identical predetermined number of bits with data mask, thereby in each data word and revising between the mask that adopts in the data one-to-one relationship is arranged, so as can enough quite simple and direct circuit in single reading/revises/write cycle time realization data modification fast.
Interior register has been arranged on memory card and revised logical circuit, on memory card, realized set and reset operation, never can cause on the meaning of any interruption to say it is automatic owing to the order of other plate that adds to storage.Carrying out most of these operations in primary memory has liberated each processor made other task of execution in its similar All Time that can use on by set and reset operation institute.Because each operates required periodicity and interface between processor and primary memory or the occupied time decreased of bus, therefore improved the handling capacity of system.At last, in case the initial modification of memory card, the traffic of interface, array initialization expense or asynchronous memory refresh operation can't interfere it to continue to finish set and reset function.
For further understanding above-mentioned and other purpose and advantage, most preferred embodiment and accompanying drawing are made a presentation below us.
Fig. 1 is the synoptic diagram of an information handling system, and the configuration of a multiprocessing facility links to each other with the primary memory that comprises a plurality of memory cards by a shared interface among the figure;
Fig. 2 is the synoptic diagram of one of them memory card of an explanation data modification logic;
Fig. 3 is the timing diagram of a traditional data modification operation;
Fig. 4 is the timing diagram of a similar Fig. 3, and data modification operation of the present invention is described;
Fig. 5 has represented one 8 bit data word, and set function is described;
Fig. 6 is similar to Fig. 5, in order to the explanation reset function.
Above-mentioned each figure is described in detail in detail now again, figure 1 illustrates an information handling system 16 that is used for storing encoded data pit and these data is carried out institute's selection operation.This system comprises two processor devices that identify with numeral 18 and 20 respectively.An arbitration link 22 couples together two processors, and this arbitration link combines allocation priority to one of them processor with arbitraling logic circuit in two treatment facilities.Should be realized that the configuration of the treatment facility in this network can be made of a single treatment facility, perhaps constitute, (corresponding be equipped with a plurality of arbitration links each treatment facility is interconnected one by one) by a plurality of treatment facilities.
An interface is connected treatment facility with primary memory, primary memory comprises a plurality of as the memory cards with 24,26 and 28 expressions.Memory card 24 for example comprises that the memory array 30 that is used to store encoded data pit and one are used for receiving data and interim store data so that be transferred to a wherein selected treatment facility impact damper 32 from interface.Memory card 24 also comprises an interior register 34 that links to each other with memory array 30.The data that are stored in memory array are loaded into the interior register 34 that is used as temporary transient intermediate storage, during this period, and can be according to modifying of order data from one of them treatment facility.
Memory card 26 is similar to memory card 24 with 28, they comprise memory array 36 respectively, an impact damper 38, an interior register 40, with 44, one impact dampers 46 of 42, one interior registers of memory array, it is the same that these parts and the corresponding component of memory card 24 come down to, and its function is also identical.
Comprise a data bus 48 and a command/address bus 50 with the interface that processor links to each other with memory card, link to each other with memory card with all processors respectively, with other bus parallel independent transmission data.Data bus 48 is transmitted as the information that conveniently is referred to as job information, that is the information that is most interested in of transmission system user.Command/address bus 50 transmission is relevant take out or deposit in the particular job data order control information and transmit the address information that is used for retrieving the storage unit position of the particular job data in memory array or is used for retrieving the storage unit position that these data will be sent to.
Each processor has an order wire 52 in order to will order and address information is transferred to bus 50 and by order wire 54 wherein this information is sent to suitable memory card from bus 50 again.Command transfer is unidirectional (from processor to a memory card), and the arrow at order wire 52 two represents that can notify remaining processor: command/address bus is occupied when order of whichever device transmission.
Data line 56 between processor and bus 48 and the data line between memory card and data bus 58 provide the transmission of the operational data on both direction.Interface also comprises do not show the bright data channel that control data bus 48 uses that is used in Fig. 1, also can comprise a common share communication bus that is used for transmitting the status information of relevant operational data.For further specifying this interface, can consult United States Patent (USP) in-application the assignee who transfers the application the US Patent No that is entitled as " High performance Shared Main Storage Interface "-.
Is useful especially at the interior register in memory card 24,26 and 26 aspect modification is stored in data in the memory array separately, because need like this data transmission to processing equipment.Be used for revising being illustrated among Fig. 2 of circuit signal of data, it is used to revise a selected data bit.What will know here is that the data in system 16 are to transmit with the form of corresponding 8 word bytes of the capacity of data bus 48 and to revise.So to any selected data word, complete modification circuit will be included as the multiplex electronics that each remaining data bit of this word is provided with in memory card, and all bits are handled side by side.
In the drawings, processor 18 provides one to be used in a data mask revising its a little data in the memory array 30 that is stored in memory card 24.One of array latchs output (as at 59 places) and is used as to an input of AND gate 60 and is used as an input information giving OR-gate 62.Another input signal of OR-gate is the output of impact damper 32.Impact damper output also is added to phase inverter 64, and the signal after anti-phase is used as another input signal of AND gate 60.The output signal of AND gate and OR-gate is delivered to multiplexer 66, and memory array 30 is returned in its output after 65 places latch.
So, each memory card comprises and is used for taking out data and it being encased in interior register from data array, be used for receiving data mask and be modified in the interior data of interior register, and be used for sending amended data back to this data array a kind of like this circuit with this data mask.The outstanding advantage of this method is that the circuit major part that is used for set and reset operation is at memory card rather than in processor, thereby the required clock periodicity for carrying out these operations is significantly reduced.
Compare with the method for prior art correction numeral, the superiority of set of the present invention or the method that resets is conspicuous.Fig. 3 shows the timing diagram of the processor control modification of the data that adopt conventional method.One comprised corresponding to the retrieval command of the address information of the storage unit of the requested data in primary memory, sent to memory card by command/address bus from processor when first clock period.
Selecteed memory card begins to visit its memory array in the second clock cycle.Specifically, by two control lines, promptly row address strobe (RAS) and column address strobe (CAS) conduct interviews to array.Row address strobe (RAS) is owing to become the visit of effective starting to the data array when the beginning in second clock cycle, column address strobe then becomes when the 3rd clock period began effectively.With regard to Fig. 3 and 4, be noted that the row and column address strobe is to be in high level when effective so that with other line, promptly processor command/data line and array data line are consistent.This only be convenient to the explanation.In fact, the row and column address strobe is " bearing effect ", promptly becomes when high logic level is transformed into low logic level effectively when this signal.
When the period 4, the data of array are read into storage buffer.When the 5th clock period, data are sent to processor by data bus, and becoming that the rank addresses gating is attached is invalid.Processor correction data when the 6th clock period.
Processor sends memory command when the 7th clock period, and then in following one-period amended data is sent back to memory card, and row address strobe is effective again simultaneously.Column address strobe is effective when the 9th cycle, and turns back to array in the data that 10-12 revised in the cycle, and attached, it is invalid that the rank addresses gating becomes once more.With mean a kind of modify steps at the array data in the 11st cycle relevant " M ", this modify steps is not for set or resets, but data are arranged as the line that is more suitable in storing from the form that is suitable for transmitting array.
The timer of Fig. 4 is similar to Fig. 3's, and it is used for the data modification that mainly carries out on memory card is described, promptly according to the order of from processor 18 data on the selected address in the storer 30 of memory card 24 is made amendment.All data bits are revised as all parts of 8 word bytes.But, only show the data word that 8 bits are only arranged with regard to a set operation and a reset operation respectively at Fig. 5 and Fig. 6 for ease of explanation.
As shown in Figure 4, processor 18 is sent to memory card 24 by command/address bus 50 with order.This order promptly can be used to " set " or is used for " resetting " be shown in data word 70 in Fig. 5 and 6.No matter whether this order is set or reset command, treatment facility provides a data mask 72 by data bus 48 to memory card.Row address strobe becomes effectively in this cycle.
Fig. 5 shows 8 identical bit-masks 72 with Fig. 6, and is logical one at the 3rd and the 7th bit, and remaining bit is a logical zero.Therefore, for a set order, data word 70 will be changed to logical one at the 3rd and the 7th bit.
For a reset command, these bits will be reset to a logical zero.In both cases, each bit of other in data word remains unchanged.
Now consult Fig. 4 again.Column address strobe becomes effectively when the period 3 begins, and data were read from memory array 30 when the period 4.Yet opposite with Fig. 3, data are not read into impact damper 32, but are latched in the interior register 34 of memory card.
If order is reset command when second round, then mask 72 is transformed to form an anti-phase mask 76.This anti-phase mask and this data word be attached be added to such as door 60 such 8 with door.Be revised (in this reset case) data word 78 with the output of door, wherein the 3rd and 7 bits are reset, and promptly the 3rd bit in data word 70 becomes logical zero, and the 7th bit remains logical zero.It is the same that other bit keeps.
Retouching operation was finished in the 6th cycle, during amended word from interior register 34 write store arrays 34, specifically turn back to selected address 68.
Like this, the present invention has increased greatly to the set of the data in memory array and the speed of reset operation, with the clock periodicity that requires cut down near half.Yet the increase of efficient is also much higher than the result who draws in the above-mentioned comparison, and this is the time that does not need the contention interface because of the processor of our hypothesis under every kind of situation in the above-mentioned example.In fact, in the configuration of any multiprocessor of sharing shared interface, related processor must with primary memory contention interface.Traditional data modification program (Fig. 3) requires processor to obtain the use of docking port for twice, once is used for fetching data from memory card, once is used for amended data are turned back to memory card.But 18 of processors only require and use interface once, in order to set or reset command and data mask are delivered to memory card 24.
This has just brought another advantage, that is to say, the occupancy of set of the present invention and reset operation docking port has been economized half, specifically, provide set or reset command with the one-period time, the one-period time provides data mask, reaches four cycles and traditional sequence requirement takies interface.
Also have the another one advantage to be for such fact: memory array is normally inactive, and it requires to have a predetermined clock periodicity to charge or be ready.This predetermined periodicity nature is with the character of array and the length in cycle and different, always but increased any required time of operation that relates to accessed array.Traditional data modification sequence requires to deliver to processor for sense data reference-to storage array and with data earlier, then, be expert at, column address strobe become invalid after, carry out the operation that writes amended data again.In contrast, then be with single the reading that account for three continuous clock cycles/revise/write in sequence to the modification of the designation number in memory card 24, therebetween once more control store to become existing row address strobe with state effective.
Compare with traditional sequence, a last advantage of the present invention is: refresh such asynchronous event such as storage and do not interfere data modification operation in the memory card in network 16.This type of incident can be prolonged and sent traditional data modification order, and is special, if they are when occurring between clock period of retrieval command and memory command.So, in Information Processing Network of the present invention,, thereby significantly reduced the use of required docking port of time and set and reset operation because the memory card of primary memory is to carry out set and reset operation according to order and mask from treatment facility.
Claims (15)
1, data disposal system, it comprises a treatment facility configuration that is used for the control bit coded data, one has the storer that is used to store as the array of data of the bits of encoded of a plurality of data words, wherein each data word comprises a plurality of bits, and comprises an interface that link to each other with processor configuration and storer, be used for transmitting the data of bits of encoded between treatment facility configuration and storer; Wherein treatment facility configuration comprises and a kind ofly is used for producing an order and selects to revise in all data words an assignable data word and produce the device of address according to deposit this specific data word in data array one selected position to have; This data handling system is characterised in that and comprises:
Mask generation device in treatment facility, it produces a data mask according to the data designated word, and by interface mask is transferred to storer; And
Data control unit in storer is used for revising specified data word selectively according to this mask after receiving mask and order, and described data control unit comprises:
An intermediate data save set;
A latch means, it determines that according to described order and address date the word of appointment is sent to the intermediate data save set in the storage unit position of array and with this designated word from selected storage unit;
A kind ofly be used to receive mask and when above-mentioned word is included in the intermediate data save set, mask is added to the data designated word, to revise the device of data word selectively; And
A kind of write device that is used for after this word is corrected, the data designated word being sent to array.
2, the data handling system of claim 1 is characterized in that each described data word has identical predetermined number of bits.
3, the system of claim 2 is characterized in that:
Described write device sends back to described selected storage unit revising the back data word.
4, the system of claim 3 is characterized in that:
Described processing configuration comprises a plurality of treatment facilities, each treatment facility comprises the device that is used for the control bit coded data and is used to produce order, and wherein said storer comprises a plurality of memory cards, and each plate is useful on the array of stored bits coded data.
5, system as claimed in claim 4 is characterized in that:
Described interface comprises that one is used for transmitting the data bus of mask and comprises a command line that is used for transmission command and address information, and described data bus and command line are shared by all treatment facilities and all memory cards.
6, the system of claim 5 is characterized in that:
Each memory card has an interior register, by described in each register form the intermediate data save set together.
7, the system of claim 2 is characterized in that:
Each mask has predetermined bit number.
8, the system of claim 7 is characterized in that:
Each described order be two kinds available and the order in a kind of order, these two kinds of alternative orders are set order and reset command.
9, the system of claim 8 is characterized in that:
Described storer comprises a plurality of memory cards, and each memory card itself has several described data arrays that are used for the stored bits coded data and has an interior register, described in each set of registers formed the intermediate data save set; And:
Wherein each described plate also comprises the logical circuit that links to each other with register in it, be used for the data word that will make an amendment and mask is delivered to as input signal or the gate logic door to carry out described set order, or be used for anti-phase mask, the data that revise and anti-phase mask are delivered to and logic gate as input signal.
10, comprise a processor configuration that is used for the control bit coded data at one, one comprises a storer that is used to store the host memory device of the encoded data pit (each data word has a plurality of bits) as a plurality of data words, and one that link to each other with processor configuration and storer, be used in the data handling system of between them interface of transmitted bit coded data a kind of being used for and revise the method that is stored in the data in the host memory device selectively, it is characterized in that the following step:
Utilize the configuration of above-mentioned processor to produce a modification order that is used for revising the data of bits of encoded, one corresponding to the address information that is stored in a selected storage unit position in the host memory device so that certain data word of being stored in the selected storage unit is appointed as the data word that will revise, and the data mask of at least one bit of sign in the data designated word that will revise;
Revising order, address information and data mask are sent in the storer by interface;
According to described order and address information, determine selected data word position, the word of appointment is sent to an intermediate data save set storer from host memory device, and
Data mask is added to the data designated word that is included in the save set, revises specified data word selectively with content according to data mask.
11, the method for claim 10, its feature also is the following step:
Amended data word is sent back to host memory device.
12, the method for claim 11 is characterized in that:
Described the data designated word is sent in the middle of save set, the step that mask is added to the data designated word and the word of amended appointment is added to primary memory is all finished in single reading/revise/write cycle time.
13, the method for claim 11 is characterized in that:
The described step that amended specific data word is sent to primary memory comprises amended data designated word is sent to selected ground storage unit.
14, the method for claim 11 is characterized in that:
Described order has the two class orders that comprise set order and reset command, and
When order is a set order, the described step that mask is added to the data designated word comprise to or logic gate step as the designated word and the mask of input signal is provided.
15, the method for claim 14 is characterized in that:
When order was a reset command, the described step that adds mask also comprised the paraphase mask so that an anti-phase mask is provided and provides the step of this anti-phase mask and data designated to one with logic gate.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/450,182 US5167029A (en) | 1989-12-13 | 1989-12-13 | Data processing system and associated process using memory cards having data modify functions utilizing a data mask and an internal register |
| US450,182 | 1989-12-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1052562A true CN1052562A (en) | 1991-06-26 |
| CN1017837B CN1017837B (en) | 1992-08-12 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN90109923A Expired CN1017837B (en) | 1989-12-13 | 1990-12-11 | Main storage memory cards having single bit set and reset functions |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US5167029A (en) |
| EP (1) | EP0437160B1 (en) |
| JP (1) | JPH03189843A (en) |
| KR (1) | KR940002903B1 (en) |
| CN (1) | CN1017837B (en) |
| AU (1) | AU636680B2 (en) |
| BR (1) | BR9006026A (en) |
| CA (1) | CA2026741C (en) |
| DE (1) | DE69033416T2 (en) |
| ES (1) | ES2140376T3 (en) |
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| CN102103673A (en) * | 2009-12-16 | 2011-06-22 | 英特尔公司 | Providing integrity verification and attestation in a hidden execution environment |
| CN114579189A (en) * | 2022-05-05 | 2022-06-03 | 深圳云豹智能有限公司 | Single-core and multi-core register data access method, processor and system |
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| IT1247640B (en) * | 1990-04-26 | 1994-12-28 | St Microelectronics Srl | BOOLEAN OPERATIONS BETWEEN TWO ANY BITS OF TWO ANY REGISTERS |
| US5434970A (en) * | 1991-02-14 | 1995-07-18 | Cray Research, Inc. | System for distributed multiprocessor communication |
| AU7049694A (en) * | 1993-06-14 | 1995-01-03 | Rambus Inc. | Method and apparatus for writing to memory components |
| AU677673B2 (en) * | 1993-10-12 | 1997-05-01 | Samsung Electronics Co., Ltd. | Method and apparatus for executing an atomic read-modify-write instruction |
| US5499376A (en) * | 1993-12-06 | 1996-03-12 | Cpu Technology, Inc. | High speed mask and logical combination operations for parallel processor units |
| US5692154A (en) * | 1993-12-20 | 1997-11-25 | Compaq Computer Corporation | Circuit for masking a dirty status indication provided by a cache dirty memory under certain conditions so that a cache memory controller properly controls a cache tag memory |
| US6532180B2 (en) | 2001-06-20 | 2003-03-11 | Micron Technology, Inc. | Write data masking for higher speed DRAMs |
| US7016999B1 (en) * | 2002-02-05 | 2006-03-21 | Adaptec, Inc. | Hardware circuit and method for automatically configuring on-the-fly a sub-unit in a SCSI message |
| US6671212B2 (en) * | 2002-02-08 | 2003-12-30 | Ati Technologies Inc. | Method and apparatus for data inversion in memory device |
| US8850137B2 (en) * | 2010-10-11 | 2014-09-30 | Cisco Technology, Inc. | Memory subsystem for counter-based and other applications |
| US11537319B2 (en) * | 2019-12-11 | 2022-12-27 | Advanced Micro Devices, Inc. | Content addressable memory with sub-field minimum and maximum clamping |
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| JPS5671154A (en) * | 1979-11-15 | 1981-06-13 | Nec Corp | Information processing device |
| US4363093A (en) * | 1980-03-10 | 1982-12-07 | International Business Machines Corporation | Processor intercommunication system |
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| US4520439A (en) * | 1981-01-05 | 1985-05-28 | Sperry Corporation | Variable field partial write data merge |
| JPS5960658A (en) * | 1982-09-30 | 1984-04-06 | Fujitsu Ltd | Semiconductor storage device provided with logical function |
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1989
- 1989-12-13 US US07/450,182 patent/US5167029A/en not_active Expired - Fee Related
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1990
- 1990-10-02 CA CA002026741A patent/CA2026741C/en not_active Expired - Fee Related
- 1990-10-31 ES ES90480174T patent/ES2140376T3/en not_active Expired - Lifetime
- 1990-10-31 EP EP90480174A patent/EP0437160B1/en not_active Expired - Lifetime
- 1990-10-31 DE DE69033416T patent/DE69033416T2/en not_active Expired - Fee Related
- 1990-11-07 JP JP2299989A patent/JPH03189843A/en active Pending
- 1990-11-13 AU AU66553/90A patent/AU636680B2/en not_active Ceased
- 1990-11-28 BR BR909006026A patent/BR9006026A/en not_active Application Discontinuation
- 1990-12-07 KR KR9020065A patent/KR940002903B1/en not_active IP Right Cessation
- 1990-12-11 CN CN90109923A patent/CN1017837B/en not_active Expired
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102103673A (en) * | 2009-12-16 | 2011-06-22 | 英特尔公司 | Providing integrity verification and attestation in a hidden execution environment |
| CN114579189A (en) * | 2022-05-05 | 2022-06-03 | 深圳云豹智能有限公司 | Single-core and multi-core register data access method, processor and system |
| CN114579189B (en) * | 2022-05-05 | 2022-09-09 | 深圳云豹智能有限公司 | Single-core and multi-core register data access method, processor and system |
Also Published As
| Publication number | Publication date |
|---|---|
| AU636680B2 (en) | 1993-05-06 |
| CN1017837B (en) | 1992-08-12 |
| AU6655390A (en) | 1991-06-20 |
| US5167029A (en) | 1992-11-24 |
| CA2026741C (en) | 1994-02-01 |
| DE69033416D1 (en) | 2000-02-10 |
| JPH03189843A (en) | 1991-08-19 |
| CA2026741A1 (en) | 1991-06-14 |
| KR910012955A (en) | 1991-08-08 |
| ES2140376T3 (en) | 2000-03-01 |
| EP0437160A3 (en) | 1993-01-13 |
| DE69033416T2 (en) | 2000-07-06 |
| KR940002903B1 (en) | 1994-04-07 |
| EP0437160A2 (en) | 1991-07-17 |
| BR9006026A (en) | 1991-09-24 |
| EP0437160B1 (en) | 2000-01-05 |
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