CN105239156A - Method for preparing plane semiconductor nanowire through epitaxial orientated growth, transfer and integration - Google Patents
Method for preparing plane semiconductor nanowire through epitaxial orientated growth, transfer and integration Download PDFInfo
- Publication number
- CN105239156A CN105239156A CN201510586924.9A CN201510586924A CN105239156A CN 105239156 A CN105239156 A CN 105239156A CN 201510586924 A CN201510586924 A CN 201510586924A CN 105239156 A CN105239156 A CN 105239156A
- Authority
- CN
- China
- Prior art keywords
- growth
- grow
- epitaxial
- substrate
- nano wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
A method for preparing a plane semiconductor nanowire through epitaxial orientated growth, transfer and integration comprises the following steps: 1) processing a crystal substrate to remove a surface oxidized layer; 2) performing vapor plating on In and Sn to induce a metal film and further to grow a metal film pattern, wherein the film thickness is several nanometers to tens of nanometers; 3) processing the metal film at a temperature of 200 DEG C-500 DEG C at a power of 2 W-50 W in a PECVD (Plasma Enhanced Chemical Vapor Deposition) system by utilizing a plasma processing technology, so as to enable the metal film to form a quasi nanometer metal catalytic particle with the diameter of ten of nanometers to several micrometers; 4) continuing to cover and grow a layer of an amorphous-silicon layer with the thickness of several nanometers to hundreds of nanometers in the PECVD system as a precursor medium layer; and 5) performing annealing on the amorphous-silicon layer in vacuum or at non-oxidative atmosphere, and utilizing an IP-SLS growth mode to grow and obtain an epitaxial silicon or germanium nanowire on the amorphous-silicon layer. A key technology is provided for field effect transistors, sensors and photoelectric devices based on the plane semiconductor nanowire.
Description
One, technical field
The present invention relates to photoelectric material and devices field, particularly about direct growth high quality single crystal epitaxial semiconductor nanowires over the crystalline substrate method and obtain nano thread structure.
Two, background technology
The semiconducter device such as current social microelectronics and opto-electronic device have been widely used in the every aspect in modern science and technology, national economy and daily life, and the epitaxy technology of these Semiconductor Devices and Materials various in style is closely related.
Semiconductor nano line structure, due to the optics of its uniqueness and electrical properties, has boundless application prospect in electron device, photodetection, biomedicine, sensor.At present, semiconductor nanowires is mainly prepared by VLS method, and the nano wire that this method is prepared is vertical, needs first it to be transferred in planar substrate.Therefore, the technique preparing high-quality planar epitaxial semiconductor nanowires in crystalline substrates has the using value of reality and wide application prospect.
The general requirement of VLS growth mechanism must have the existence of catalyzer, first growth material is evaporated into gaseous state, at suitable temperature, catalyzer can form liquid eutectic with the constituent element of growth material is molten mutually, the constituent element of growth material constantly obtains from gas phase, after matter constituent element molten in liquid state reaches supersaturation, whisker will be separated out along solid-liquid interface one preferential direction, grow up to linear crystal.The size of catalyzer will control the size of grown whisker to a great extent obviously.Experiment proves that this growth mechanism can be used for preparing the even more complicated monocrystalline of a large amount of simple substance, binary compound, and the essentially no dislocation of monocrystalline of the method growth, fast growth.A large amount of quasi-one-dimensional nanometer materials can be prepared by the size controlling catalyzer.
The mechanism that liquid-liquid phase-solid phase (SLS) growth mechanism SLS grows is similar to a little VLS mechanism, is only with the difference of VLS mechanism, and in VLS mechanism process of growth, required starting material are provided by gas phase; And in SLS mechanism process of growth, required raw material provides from solution, in general, in this method, conventional low melting point metal (as In, Sn or Bi etc.) is as solubility promoter (fluxdroplet), is equivalent to the catalyzer in VLS mechanism.Buhro group of Washington, DC university obtains the semiconductor nanowires of high-crystallinity at low temperatures by SLS mechanism, as InP, InAs, GaAs nano wire, the nano wire of this method growth is polycrystalline or nearly single crystal structure, and the size distribution ranges of nano wire is wider.
Three, summary of the invention
For the problems referred to above, the object of the invention is, a kind of method preparing high quality flat surface semiconductor nano wire is provided.Especially extension oriented growth, transfer and integrated approach prepare planar semiconductor nano wire.
The present invention takes following technical scheme: the method for extension oriented growth, transfer and integrated planar semiconductor nanowires, its step is as follows: 1) to crystalline substrates (as silicon substrate, sapphire etc. and institute grow nanowire lattice the crystalline substrates of mating) carry out processing early stage, remove surface oxide layer; As with HF solution to substrate processing, expose the plane of crystal of silicon substrate; 2) the inducing metal film such as evaporation In, Sn, induction In, Sn metal (as the mode evaporation with mask plate goes out) grows metal film pattern, thickness of metal film in several nanometer to tens nanometers; 3) utilize plasma treatment technique in a pecvd system, process when temperature 200 DEG C-500 DEG C, power 2W-50W, metallic membrane is shunk becomes the accurate catalyzing nano-particles of diameter between tens nanometers are to several microns; 4) amorphous silicon layer of covering growth one deck suitable thickness (a few nanometer is to hundreds of nanometer) in a pecvd system, is continued as presoma medium layer; 5), amorphous silicon layer anneals (temperature is more than 280-500 DEG C) in a vacuum or in the non-oxidizing atmosphere such as hydrogen, nitrogen, utilizes IP-SLS growth pattern to obtain epitaxial silicon or Ge nanoline in amorphous silicon layer growth.
Further, utilize the transfer techniques such as anode linkage that the epitaxial silicon of growth or Ge nanoline are transferred in other target substrate.
Further, the present invention program can regulate and control the growth of epitaxial silicon or Ge nanoline by parameters such as the temperature condition of plasma treatment time power and temperature in adjustment process of growth, covering non-crystalline silicon thickness and growth, annealing temperature and times, obtain diameter, length, epitaxial silicon nanowire that the direction of growth is adjustable.
Further, inducing metal both can be In, Bi or Sn, also can be that other can the metal of induced growth plane nano line.
Further, epitaxially grown nano wire both can be silicon nanowires, also can be with presoma be the Ge nanoline of amorphous germanium growth and other can the semiconductor nanowires of induced growth, nano wire both can be intrinsic nano wire also can be the doped nanowire grown by controlled doping presoma.Such as, be add PH3 at covering non-crystalline silicon, form N-type non-crystalline silicon presoma, thus grow the silicon nanowires of N-type doping.
The pattern of inducing metal both can use mask plate, also can utilize photoetching technique, nanometer embossing obtains.
The growth of nanometer both can be the lattice epitaxy along certain lattice direction, also can be the Self-aligned growth of the figure formed after the cutting of certain particular crystal orientation.
The substrate of growing epitaxial nano wire both can be planar substrate, also can be that planar substrate is along the graph substrate after the cutting of certain crystal orientation.
The transfer techniques of nano wire both can be anode linkage technology, also can be the transfer techniques of other nano wires.
Beneficial effect of the present invention, the present invention adopts IP-SLS method growing epitaxial semiconductor nanowires in a pecvd system.IP-SLS method can growth plane nano wire, just can grow high-quality planar epitaxial crystal semiconductor nanowire line in conjunction with epitaxy technology.Epitaxial semiconductor nanowires is the special crystal orientation growth along crystalline substrates, so just can grow self-orientating silicon nanowires.Self-align, self-orientating planar epitaxial silicon nanowires just can be obtained in conjunction with behind the position of photoetching technique locating catalytic particles.Because the epitaxial interface of this type of nano wire and substrate can effectively regulate, this type of epitaxial planar nano wire can carry out peeling off and transferring on other flexible substrate further.Because its direction of growth postpones the peculiar crystal orientation of crystal, electricity device can be carried out easily and to connect and integrated.The technology is provide gordian technique basis based on the high performance field effect transistors of planar semiconductor nano wire, sensor and photoelectric device.Wide prospect is had in the application aspect of high performance field effect transistors, sensor and photoelectric device.
Four, accompanying drawing explanation
Fig. 1: planar epitaxial silicon plane nano line process of growth schema.
Planar epitaxial silicon nanowires SEM shape appearance figure on Fig. 2: Si (100) substrate;
Fig. 3: planar epitaxial silicon nanowires SEM shape appearance figure in Sapphire Substrate.
Five, embodiment
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, the present invention is described in more detail.Schema as shown in Figure 1.A technology for extension oriented growth, transfer and integrated planar semiconductor nanowires,
On embodiment 1, Si (100) substrate, extension oriented growth planar silicon nano wire comprises the following steps:
1) adopt Si (100) substrate, with HF solution to substrate processing, the surface oxide layer of removing substrate, exposes the plane of crystal of silicon substrate.
2) utilize shadowmask for the inducing metal patterns such as mask plate evaporation In or Sn (thickness in several nanometer to tens nanometers).The pattern of inducing metal both can use mask plate, also can utilize existing photoetching technique, nanometer embossing obtains.
3) catalyzing nano-particles of diameter between tens nanometers to several micron is formed in a pecvd system, utilize the temperature of plasma treatment technique 100 DEG C-400 DEG C under 1-50W power under.
4) amorphous silicon layer of covering one deck suitable thickness is in a pecvd system continued as presoma medium layer; The amorphous silicon layer of one deck suitable thickness is covered at 100 DEG C-400 DEG C.
5) (temperature is at 280-500 DEG C) is annealed in a vacuum or in the non-oxidizing atmosphere such as hydrogen, nitrogen, at 280 DEG C-500 DEG C, the non-crystalline silicon of surrounding can be absorbed after catalysis drop is activated, thus can induced growth out-of-plane silicon nanowires, under substrate lattice effect, nano wire, along substrate special crystal orientation growth, forms epitaxially grown planar silicon nano wire.
6) utilize the transfer techniques such as anode linkage that the epitaxial nanowires of growth is transferred in other target substrate.
In embodiment 2, Sapphire Substrate, extension oriented growth planar silicon nano wire comprises the following steps:
1) adopt sapphire R (11-20) substrate, use acetone, Virahol, alcohol, deionized water solution to substrate processing respectively, the surface attachments of removing substrate.
2) utilize shadowmask for the inducing metal patterns such as mask plate evaporation In, Sn or ITO (thickness in several nanometer to tens nanometers).The pattern of inducing metal both can use mask plate, also can utilize existing photoetching technique, nanometer embossing obtains.
3) in a pecvd system, at 1-50W power, the temperature of 200 DEG C-400 DEG C, plasma treatment technique is utilized to make it to form the catalyzing nano-particles of diameter between tens nanometers to several micron;
4) amorphous silicon layer of covering one deck suitable thickness is in a pecvd system continued as presoma medium layer; The amorphous silicon layer of one deck suitable thickness is covered at 2 DEG C-400 DEG C.
5) (temperature is at 280-600 DEG C) is annealed in a vacuum or in the non-oxidizing atmosphere such as hydrogen, nitrogen, at 280 DEG C-600 DEG C, the non-crystalline silicon of surrounding can be absorbed after catalysis drop is activated, thus can induced growth out-of-plane silicon nanowires, under substrate lattice effect, nano wire, along substrate special crystal orientation growth, forms epitaxially grown planar silicon nano wire.
6) utilize the transfer techniques such as anode linkage that the epitaxial nanowires of growth is transferred in other target substrate.
The adjusting and controlling growth of extension cord refers to that the parameters such as the temperature of covering non-crystalline silicon and thickness, annealing temperature and time realize by adjustment H2 Cement Composite Treated by Plasma power, time.Such as, the diameter of the catalyticing metal particle that can be obtained by adjustment H2 gas ions processing power, time controling, thus the control to nanowire diameter can be realized.
Inducing metal both can be In, Bi or Sn, also can be that other can the metal of induced growth plane nano line.
Epitaxially grown nano wire both can be silicon nanowires, also can be Ge nanoline and other can the semiconductor nanowires of induced growth, nano wire both can be intrinsic nano wire also can be doped nanowire.
The growth of nanometer both can be the lattice epitaxy along certain lattice direction, also can be the Self-aligned growth of the figure formed after the cutting of certain particular crystal orientation.The substrate of growing epitaxial nano wire both can be Si substrate, the crystalline substrates that also can be sapphire etc. mate with institute grow nanowire lattice.
The transfer techniques of nano wire both can be anode linkage technology, also can be the transfer techniques of other nano wires.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. the method for extension oriented growth, transfer and integrated planar semiconductor nanowires, is characterized in that step is as follows: 1) to crystalline substrates process, remove surface oxide layer; 2) evaporation In, Sn inducing metal film, grows metal film pattern, thickness of metal film in several nanometer to tens nanometers; 3) utilize plasma treatment technique in a pecvd system, process when temperature 200 DEG C-500 DEG C, power 2W-50W, metallic membrane is shunk becomes the accurate nano metal catalysed particulate of diameter between tens nanometers are to several microns; 4) continue to cover the amorphous silicon layer of a few nanometer of growth one deck to hundreds of nanometer in a pecvd system as presoma medium layer; 5) amorphous silicon layer is annealed in a vacuum or in the non-oxidizing atmosphere such as hydrogen, nitrogen, temperature is at 280-500
oc, utilizes IP-SLS growth pattern to obtain epitaxial silicon or Ge nanoline in amorphous silicon layer growth.
2. the method for grow nanowire according to claim 1, is characterized in that: utilize anode linkage transfer techniques that the epitaxial nanowires of growth is transferred in other target substrate.
3. the method for grow nanowire according to claim 1, it is characterized in that: the growth being regulated and controled epitaxial silicon nanowire by parameters such as the temperature condition of plasma treatment time power and temperature in adjustment process of growth, covering non-crystalline silicon thickness and growth, annealing temperature and times, obtain diameter, length, epitaxial silicon nanowire that the direction of growth is adjustable.
4. the method for grow nanowire according to claim 1, is characterized in that: inducing metal is In, Bi or Sn, or other can the metal of induced growth plane nano line.
5. the method for grow nanowire according to claim 1, is characterized in that: epitaxially grown nano wire be silicon nanowires or Ge nanoline and other can the semiconductor nanowires of induced growth, nano wire is intrinsic nano wire or doped nanowire.
6. the method for grow nanowire according to claim 1, is characterized in that: the pattern of inducing metal both used mask plate, or utilize photoetching technique, nanometer embossing obtains.
7. the method for grow nanowire according to claim 1, is characterized in that: the growth of nanometer along the lattice epitaxy of certain lattice direction, or can grow along the rear Self-aligned formed of certain particular crystal orientation cutting.
8. the method for grow nanowire according to claim 1, is characterized in that: the substrate of growing epitaxial nano wire both can be Si substrate, the crystalline substrates that also can be sapphire etc. mate with institute grow nanowire lattice.
9. the method for grow nanowire according to claim 1, is characterized in that: the substrate of growing epitaxial nano wire both can be planar substrate, also can be that planar substrate is along the graph substrate after the cutting of certain crystal orientation.
10. the method for grow nanowire according to claim 1, is characterized in that: the transfer techniques of nano wire is anode linkage technology, or the transfer techniques of other nano wires.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510586924.9A CN105239156A (en) | 2015-09-15 | 2015-09-15 | Method for preparing plane semiconductor nanowire through epitaxial orientated growth, transfer and integration |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510586924.9A CN105239156A (en) | 2015-09-15 | 2015-09-15 | Method for preparing plane semiconductor nanowire through epitaxial orientated growth, transfer and integration |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105239156A true CN105239156A (en) | 2016-01-13 |
Family
ID=55036968
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510586924.9A Pending CN105239156A (en) | 2015-09-15 | 2015-09-15 | Method for preparing plane semiconductor nanowire through epitaxial orientated growth, transfer and integration |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105239156A (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106770543A (en) * | 2016-08-27 | 2017-05-31 | 黄辉 | A kind of electrochemical sensor based on nano wire microelectrode |
| CN106876520A (en) * | 2017-01-22 | 2017-06-20 | 杭州电子科技大学 | The device of control silicon nanowires trend |
| CN107086180A (en) * | 2017-03-15 | 2017-08-22 | 南京大学 | A kind of single nano-wire multichannel is multiplexed the preparation method of film transistor device |
| CN107640741A (en) * | 2017-03-15 | 2018-01-30 | 南京大学 | A kind of plane germanium silicon based on the supply of heterogeneous lamination noncrystal membrane and related nanowire growth pattern and the method for component regulation and control |
| CN108231542A (en) * | 2018-01-09 | 2018-06-29 | 南京大学 | A kind of plane germanium silicon based on heterogeneous lamination noncrystal membrane and related nanowire growth method |
| CN109234807A (en) * | 2017-06-15 | 2019-01-18 | 南京大学 | A kind of stretchable crystalline semiconductor nano wire and preparation method thereof |
| CN109280903A (en) * | 2018-10-24 | 2019-01-29 | 中国科学院上海微***与信息技术研究所 | The preparation method of high density Ge nanoline |
| CN109813760A (en) * | 2019-02-28 | 2019-05-28 | 江苏理工学院 | A kind of zinc oxide nanowire gas sensor and preparation method thereof |
| CN111081534A (en) * | 2019-12-25 | 2020-04-28 | 上海集成电路研发中心有限公司 | Method for forming semiconductor nano-wire |
| CN111128723A (en) * | 2019-12-25 | 2020-05-08 | 上海集成电路研发中心有限公司 | Method for forming semiconductor nano-wire |
| CN111112642A (en) * | 2019-12-18 | 2020-05-08 | 宁波大学 | Method for preparing germanium nanowires |
| WO2020228421A1 (en) * | 2019-05-13 | 2020-11-19 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, and display panel |
| CN114256147A (en) * | 2020-09-22 | 2022-03-29 | 荣耀终端有限公司 | Method for manufacturing semiconductor structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101891198A (en) * | 2009-05-22 | 2010-11-24 | 熊长宏 | Solid-liquid-solid phase preparation method of Si nanowires |
-
2015
- 2015-09-15 CN CN201510586924.9A patent/CN105239156A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101891198A (en) * | 2009-05-22 | 2010-11-24 | 熊长宏 | Solid-liquid-solid phase preparation method of Si nanowires |
Non-Patent Citations (2)
| Title |
|---|
| LINWEI YU ET AL.: ""In-Plane Epitaxial Growth of Silicon Nanowires and Junction Formation on Si(100) Substrates"", 《NANOLETTERS》 * |
| MINGKUN XU ET AL.: "Operating principles of in-plane silicon nanowires at simple step-edges", 《NANOSCALE》 * |
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106770543A (en) * | 2016-08-27 | 2017-05-31 | 黄辉 | A kind of electrochemical sensor based on nano wire microelectrode |
| CN106770543B (en) * | 2016-08-27 | 2019-03-01 | 黄辉 | A kind of electrochemical sensor based on nano wire microelectrode |
| CN106876520B (en) * | 2017-01-22 | 2019-01-15 | 杭州电子科技大学 | Control the device of silicon nanowires trend |
| CN106876520A (en) * | 2017-01-22 | 2017-06-20 | 杭州电子科技大学 | The device of control silicon nanowires trend |
| CN107640741B (en) * | 2017-03-15 | 2019-11-15 | 南京大学 | A method of plane germanium silicon and related nanowire growth pattern and component regulation based on the supply of heterogeneous lamination noncrystal membrane |
| CN107640741A (en) * | 2017-03-15 | 2018-01-30 | 南京大学 | A kind of plane germanium silicon based on the supply of heterogeneous lamination noncrystal membrane and related nanowire growth pattern and the method for component regulation and control |
| CN107086180A (en) * | 2017-03-15 | 2017-08-22 | 南京大学 | A kind of single nano-wire multichannel is multiplexed the preparation method of film transistor device |
| CN109234807A (en) * | 2017-06-15 | 2019-01-18 | 南京大学 | A kind of stretchable crystalline semiconductor nano wire and preparation method thereof |
| CN108231542A (en) * | 2018-01-09 | 2018-06-29 | 南京大学 | A kind of plane germanium silicon based on heterogeneous lamination noncrystal membrane and related nanowire growth method |
| CN109280903B (en) * | 2018-10-24 | 2020-10-20 | 中国科学院上海微***与信息技术研究所 | Preparation method of high-density germanium nanowire |
| CN109280903A (en) * | 2018-10-24 | 2019-01-29 | 中国科学院上海微***与信息技术研究所 | The preparation method of high density Ge nanoline |
| CN109813760A (en) * | 2019-02-28 | 2019-05-28 | 江苏理工学院 | A kind of zinc oxide nanowire gas sensor and preparation method thereof |
| US11715744B2 (en) | 2019-05-13 | 2023-08-01 | Boe Technology Group Co., Ltd. | Array substrate, preparation method thereof, and display panel |
| WO2020228421A1 (en) * | 2019-05-13 | 2020-11-19 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, and display panel |
| CN111112642A (en) * | 2019-12-18 | 2020-05-08 | 宁波大学 | Method for preparing germanium nanowires |
| CN111112642B (en) * | 2019-12-18 | 2022-09-27 | 宁波大学 | Method for preparing germanium nanowires |
| CN111128723A (en) * | 2019-12-25 | 2020-05-08 | 上海集成电路研发中心有限公司 | Method for forming semiconductor nano-wire |
| CN111081534A (en) * | 2019-12-25 | 2020-04-28 | 上海集成电路研发中心有限公司 | Method for forming semiconductor nano-wire |
| CN111128723B (en) * | 2019-12-25 | 2023-09-15 | 上海集成电路研发中心有限公司 | Method for forming semiconductor nanowire |
| CN111081534B (en) * | 2019-12-25 | 2023-10-27 | 上海集成电路研发中心有限公司 | Method for forming semiconductor nanowire |
| CN114256147A (en) * | 2020-09-22 | 2022-03-29 | 荣耀终端有限公司 | Method for manufacturing semiconductor structure |
| CN114256147B (en) * | 2020-09-22 | 2023-05-23 | 荣耀终端有限公司 | Method for preparing semiconductor structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105239156A (en) | Method for preparing plane semiconductor nanowire through epitaxial orientated growth, transfer and integration | |
| US11257967B2 (en) | Solar cells | |
| Han et al. | Facile synthesis and growth mechanism of Ni-catalyzed GaAs nanowires on non-crystalline substrates | |
| CN105177706A (en) | Method for preparing high-quality flexible monocrystal silicon nanowire | |
| CN102623521A (en) | Method for preparing cuprous oxide film | |
| KR101848460B1 (en) | Preparation of copper selenide nanoparticles | |
| CN109056057B (en) | Preparation method of large-size single-crystal gallium oxide nanosheet | |
| Hainey et al. | Aluminum-catalyzed silicon nanowires: Growth methods, properties, and applications | |
| CN112490112A (en) | Gallium oxide film and heteroepitaxial growth method and application thereof | |
| Eisenhawer et al. | Growth of axial SiGe heterostructures in nanowires using pulsed laser deposition | |
| Hetzel et al. | Ultra-fast vapour–liquid–solid synthesis of Si nanowires using ion-beam implanted gallium as catalyst | |
| CN103320866A (en) | Molecular beam epitaxial (MBE) growth method of Bi element regulated and controlled GaAs-based nanowire crystal structure | |
| CN114717657B (en) | Method for growing nickel oxide monocrystal film based on plasma-assisted laser molecular beam epitaxy | |
| CN103094073B (en) | The preparation method of semi-insulating silicon carbide substrate titanium ohmic contact electrode | |
| CN101798672A (en) | Method for preparing P-type zinc oxide film from in situ low-pressure oxidized aluminum-doped zinc nitride | |
| CN102456786B (en) | Light-emitting Diode And Its Making Method | |
| CN105529242B (en) | A kind of method for preparing bead string shape monocrystalline silicon nano line | |
| Thandavan et al. | Synthesis of ZnO nanowires via hotwire thermal evaporation of brass (CuZn) assisted by vapor phase transport of methanol | |
| KR102010420B1 (en) | Single-crystal metal thin film and preparing method thereof | |
| CN107723789B (en) | Low-temperature epitaxial preparation method of high-quality gray tin single crystal film | |
| US20140196775A1 (en) | Synthesis method of cu(in,ga)se2 nanorod or nanowire and materials including the same | |
| Dujavová-Laurenčíková et al. | Ohmic contacts to p-GaP/n-ZnO core/shell nanowires based on Au metallization | |
| Kouvetakis et al. | Si-Ge-Sn technologies: From molecules to materials to prototype devices | |
| Zou et al. | Assembly-line flash synthesis of ZnO nanobelts on metal Zn | |
| CN112877779B (en) | Method for growing high-quality GaAs nanowire based on Sn catalysis gas phase |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160113 |
|
| RJ01 | Rejection of invention patent application after publication |