CN105224241A - Mram memory, data-storage system and method for reading data - Google Patents

Mram memory, data-storage system and method for reading data Download PDF

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Publication number
CN105224241A
CN105224241A CN201410283328.9A CN201410283328A CN105224241A CN 105224241 A CN105224241 A CN 105224241A CN 201410283328 A CN201410283328 A CN 201410283328A CN 105224241 A CN105224241 A CN 105224241A
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data
mram
read
memory
interface
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赵继勋
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Beijing legend core technology Co., Ltd.
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Lenovo Beijing Ltd
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Abstract

The embodiment of the present invention provides a kind of mram memory, data-storage system and method for reading data, and wherein MRAM storage comprises: the NAND interface receiving data operation commands; According to the data operation commands that described NAND interface receives, perform the MRAM array of data manipulation; Obtain and data to be read in buffer memory MRAM array, and by the page buffer Page of described data to be read by described NAND interface output? Buffer; Wherein, described MRAM array is connected with described NAND interface by described page buffer.Page buffer, using the data-interface of NAND interface as mram memory, is read out the region of data by the embodiment of the present invention simultaneously from mram memory as external unit, the speed making mram memory read data is improved.

Description

Mram memory, data-storage system and method for reading data
Technical field
The present invention relates to technical field of memory, more particularly, relate to a kind of mram memory, data-storage system and method for reading data.
Background technology
MRAM (MagneticRandomAccessMemory, nonvolatile magnetic RAM) storer is the one of data-carrier store, the high speed having static RAM (SRAM) due to mram memory reads write capability, and the high integration of dynamic RAM (DRAM), substantially can carry out repeating write, therefore the application of mram memory is comparatively extensive unlimitedly.
The present inventor finds in research process: although mram memory repeating to write and have comparatively outstanding performance (substantially can carry out unlimited repeat write) in data, but mram memory (as when making page (Page) and reading) when carrying out digital independent, the data read rates of mram memory is still comparatively slow relative to storeies such as SRAM, and the data read rates how promoting mram memory is the problem that those skilled in the art very pay close attention to always.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of mram memory, data-storage system and method for reading data, to realize the object of the data read rates promoting mram memory.
For achieving the above object, the embodiment of the present invention provides following technical scheme:
A kind of mram memory, comprising:
Receive the NAND interface of data operation commands;
According to the data operation commands that described NAND interface receives, perform the MRAM array of data manipulation;
Obtain and data to be read in buffer memory MRAM array, and by the page buffer PageBuffer of described data to be read by described NAND interface output;
Wherein, described MRAM array is connected with described NAND interface by described page buffer.
Wherein, described mram memory also comprises:
Be connected with described MRAM array with described NAND interface respectively, resolve the data operation commands that described NAND interface receives, to control described MRAM array at least one code translator according to analysis result execution data manipulation.
Wherein, described mram memory also comprises:
The X-direction address decoder be connected with described MRAM array;
And/or, the Y-direction address decoder be connected with described MRAM array;
And/or, command decoder.
Wherein, described mram memory also comprises:
Double Data Rate synchronous DRAM ddr interface, and/or, static RAM SRAM interface, and/or, serial peripheral equipment interface SPI interface.
The embodiment of the present invention also provides a kind of data-storage system, comprising: nand flash memory controller, and mram memory described above; Described nand flash memory controller is articulated on described NAND interface, for controlling described mram memory access data.
The embodiment of the present invention also provides a kind of method for reading data, and based on mram memory described above, described method comprises:
NAND interface data read command;
MRAM array determines the to be read data corresponding with described data read command;
Page buffer PageBuffer obtains and data to be read described in buffer memory, and described data to be read is exported by described NAND interface.
Wherein, described MRAM array determines that the to be read data corresponding with described data read command comprise:
Resolve by code translator the data read command that described NAND interface receives, and obtain analysis result;
The data read address corresponding with described data read command is determined according to described analysis result;
Determine that the data corresponding with described data read address are described data to be read.
Wherein, described page buffer obtains and described in buffer memory, data to be read comprise:
After described MRAM array determines described data to be read, receive the data described to be read of described MRAM Array transfer, data to be read described in buffer memory.
The embodiment of the present invention also provides a kind of method for reading data, and based on a kind of data-storage system, described data-storage system comprises: nand flash memory controller, and mram memory described above; Described nand flash memory controller is articulated on described NAND interface, for controlling described mram memory access data; Described method comprises:
Described nand flash memory controller sends data read command;
The NAND interface data read command of described mram memory;
The MRAM array of described mram memory determines the to be read data corresponding with described data read command;
The page buffer PageBuffer of described mram memory obtains and data to be read described in buffer memory, and under the control of described nand flash memory controller, exports the data to be read of institute's buffer memory to described nand flash memory controller by described NAND interface.
Wherein, the MRAM array of described mram memory determines that the to be read data corresponding with described data read command comprise:
Resolve by the code translator of mram memory the data read command that described NAND interface receives, and obtain analysis result;
The data read address corresponding with described data read command is determined according to described analysis result;
Determine that the data corresponding with described data read address are described data to be read.
Based on technique scheme, the mram memory that the embodiment of the present invention provides, data operation commands is received as the data-interface of mram memory by NAND interface, make mram memory can be mutually compatible with nand flash memory controller, by nand flash memory technology (data reading speed of nand flash memory technology is much larger than writing speed), mram memory can have larger data reading speed; Simultaneously, by data to be read in page buffer buffer memory MRAM array, so that external unit reads out data from page buffer, because MRAM array filling page buffer required time is shorter, and page buffer has larger interface data bandwidth, therefore external unit reads out the time of data from the mram memory that the embodiment of the present invention provides, and is less than the time reading out data from nand flash memory; Page buffer, using the data-interface of NAND interface as mram memory, is read out the region of data by the embodiment of the present invention simultaneously from mram memory as external unit, the speed making mram memory read data is improved.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments of the invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to the accompanying drawing provided.
The structured flowchart of the mram memory that Fig. 1 provides for the embodiment of the present invention;
Another structured flowchart of the mram memory that Fig. 2 provides for the embodiment of the present invention;
A structured flowchart again of the mram memory that Fig. 3 provides for the embodiment of the present invention;
The process flow diagram of the method for reading data that Fig. 4 provides for the embodiment of the present invention;
The structured flowchart of the data-storage system that Fig. 5 provides for the embodiment of the present invention;
Another process flow diagram of the method for reading data that Fig. 6 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The structured flowchart of the mram memory that Fig. 1 provides for the embodiment of the present invention, with reference to Fig. 1, this mram memory can comprise: NAND interface 10, MRAM array 20, page buffer (PageBuffer) 30; Wherein, MRAM array 20 is connected with NAND interface 10 by page buffer 30.
In embodiments of the present invention, NAND interface 10, as the data-interface of mram memory, can be used for receiving the data operation commands for mram memory;
It should be noted that NAND interface 10 can think one in the numerous data-interface of mram memory, also can think that mram memory only has this data-interface of NAND interface 10;
MRAM array 20 is the core of mram memory, the data operation commands that can receive according to NAND interface 10, performs data manipulation;
In embodiments of the present invention, data operation commands can comprise data storage command and data read command, and namely MRAM array 20 can perform data storage operations, stores external data, also data read operation can be performed, by the data reading stored in mram memory.
Corresponding, when data operation commands is data read command, MRAM array can perform data read operation, determines the data to be read in MRAM array.After determining the data to be read in MRAM array, page buffer 30 can obtain and data to be read in buffer memory MRAM array, and exports described data to be read to external unit by NAND interface 10.
Optionally, in embodiments of the present invention, NAND interface can be NANDFlash interface, and page buffer PageBuffer can be the PageBuffer based on SRAM.
The mram memory that the embodiment of the present invention provides, data operation commands is received as the data-interface of mram memory by NAND interface, make mram memory can be mutually compatible with nand flash memory controller, by nand flash memory technology (data reading speed of nand flash memory technology is much larger than writing speed), mram memory can have larger data reading speed; Simultaneously, by data to be read in page buffer buffer memory MRAM array, so that external unit reads out data from page buffer, because MRAM array filling page buffer required time is shorter, and page buffer has larger interface data bandwidth, therefore external unit reads out the time of data from the mram memory that the embodiment of the present invention provides, and is less than the time reading out data from nand flash memory; Page buffer, using the data-interface of NAND interface as mram memory, is read out the region of data by the embodiment of the present invention simultaneously from mram memory as external unit, the speed making mram memory read data is improved.
Another structured flowchart of the mram memory that Fig. 2 provides for the embodiment of the present invention, shown in composition graphs 1 and Fig. 2, mram memory can also comprise: at least one code translator 40; For ease of drawing, Fig. 2 illustrate only the code translator of a quantity, but actually arranges, and the quantity of code translator can be one or more.
In embodiments of the present invention, code translator 40 can be connected with MRAM array 20 with NAND interface 10 respectively, after NAND interface 10 receives data operation commands, code translator 40 can resolve the data operation commands that NAND interface 10 receives, and analysis result is passed to MRAM array 20, perform data manipulation with control MRAM array 20 according to analysis result.
The mram memory that the embodiment of the present invention provides can be as follows in data manipulation flow process: NAND interface data operation commands, code translator is resolved this data operation commands and analysis result is passed to MRAM array, and MRAM array performs data manipulation according to analysis result; Corresponding, if analysis result is the analysis result that data storage command is corresponding, then MRAM array can determine that data to be stored are (optional, data to be stored are carried in data storage command), and store data to be stored (optional, if there is address data memory in analysis result, then data to be stored can be stored in region corresponding to this address data memory, if there is not address data memory in analysis result, then can store data to be stored at random); Corresponding, if analysis result is the analysis result that data read command is corresponding, then MRAM array can determine that data to be read in MRAM array are (optional, by the data read address carried in analysis result, determine data to be read in MRAM array), and by data-moving to be read to page buffer, to obtain and after data to be read in buffer memory MRAM array, page buffer can export described data to be read to external unit by NAND interface at page buffer.
A structured flowchart again of the mram memory that Fig. 3 provides for the embodiment of the present invention, shown in composition graphs 1 and Fig. 3, mram memory can also comprise: X-direction address decoder 50, Y-direction address decoder 60 and command decoder 70; X-direction address decoder 50, Y-direction address decoder 60 is connected with MRAM array 20 respectively with command decoder 70;
Wherein, X-direction address decoder 50 is mainly used in the address decoding of X-direction in MRAM array 20;
Y-direction address decoder 60 is mainly used in carrying out decoding gating to the storage unit in a line in MRAM array;
Shown in the function of command decoder 70 and Fig. 2, the function class of code translator 40 seemingly, can refer to.
It should be noted that the mram memory provided in the embodiment of the present invention also can comprise the address decoder of X-direction shown in Fig. 3 50, at least one in Y-direction address decoder 60 and command decoder 70.
Already described above, NAND interface 10 can think one in the numerous data-interface of mram memory; Optionally, mram memory can also comprise other data-interface, as DDR (Double Data Rate synchronous DRAM) interface, and/or, SRAM (static RAM) interface, and/or, SPI (Serial Peripheral Interface (SPI)) interface.
After deliberation, the SRAM memory that provides of the embodiment of the present invention at least tool have the following advantages:
The setting of NAND interface in mram memory, mram memory can be made can to have good compatibility, can directly and the nand flash memory controller of SOC (SystemonChip, system level chip) mount mutually, MRAM is stored and applies widely.
Meanwhile, when being Page and reading, because MRAM array reading speed is higher than nand flash memory, and have employed the PageBuffer with larger data bandwidth, mram memory can be made to reach data reading speed higher than nand flash memory.
In addition, mram memory is after being articulated on nand flash memory controller, due to the high reliability of MRAM, there is not nand flash memory and need ECC (ErrorCorrectingCode, bug check and correction) process of error correction, the expense that time of correcting data error and software manage storer can be saved in data read process.
Further, due to the high reliability of mram memory, supporting to store more start-up code in the mram memory with NAND interface in the SOC that nand flash memory starts, and do not worrying that start-up code lost efficacy because of the mistake of storage array.
Be introduced the method for reading data that the embodiment of the present invention provides below, method for reading data described below can based on above-described mram memory, hereafter describe in content relate to part that MRAM stores can with phase reference above.
The process flow diagram of the method for reading data that Fig. 4 provides for the embodiment of the present invention, with reference to Fig. 4, the method can comprise:
Step S100, NAND interface data read command;
Step S110, MRAM array determine the to be read data corresponding with described data read command;
Optionally, MRAM array is by resolving with the code translator that NAND interface is connected with MRAM array the data read command that NAND interface receives, thus get analysis result, and then determine the data read address corresponding with the data read command that NAND interface receives according to analysis result, determine the data corresponding with described data read address; Determined and that described data read address is corresponding data are the data to be read that MRAM array is determined herein.
Step S120, page buffer PageBuffer obtain and data to be read described in buffer memory, and described data to be read are exported by described NAND interface.
Optionally, page buffer can receive the data to be read of MRAM Array transfer, realizes the buffer memory of described data to be read.Corresponding, after MRAM array determines described data to be read, page buffer can receive the data described to be read of MRAM Array transfer, data to be read described in buffer memory.
Optionally, after MRAM array determines described data to be read, page buffer also initiatively can obtain described data to be read from MRAM array.
The method for reading data that the embodiment of the present invention provides, by NAND interface data read command, make mram memory can be mutually compatible with nand flash memory controller, by nand flash memory technology, mram memory can have larger data reading speed; Simultaneously, by data to be read in page buffer buffer memory MRAM array, so that external unit reads out data from page buffer, because MRAM array filling page buffer required time is shorter, and page buffer has larger interface data bandwidth, therefore external unit reads out the time of data from the mram memory that the embodiment of the present invention provides, and is less than the time reading out data from nand flash memory; The method for reading data that the embodiment of the present invention provides can promote the speed that mram memory reads data.
Optionally, the mram memory that the embodiment of the present invention provides can mount nand flash memory controller.Below the data-storage system that the embodiment of the present invention provides is introduced, hereafter describe in relate to mram memory part can with corresponding reference above.
The structured flowchart of the data-storage system that Fig. 5 provides for the embodiment of the present invention, with reference to Fig. 5, this data-storage system can comprise: nand flash memory controller 100, and mram memory 200; Wherein, mram memory 200 can be above-described mram memory.
Wherein, nand flash memory controller 100 can be used for controlling mram memory 200 access data; In connected mode, nand flash memory controller can be articulated on the NAND interface of mram memory 200.
The data-storage system that the embodiment of the present invention provides, by the setting of NAND interface in mram memory, can make mram memory can mount mutually with nand flash memory controller, MRAM be stored and applies widely.
In addition, mram memory is after being articulated on nand flash memory controller, and due to the high reliability of MRAM, there is not nand flash memory needs ECC (ErrorCorrectingCode, bug check and correction) error correction procedure, substantially increase the overall performance of data-storage system.
Based on data-storage system shown in Fig. 5, be introduced below to another method for reading data that the embodiment of the present invention provides, method for reading data described below can with corresponding part be cross-referenced above.
Another process flow diagram of the method for reading data that Fig. 6 provides for the embodiment of the present invention, with reference to Fig. 6, the method can comprise:
Step S200, nand flash memory controller send data read command;
The NAND interface data read command of step S210, mram memory;
The MRAM array of step S220, mram memory determines the to be read data corresponding with described data read command;
Optionally, MRAM array resolves by the code translator of mram memory the data read command that described NAND interface receives, and obtain analysis result, thus determine the data read address corresponding with described data read command according to described analysis result, determine that the data corresponding with described data read address are described data to be read.
The page buffer of step S230, mram memory obtains and data to be read described in buffer memory, and under the control of described nand flash memory controller, exports the data to be read of institute's buffer memory to described nand flash memory controller by described NAND interface.
The method for reading data that the embodiment of the present invention provides, using the data-interface of NAND interface as mram memory, page buffer is read out from mram memory the region of data as nand flash memory controller, the speed making mram memory read data is improved simultaneously.
In this instructions, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar portion mutually see.For device disclosed in embodiment, because it corresponds to the method disclosed in Example, so description is fairly simple, relevant part illustrates see method part.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.

Claims (10)

1. a mram memory, is characterized in that, comprising:
Receive the NAND interface of data operation commands;
According to the data operation commands that described NAND interface receives, perform the MRAM array of data manipulation;
Obtain and data to be read in buffer memory MRAM array, and by the page buffer PageBuffer of described data to be read by described NAND interface output;
Wherein, described MRAM array is connected with described NAND interface by described page buffer.
2. mram memory according to claim 1, is characterized in that, also comprises:
Be connected with described MRAM array with described NAND interface respectively, resolve the data operation commands that described NAND interface receives, to control described MRAM array at least one code translator according to analysis result execution data manipulation.
3. mram memory according to claim 1, is characterized in that, also comprises:
The X-direction address decoder be connected with described MRAM array;
And/or, the Y-direction address decoder be connected with described MRAM array;
And/or, command decoder.
4. the mram memory according to any one of claim 1-3, is characterized in that, also comprises:
Double Data Rate synchronous DRAM ddr interface, and/or, static RAM SRAM interface, and/or, serial peripheral equipment interface SPI interface.
5. a data-storage system, is characterized in that, comprising: nand flash memory controller, and the mram memory described in any one of claim 1-4; Described nand flash memory controller is articulated on described NAND interface, for controlling described mram memory access data.
6. a method for reading data, is characterized in that, based on the mram memory described in any one of claim 1-4, described method comprises:
NAND interface data read command;
MRAM array determines the to be read data corresponding with described data read command;
Page buffer PageBuffer obtains and data to be read described in buffer memory, and described data to be read is exported by described NAND interface.
7. method for reading data according to claim 6, is characterized in that, described MRAM array determines that the to be read data corresponding with described data read command comprise:
Resolve by code translator the data read command that described NAND interface receives, and obtain analysis result;
The data read address corresponding with described data read command is determined according to described analysis result;
Determine that the data corresponding with described data read address are described data to be read.
8. the method for reading data according to claim 6 or 7, is characterized in that, described page buffer obtains and described in buffer memory, data to be read comprise:
After described MRAM array determines described data to be read, receive the data described to be read of described MRAM Array transfer, data to be read described in buffer memory.
9. a method for reading data, is characterized in that, based on a kind of data-storage system, described data-storage system comprises: nand flash memory controller, and the mram memory described in any one of claim 1-4; Described nand flash memory controller is articulated on described NAND interface, for controlling described mram memory access data; Described method comprises:
Described nand flash memory controller sends data read command;
The NAND interface data read command of described mram memory;
The MRAM array of described mram memory determines the to be read data corresponding with described data read command;
The page buffer PageBuffer of described mram memory obtains and data to be read described in buffer memory, and under the control of described nand flash memory controller, exports the data to be read of institute's buffer memory to described nand flash memory controller by described NAND interface.
10. method for reading data according to claim 9, is characterized in that, the MRAM array of described mram memory determines that the to be read data corresponding with described data read command comprise:
Resolve by the code translator of mram memory the data read command that described NAND interface receives, and obtain analysis result;
The data read address corresponding with described data read command is determined according to described analysis result;
Determine that the data corresponding with described data read address are described data to be read.
CN201410283328.9A 2014-06-23 2014-06-23 Mram memory, data-storage system and method for reading data Pending CN105224241A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110727470A (en) * 2018-06-29 2020-01-24 上海磁宇信息科技有限公司 Hybrid non-volatile storage device
CN113220616A (en) * 2021-05-31 2021-08-06 北京航空航天大学 FPGA-based interface conversion system and method from SDRAM to MRAM

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1661582A (en) * 2004-02-29 2005-08-31 深圳市朗科科技有限公司 Data processing chip and memory device
US20130265826A1 (en) * 2012-04-09 2013-10-10 Samsung Electronics Co., Ltd. Memory system and operating method of controller
CN103578555A (en) * 2012-07-19 2014-02-12 三星电子株式会社 Nonvolatile memory, reading method of nonvolatile memory, and memory system including nonvolatile memory
CN103714856A (en) * 2012-10-05 2014-04-09 三星电子株式会社 Memory system and read reclaim method thereof
US20140149786A1 (en) * 2011-11-08 2014-05-29 Micron Technology, Inc. Apparatuses and methods for operating a memory device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1661582A (en) * 2004-02-29 2005-08-31 深圳市朗科科技有限公司 Data processing chip and memory device
US20140149786A1 (en) * 2011-11-08 2014-05-29 Micron Technology, Inc. Apparatuses and methods for operating a memory device
US20130265826A1 (en) * 2012-04-09 2013-10-10 Samsung Electronics Co., Ltd. Memory system and operating method of controller
CN103578555A (en) * 2012-07-19 2014-02-12 三星电子株式会社 Nonvolatile memory, reading method of nonvolatile memory, and memory system including nonvolatile memory
CN103714856A (en) * 2012-10-05 2014-04-09 三星电子株式会社 Memory system and read reclaim method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110727470A (en) * 2018-06-29 2020-01-24 上海磁宇信息科技有限公司 Hybrid non-volatile storage device
CN113220616A (en) * 2021-05-31 2021-08-06 北京航空航天大学 FPGA-based interface conversion system and method from SDRAM to MRAM
CN113220616B (en) * 2021-05-31 2022-11-15 北京航空航天大学 FPGA-based interface conversion system and method from SDRAM to MRAM

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