CN105208380B - Verification platform and system - Google Patents
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Abstract
The invention discloses a kind of verification platform and systems.Wherein, which includes：Programming logic gate array FPGA is designed verification for the corresponding intellectual property IP kernel of IC design to high definition digital video interface；Program download interface, is connected with FPGA, for the corresponding program of IP kernel to be downloaded in FPGA.The present invention solve in correlation technique due to the unspecial verification platform for high definition digital video interface IP and caused by the technical issues of being difficult to verify high definition digital video interface IP exactly.
Description
Technical field
The present invention relates to circuit design verification field, in particular to a kind of verification platform and system.
Background technology
Usually, for integrated circuit reusing design intellectual property (Intellectual Property, referred to as
IP) core, in programming to application-specific integrated circuit, (Application Specific Integrated Circuit are referred to as
ASIC) before chip, it is necessary to which (FieldProgrammableGate Array are referred to as programmable gate array at the scene
FPGA design verification) is carried out on platform, can just freeze the IP core design after being verified, and then enter the flow stage.
For example, during design high definition digital video interface, before IP asic chips are made, must generally test to retouch
State the IP kernel of high definition digital video interface and high-definition digital display interface (Display Port, referred to as DP) and high-definition multimedia
The corresponding signal of interface (High Definition Multimedia Interface, referred to as HDMI) transmits/receives port
(Receiver/Transmitter, referred to as TX/RX), i.e. DP TX/RX, HDMI TX/RX and mobile Industry Processor connect
The corresponding receiver port of mouth (Mobile Industry Processor Interface, referred to as MIPI), i.e. MIPI
TX/RX。
Although FPGA has been widely used and asic chip verification, communication signal processing, computer digit processing, consumer electronics
The fields such as product design and Industry Control, but since FPGA can the application characteristic of flexible programming and high definition digital video interface skill
The primacy and technical difficulty of art currently without dedicated for verifying the FPGA application platforms of high definition digital video interface IP, are led
Cause is difficult to verify high definition digital video interface IP exactly.
For it is above-mentioned the problem of, currently no effective solution has been proposed.
The content of the invention
An embodiment of the present invention provides a kind of verification platform and system, at least to solve in correlation technique due to unspecial
The verification platform for high definition digital video interface IP and caused by be difficult to verify high definition digital video interface IP's exactly
Technical problem.
One side according to embodiments of the present invention provides a kind of verification platform, including：Programmable gate array
FPGA is designed verification for the corresponding intellectual property IP kernel of IC design to high definition digital video interface；Program
Download interface is connected with above-mentioned FPGA, for the corresponding program of above-mentioned IP kernel to be downloaded in above-mentioned FPGA.
Further, above-mentioned verification platform further includes：Program storage, be connected to above procedure download interface with it is above-mentioned
Between FPGA, for storing the corresponding program of above-mentioned IP kernel downloaded by above procedure download interface.
Further, above-mentioned verification platform is further included at least one of lower port or port set：High-definition digital is shown
Receiving port DP RX and Low Voltage Differential Signal LVDS output ports；High-definition digital shows sending port DP TX；High-definition multimedia
Receiving port HDMI RX and above-mentioned Low Voltage Differential Signal LVDS output ports；High-definition multimedia sending port HDMI TX；It is mobile
Industry Processor sending port MIPI TX.
Further, above-mentioned high-definition digital shows receiving port DP RX, is connected with above-mentioned FPGA, for receiving external height
The DP digital format images of clear numerical monitor DP signal sources output；Above-mentioned Low Voltage Differential Signal LVDS output ports, it is and above-mentioned
FPGA connections, for exporting the picture signal that above-mentioned FPGA is recovered according to the above-mentioned DP RX digital format images received.
Further, above-mentioned verification platform further includes：External memory is connected with above-mentioned FPGA, for store by
State the above-mentioned DP digital format images of DP signal sources output.
Further, above-mentioned high-definition digital shows sending port DP TX, is connected with above-mentioned FPGA, for reading external height
The test image signal for meeting the picture format of generation is simultaneously sent to above-mentioned by the picture format of clear number DP display screens support
DP display screens.
Further, above-mentioned high-definition multimedia receiving port HDMI RX, are connected with above-mentioned FPGA, for receiving external height
The HDMI digital format images of clear multimedia HDMI signal sources output；Above-mentioned Low Voltage Differential Signal LVDS output ports, it is and above-mentioned
FPGA connections, for exporting the image that above-mentioned FPGA is recovered according to the above-mentioned HDMI RX HDMI digital format images received
Signal.
Further, above-mentioned high-definition multimedia sending port HDMI TX, are connected with above-mentioned FPGA, for reading external height
The test image signal for meeting the picture format of generation is simultaneously sent to by the picture format of clear multimedia HDMI display screens support
Above-mentioned HDMI display screens.
Further, above-mentioned mobile Industry Processor sending port MIPI TX, are connected with above-mentioned FPGA, for that will generate
Test image signal be sent to HDMI display screens.
Another aspect according to embodiments of the present invention additionally provides a kind of verification system, including：The above-mentioned verification of any one
Platform.
In embodiments of the present invention, using the side for designing special FPGA verification platforms verification high definition digital video interface IP
Formula, by programming logic gate array FPGA, for the corresponding knowledge production of IC design to high definition digital video interface
Power IP kernel is designed verification；Program download interface, is connected with FPGA, for the corresponding program of IP kernel to be downloaded in FPGA,
The special verification platform purpose for high definition digital video interface IP of design is reached, it is achieved thereby that verifying high definition exactly
The technique effect of digital visual interface IP, and then solve in correlation technique and connect due to unspecial for high-definition digital video
The verification platform of mouthful IP and caused by the technical issues of being difficult to verify high definition digital video interface IP exactly.
Description of the drawings
Attached drawing described herein is used for providing a further understanding of the present invention, forms the part of the application, this hair
Bright schematic description and description does not constitute improper limitations of the present invention for explaining the present invention.In the accompanying drawings：
Fig. 1 is a kind of schematic diagram of optional verification system according to embodiments of the present invention；
Fig. 2 is a kind of schematic diagram of optional DP RX IP verifications system according to embodiments of the present invention；
Fig. 3 is a kind of schematic diagram of optional DP TX IP verifications system according to embodiments of the present invention；
Fig. 4 is a kind of schematic diagram of optional HDMI RX IP verifications system according to embodiments of the present invention；
Fig. 5 is a kind of schematic diagram of optional HDMI TX IP verifications system according to embodiments of the present invention；
Fig. 6 is a kind of schematic diagram of optional MIPI TX IP verifications system according to embodiments of the present invention；
Fig. 7 is a kind of schematic diagram of optional verification platform according to embodiments of the present invention.
Specific embodiment
In order to which those skilled in the art is made to more fully understand the present invention program, below in conjunction in the embodiment of the present invention
The technical solution in the embodiment of the present invention is clearly and completely described in attached drawing, it is clear that described embodiment is only
The embodiment of a part of the invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people
Member's all other embodiments obtained without making creative work should all belong to the model that the present invention protects
It encloses.
It should be noted that term " first " in description and claims of this specification and above-mentioned attached drawing, "
Two " etc. be the object for distinguishing similar, without being used to describe specific order or precedence.It should be appreciated that it so uses
Data can exchange in the appropriate case, so as to the embodiment of the present invention described herein can with except illustrating herein or
Order beyond those of description is implemented.In addition, term " comprising " and " having " and their any deformation, it is intended that cover
Cover non-exclusive include.
Embodiment 1
According to embodiments of the present invention, a kind of device embodiment of verification system is provided.
The verification system includes：Verification platform.Wherein, which includes：Programming logic gate array FPGA is used for
Verification is designed to the corresponding intellectual property IP kernel of the IC design of high definition digital video interface；Program download interface,
It is connected with FPGA, for the corresponding program of IP kernel to be downloaded in FPGA.
Optionally, above-mentioned verification platform can also be the technology that any preferred embodiment is provided in following embodiments 2
Verification platform in scheme, details are not described herein.
Fig. 1 is a kind of schematic diagram of optional verification system according to embodiments of the present invention, as shown in Figure 1, the system bag
It includes：Verification platform 10 and host computer 20.During implementation, host computer 20 can be by the ASIC for the high definition digital video interface being pre-designed
IP kernel in chip passes through (such as FPGA JTAG (the Joint Test Action of program download interface 104 on verification platform 10
Group) download interface) it directly downloads into the FPGA 102 in verification platform 10, while host computer 20 can pass through FPGA
IP kernel in the asic chip of JTAG download interfaces on-line debugging and monitoring high definition digital video interface.Wherein, in IP program liters
During grade, verification platform 10 can download the IP programs after upgrading by program download interface 104 at host computer 20.But the verification
After platform power-off, code can be lost in FPGA 102.
By the embodiment of the present invention, solve the prior art and be difficult to verify that high-definition digital video connects in asic chip exactly
The problem of corresponding IP kernel, has reached the special verification platform purpose for high definition digital video interface IP of design, so as to real
The technique effect for verifying high definition digital video interface IP exactly is showed, and then has improved and realize high definition digital video interface
The purpose of the success rate of IP.
Further, above-mentioned verification system in addition to including verification platform 10 and host computer 20, can also include following
One or more in external equipment：High-definition digital shows DP signal sources, Low Voltage Differential Signal LVDS display screens, DP display screens
(or DP displays), high-definition multimedia HDMI signal sources, HDMI display screens (or HDMI display), MIPI turn HDMI TX chips,
So as to respectively constitute such as the verification system in Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6.Wherein, Fig. 2 is according to embodiments of the present invention one
The schematic diagram of the optional DP RX IP verifications system of kind；Fig. 3 is that a kind of optional DP TX IP according to embodiments of the present invention are tested
The schematic diagram of card system；Fig. 4 is a kind of schematic diagram of optional HDMI RX IP verifications system according to embodiments of the present invention；Figure
5 be a kind of schematic diagram of optional HDMI TX IP verifications system according to embodiments of the present invention；Fig. 6 is to implement according to the present invention
A kind of schematic diagram of optional MIPI TX IP verifications system of example.In this way, verification platform 10 can be loaded by FPGA 102
Different high definition digital video interface asic chip IP, and different external equipments is coordinated to form different verification systems and is designed
Verification.
It should be noted that the verification system involved in Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6 will combine in following embodiments 2
Corresponding verification platform is described in detail, and details are not described herein.
Embodiment 2
According to embodiments of the present invention, a kind of device embodiment of verification platform is provided.
Fig. 7 is a kind of schematic diagram of optional verification platform according to embodiments of the present invention, as shown in fig. 7, the verification is put down
Platform 10 includes：Programming logic gate array FPGA 102 (such as Xilinx Virtex-6XC6VLX240T), for high-definition digital
The corresponding intellectual property IP kernel (hereinafter referred to as high definition digital video interface IP) of IC design of video interface is set
Meter verification；Program download interface 104 is connected with FPGA 102, for the corresponding program of IP kernel to be downloaded in FPGA 102.
With reference to Fig. 1 and Fig. 7, host computer 20 can by high definition digital video interface IP by program download interface 104 (such as
FPGA JTAG download interfaces) it directly downloads into FPGA 102, while host computer 20 can be by program download interface 104 (such as
FPGA JTAG download interfaces) on-line debugging and monitoring high definition digital video interface IP.Wherein, when IP programs upgrade, verification is flat
Platform 10 can download the IP programs after upgrading by program download interface 104 at host computer 20.But after verification platform power-off,
Code can be lost in FPGA 102.
By the embodiment of the present invention, using the side for designing special FPGA verification platforms verification high definition digital video interface IP
Formula has reached the special verification platform purpose for high definition digital video interface IP of design, it is achieved thereby that verifying exactly
The technique effect of high definition digital video interface IP, and then improve the mesh for the success rate for realizing high definition digital video interface IP
's.
Optionally, as shown in fig. 7, above-mentioned verification platform 10 further includes：Program storage 106 is connected to program download and connects
Between mouth 104 and FPGA 102, for storing the corresponding program of IP kernel downloaded by program download interface 104.
With reference to Fig. 1 and Fig. 7, host computer 20 can by high definition digital video interface IP by program download interface 104 (such as
FPGA JTAG download interfaces) it is downloaded in the program storage 106 (i.e. EEPROM (XCF128X)) of FPGA, verification platform 10 powers on
Afterwards, FPGA 102 can load high definition digital video interface IP codes from the program storage 106 (i.e. EEPROM) of FPGA automatically
It is designed verification.In this way, after platform power-off, it is ensured that code is not lost in FPGA 2.
Optionally, the verification system with reference to involved in Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, in order to verify that high-definition digital video connects
The design conditions of different piece, above-mentioned verification platform 10 are further included at least one of lower port or port set in mouth IP：It is high
Clear numerical monitor receiving port DP RX (Receiver) and Low Voltage Differential Signal LVDS output ports；High-definition digital display is sent
Port DP TX；High-definition multimedia receiving port HDMI RX and Low Voltage Differential Signal LVDS output ports；High-definition multimedia is sent
Port HDMI TX (Transmitter)；Mobile Industry Processor sending port MIPI TX.As shown in fig. 7, above-mentioned verification platform
10 further include with lower port or port set：High-definition digital shows receiving port DP RX 108 and Low Voltage Differential Signal LVDS outputs
Port 110；High-definition digital shows sending port DP TX 112；High-definition multimedia receiving port HDMI RX 114 and low-voltage differential
Signal LVDS output ports 110；High-definition multimedia sending port HDMI TX 116；Mobile Industry Processor sending port MIPI
TX 118。
Below in conjunction with Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, different verification systems and correspondence system institute are elaborated
The function for the corresponding port being related to.
As shown in Fig. 2, DP RX IP verifications system includes：Verification platform 10, DP signal sources 30 and LVDS display screens 40.
Wherein, verification platform 10 is included with lower port：High-definition digital shows that receiving port DP RX 108 and Low Voltage Differential Signal LVDS are defeated
Exit port 110.Wherein, high-definition digital shows receiving port DP RX 108, is connected with FPGA 102, for receiving external high definition
The DP digital format images that numerical monitor DP signal sources 30 export；110 (such as 80pins of Low Voltage Differential Signal LVDS output ports
LVDS/LVTTL output interfaces), it is connected with FPGA 102, for exporting the digital lattice that FPGA 102 is received according to DP RX 108
The picture signal that formula image recovers.During implementation, DP signal sources 30 are connected with DP RX 108, and DP numbers are exported to FPGA 102
Word format image.FPGA 102 is connected with DP RX108, recovers the picture signal of the DP digital format images of DP signal sources 30.
FPGA 102 is connected with LVDS output ports 110, and the picture signal recovered is exported in the form of LVDS format-patterns.LVDS
Display screen 40 is connected with LVDS output ports 110, is displayed for the DP digital format images received from DP RX 108.
As shown in fig. 7, above-mentioned verification platform 10 further includes：External memory 120 is connected with FPGA 102, for storing
The DP digital format images exported by DP signal sources 30.Wherein, the external memory 120 of FPGA can be that Double Data Rate is synchronously dynamic
State random access memory DDR3 storage particles (MT41J64M16).As shown in Fig. 2, the external memory 120 of FPGA and FPGA 102
It is connected, the picture signal of the output of DP signal sources 30 can be stored.But when DP signal sources 30 stop output picture signal, FPGA 102
Data can be read from external memory 120 and be shown in LVDS display screens 40.
It should be noted that verifying system by using DP RX IP shown in Fig. 2, DP RX IP work(can not only be verified
Can, while can also verify the PSR functions of eDP1.3.
As shown in figure 3, DP TX IP verifications system includes：Verification platform 10, DP display screens 50.Wherein, verification platform
10 include：The high-definition digital being connected with FPGA 102 shows sending port DP TX 112, is shown for reading external high-definition digital DP
The test image signal for meeting the picture format of generation is simultaneously sent to DP display screens 50 by the picture format of the support of display screen 50.
In the system, DP TX 112 are connected with DP display screens 50.FPGA 102 can read DP display screens 50 by DP TX 112
The test image signal of generation is simultaneously transferred to DP display screens 50 by the picture format held by DP TX112, so as to be shown by DP
The image detection DP TX IP shown in screen 50.
System is verified by using DP TX IP as shown in Figure 3, is able to verify that DP TX IP functions.
As shown in figure 4, HDMI RX IP verifications system includes：Verification platform 10, HDMI signal sources 60 and LVDS are shown
Screen 40.Wherein, verification platform 10 includes：The high-definition multimedia receiving port HDMI RX114 being connected with FPGA 102, for connecing
Receive the HDMI digital format images of external 60 output of high-definition multimedia HDMI signal sources；Low Voltage Differential Signal LVDS output ports
110, it is connected with FPGA 102, recovers for exporting the HDMI digital format images that FPGA 102 is received according to HDMI RX 114
Picture signal out.During implementation, HDMI signal sources 60 are connected with HDMI RX 114, export HDMI digital format images.FPGA
102 are connected with HDMI RX 114, recover the picture signal of HDMI signal sources 60.110 phase of FPGA 102 and LVDS output ports
Even, LVDS format-pattern signals are exported.LVDS display screens 40 are connected with the LVDS output ports 110 on verification platform 10, can be with
For showing the corresponding image of HDMI picture signals received from HDMI RX114.
System is verified by using HDMI RX IP as shown in Figure 4, is able to verify that HDMI RX IP functions.
As shown in figure 5, HDMI TX IP verifications system includes：Verification platform 10, HDMI display screens 70.Wherein, verify
Platform 10 includes：The high-definition multimedia sending port HDMI TX 116 being connected with FPGA 102, for reading the more matchmakers of external high definition
The test image signal for meeting the picture format of generation is simultaneously sent to HDMI by the picture format of the support of body HDMI display screens 70
Display screen 70.During implementation, HDMI TX 116 are connected with HDMI display screens 70, and FPGA 102 can be read by HDMI TX 116
The test image signal of generation is simultaneously transferred to HDMI by HDMI TX 116 and shown by picture format that HDMI display screens 70 are supported
Screen 70, so as to the image detection HDMI TX IP shown by HDMI display screens 70.
System is verified by using HDMI TX IP as shown in Figure 5, is able to verify that HDMI TX IP functions.
As shown in fig. 6, MIPI TX IP verifications system includes：Verification platform 10, HDMI display screens 70 and MIPI turn
HDMI TX chips 80.Wherein, verification platform 10 includes：The mobile Industry Processor sending port MIPI being connected with FPGA 102
TX 118, for the test image signal of generation to be sent to HDMI display screens.It should be noted that MIPI TX 118 will be surveyed
Examination picture signal is sent to before HDMI display screens, first to turn what HDMI TX chips 80 sent MIPI TX 118 by MIPI
Test image signal is converted to the picture signal of HDMI number formats.During implementation, FPGA 102 is connected with MIPI TX 118.
MIPI TX 118 turn HDMI TX chips 80 with MIPI and are connected.FPGA 102 can send MIPI forms by MIPI TX 118
Picture signal turns HDMI TX chips 80 to MIPI.MIPI turns HDMI TX chips 80 and connects HDMI display 70, HDMI display
70 for showing MIPI images, so as to the image detection MIPI TX IP shown by HDMI display screens 70.
System is verified by using MIPI TX IP as shown in Figure 6, is able to verify that MIPI TX IP functions.
The embodiments of the present invention are for illustration only, do not represent the quality of embodiment.
In the above embodiment of the present invention, all emphasize particularly on different fields to the description of each embodiment, do not have in some embodiment
The part of detailed description may refer to the associated description of other embodiment.
In several embodiments provided herein, it should be understood that disclosed technology contents can pass through others
Mode is realized.Wherein, the apparatus embodiments described above are merely exemplary, such as the division of unit, can be one kind
Division of logic function, can there is an other dividing mode in actual implementation, such as multiple units or component can combine or can
To be integrated into another system or some features can be ignored or does not perform.Another, shown or discussed is mutual
Coupling, direct-coupling or communication connection can be by some interfaces, the INDIRECT COUPLING or communication connection of unit or module,
Can be electrical or other forms.
The unit illustrated as separating component may or may not be physically separate, be shown as unit
Component may or may not be physical location, you can be located at a place or can also be distributed to multiple units
On.Some or all of unit therein can be selected to realize the purpose of this embodiment scheme according to the actual needs.
It the above is only the preferred embodiment of the present invention, it is noted that come for those skilled in the art
It says, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (9)
1. a kind of verification platform, which is characterized in that including：
Programming logic gate array FPGA, for the corresponding intellectual property IP of IC design to high definition digital video interface
Core is designed verification；
Program download interface is connected with the FPGA, for the corresponding program of the IP kernel to be downloaded in the FPGA,
In, the corresponding program of the IP kernel is the IP programs after upgrading；
Program storage is connected between described program download interface and the FPGA, is downloaded for storing by described program
The corresponding program of the IP kernel that interface is downloaded.
2. verification platform according to claim 1, which is characterized in that the verification platform is further included with lower port or port
At least one of group：
High-definition digital shows receiving port DP RX and Low Voltage Differential Signal LVDS output ports；
High-definition digital shows sending port DP TX；
High-definition multimedia receiving port HDMI RX and the Low Voltage Differential Signal LVDS output ports；
High-definition multimedia sending port HDMI TX；
Mobile Industry Processor sending port MIPI TX.
3. verification platform according to claim 2, which is characterized in that
The high-definition digital shows receiving port DP RX, is connected with the FPGA, and DP letters are shown for receiving external high-definition digital
The DP digital format images of number source output；
The Low Voltage Differential Signal LVDS output ports, are connected with the FPGA, for exporting the FPGA according to the DP RX
The picture signal that the digital format images of reception recover.
4. verification platform according to claim 3, which is characterized in that further include：
External memory is connected with the FPGA, for storing the DP digital format images exported by the DP signal sources.
5. verification platform according to claim 2, which is characterized in that
The high-definition digital shows sending port DP TX, is connected with the FPGA, for reading external high-definition digital DP display screens
The test image signal for meeting the picture format of generation is simultaneously sent to the DP display screens by the picture format of support.
6. verification platform according to claim 2, which is characterized in that
The high-definition multimedia receiving port HDMI RX, are connected with the FPGA, for receiving external high-definition multimedia HDMI letters
The HDMI digital format images of number source output；
The Low Voltage Differential Signal LVDS output ports, are connected with the FPGA, for exporting the FPGA according to the HDMI
The picture signal that the HDMI digital format images that RX is received recover.
7. verification platform according to claim 2, which is characterized in that
The high-definition multimedia sending port HDMI TX, are connected with the FPGA, are shown for reading external high-definition multimedia HDMI
The test image signal for meeting the picture format of generation is simultaneously sent to the HDMI display screens by the picture format of display screen support.
8. verification platform according to claim 2, which is characterized in that
The mobile Industry Processor sending port MIPI TX, are connected with the FPGA, for the test image signal that will be generated
It is sent to HDMI display screens.
9. a kind of verification system, which is characterized in that including：Verification platform described in any item of the claim 1 to 8.
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| CN108053784B (en) * | 2017-12-21 | 2020-11-24 | 苏州华兴源创科技股份有限公司 | System and method for testing high-speed image signal source |
| CN108896841A (en) * | 2018-03-19 | 2018-11-27 | 硅谷数模半导体（北京）有限公司 | Test macro, test method and device |
| CN111241602B (en) * | 2018-11-29 | 2023-05-02 | 阿里巴巴集团控股有限公司 | FPGA IP core loading method and device and electronic equipment |
| CN111163276A (en) * | 2019-12-30 | 2020-05-15 | 深圳Tcl新技术有限公司 | Data transmission format determining method, device and system |
| CN111475452B (en) * | 2020-05-06 | 2021-08-06 | 中国人民解放军国防科技大学 | DisplayPort interface speed bridge system for FPGA prototype verification |
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