CN105185739A - Array substrate making method, mask, array substrate and display device - Google Patents
Array substrate making method, mask, array substrate and display device Download PDFInfo
- Publication number
- CN105185739A CN105185739A CN201510369476.7A CN201510369476A CN105185739A CN 105185739 A CN105185739 A CN 105185739A CN 201510369476 A CN201510369476 A CN 201510369476A CN 105185739 A CN105185739 A CN 105185739A
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- substrate
- organic film
- mask plate
- pixel electrode
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- 239000000758 substrate Substances 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims abstract description 41
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 230000005540 biological transmission Effects 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 7
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 4
- 229910004205 SiNX Inorganic materials 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 4
- 239000011651 chromium Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 abstract description 9
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 5
- 238000005516 engineering process Methods 0.000 abstract description 4
- -1 silicon nitride compound Chemical class 0.000 abstract 1
- 238000002834 transmittance Methods 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 20
- 238000010586 diagram Methods 0.000 description 14
- 238000005286 illumination Methods 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000004062 sedimentation Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 235000008429 bread Nutrition 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention relates to the technical field of display, and particularly relates to an array substrate making method, a mask, an array substrate and a display device. The invention aims to solve the problem in the prior art that the array substrate making process is complex. According to an embodiment of the invention, the method comprises the steps as follows: applying a negative organic film to a substrate on which a source and a drain are formed; exposing the substrate coated with the negative organic film through a mask, developing the substrate after exposure, and removing the negative organic film in a via hole area; etching a via hole etching area in the via hole area to form a via hole; and forming an indium tin oxide ITO pixel electrode after the via hole is formed. According to the technical scheme, the negative organic film is applied to the substrate on which the source and the drain are formed. Compared with a technical scheme in which a silicon nitride compound is deposited by PECVD on the substrate on which the source and the drain are formed, the array substrate making technology is simplified, and the aperture ratio and transmittance of the array substrate are improved.
Description
Technical field
The present invention relates to Display Technique field, particularly array base palte make method, mask plate, array base palte and display unit.
Background technology
In TFT-LCD manufacturing, PECVD (the PlasmaEnhancedChemicalVaporDesposition of usual employing costliness, plasma enhanced chemical vapor deposition method) deposited silicon nitride SiNx compound make array base palte, specifically, the gas ionization containing film composed atom is made by microwave or radio frequency etc., be partially formed plasma, then on substrate, deposition obtains the film expected, and need the temperature that substrate is higher, wherein, as shown in Fig. 1 (a), the cross sectional representation of the array base palte utilizing PECVD sedimentation to make, wherein array base palte comprises substrate 1, grid 2, gate insulation layer 3, data wire 4, protective layer 5, pixel electrode 6, can find out that from Fig. 1 (a) surface flatness of array base palte is lower, and pixel electrode and grid line and data wire is overlapping less, the vertical view of array base palte of Fig. 1 (b) for utilizing PECVD sedimentation and making.
In sum, the problem that in currently available technology, the manufacture craft of array base palte is comparatively complicated.
Summary of the invention
The invention provides method, mask plate, array base palte and display unit that a kind of array base palte makes, the problem that the manufacture craft in order to solve array base palte in prior art is comparatively complicated.
Embodiments provide a kind of method that array base palte makes, comprising:
The substrate forming source electrode and drain electrode applies negativity organic film;
By mask plate to the base board to explosure being coated with negativity organic film, and exposure metacoxal plate is developed, remove the negativity organic film of via area;
Via etch region in described via area is etched, forms via hole;
After formation via hole, form tin indium oxide ITO pixel electrode.
Apply negativity organic film on the substrate forming source electrode and drain electrode due to what adopt in embodiments of the present invention, with the Compound Phase ratio adopting PECVD deposited silicon nitride on the substrate forming source electrode and drain electrode, not only simplify the manufacture craft of array base palte, and improve aperture opening ratio and the transmitance of array base palte.
Optionally, to the base board to explosure being coated with negativity organic film, specifically comprise:
By adopting the mask plate with sectional hole patterns and ITO pixel electrode pattern, to the base board to explosure being coated with negativity organic film;
Wherein, the region crossing sectional hole patterns in described mask plate is light tight region, and in described mask plate, the region of ITO pixel electrode pattern is semi-transparent region, and in described mask plate, other region is transmission region.Optionally, form ITO pixel electrode, specifically comprise:
Depositing indium tin oxide ITO;
On the substrate of deposition ITO, coating photoresist;
By having the mask plate of sectional hole patterns and ITO pixel electrode pattern described in adopting, to the base board to explosure of coating photoresist, and the substrate after exposure is developed and etch, formation ITO pixel electrode.Due in the process forming via hole and in the process of formation ITO pixel electrode, by a mask board to explosure, thus reduce the cost of array base palte making, reduce the flow process of technique and the difficulty of technique simultaneously.
Optionally, the via etch region in described via area is etched, specifically comprises:
SiNx dry etching is carried out to the via etch region in described via area;
Substrate after exposure is etched, specifically comprises:
Wet etching is carried out to the substrate after exposure.Optionally, described negativity organic film is resin material.
Optionally, the via etch region in described via area is etched, specifically comprises:
The gate insulation layer in via etch region in described via area is etched.
The invention provides a kind of mask plate for above-mentioned manufacturing method of array base plate, comprising:
Light tight region, semi-transparent region and transmission region;
Wherein, light tight region correspondence crosses sectional hole patterns; The corresponding ITO pixel electrode pattern in semi-transparent region.
Optionally, described light tight region is made up of chromium film, and described semi-transparent region is made up of pellicle.
The invention provides a kind of array base palte, adopt the array base palte that embodiment of the present invention array substrate manufacturing method is made.
The invention provides a kind of display unit, comprising: the above-mentioned array base palte that the embodiment of the present invention provides.
Accompanying drawing explanation
Fig. 1 (a) is the cross sectional representation of array base palte in prior art;
Fig. 1 (b) is the schematic top plan view of array base palte in prior art;
Fig. 2 is the schematic flow sheet of embodiment of the present invention array substrate manufacturing method;
The schematic diagram that Fig. 3 (a) makes for embodiment of the present invention array base palte;
The schematic diagram that Fig. 3 (b) makes for embodiment of the present invention array base palte;
The schematic diagram that Fig. 3 (c) makes for embodiment of the present invention array base palte;
The schematic diagram that Fig. 3 (d) makes for embodiment of the present invention array base palte;
The schematic diagram that Fig. 3 (e) makes for embodiment of the present invention array base palte;
The schematic diagram that Fig. 3 (f) makes for embodiment of the present invention array base palte;
The schematic diagram that Fig. 3 (g) makes for embodiment of the present invention array base palte;
The schematic diagram that Fig. 3 (h) makes for embodiment of the present invention array base palte;
The schematic diagram that Fig. 3 (i) makes for embodiment of the present invention array base palte;
Fig. 4 (a) is the schematic diagram of embodiment of the present invention mask plate;
Fig. 4 (b) is the schematic diagram of embodiment of the present invention mask plate;
Fig. 4 (c) is the schematic diagram of embodiment of the present invention mask plate;
Fig. 5 (a) is the cross sectional representation of embodiment of the present invention array base palte;
Fig. 5 (b) is the vertical view of embodiment of the present invention array base palte;
Fig. 6 is the manufacture method schematic flow sheet of embodiment of the present invention array base palte.
Embodiment
The embodiment of the present invention applies negativity organic film on the substrate forming source electrode and drain electrode; By mask plate to the base board to explosure being coated with negativity organic film, and exposure metacoxal plate is developed, remove the negativity organic film of via area; Via etch region in via area is etched, forms via hole; After formation via hole, form tin indium oxide ITO pixel electrode.This technical scheme is apply negativity organic film on the substrate forming source electrode and drain electrode due to what adopt, with the Compound Phase ratio adopting PECVD deposited silicon nitride on the substrate forming source electrode and drain electrode, not only simplify the manufacture craft of array base palte, and improve aperture opening ratio and the transmitance of array base palte.
Below in conjunction with Figure of description, the embodiment of the present invention is described in further detail.
As shown in Figure 2, the manufacture method of embodiment of the present invention array base palte, comprising:
Step 200, the substrate forming source electrode and drain electrode applies negativity organic film;
Step 201, by mask plate to the base board to explosure being coated with negativity organic film, and develops to exposure metacoxal plate, removes the negativity organic film of via area;
Step 202, etches the via etch region in via area, forms via hole;
Step 203, after formation via hole, forms tin indium oxide ITO pixel electrode.
The manufacture method of array base palte of the present invention is applicable to the making of the array base palte of various display mode.
Be described for Fig. 3 (a), wherein, Fig. 3 (a) is the cross sectional representation of the array base palte after forming source-drain electrode 30.
Substrate after forming source electrode and drain electrode 30 applies negativity organic film, and a kind of material of optional negativity organic film is resin, obtains the substrate as shown in Fig. 3 (b).
It should be noted that, the substrate forming source electrode and drain electrode 30 applies negativity organic film, is that the upper surface of substrate is all applied negativity organic film, and makes the upper surface of substrate smooth, as shown in Fig. 3 (b).
Then, by having the mask plate of sectional hole patterns to the base board to explosure shown in Fig. 3 (b), then can not be dissolved in developing process because negativity organic film is subject to illumination, then do not dissolved in developing process by the negativity organic film of illumination, therefore the region crossing sectional hole patterns in mask plate is light tight region, region beyond via area is transmission region, wherein, there is the mask plate of sectional hole patterns can be the mask plate only having sectional hole patterns 40, wherein 41 is quartz glass, as shown in Fig. 4 (a), also can for comprising the mask plate of sectional hole patterns and pixel electrode pattern as shown in Fig. 4 (b), wherein the mask plate via hole part of Fig. 4 (b) is covered by chromium film, namely sectional hole patterns 40 is crossed for light tight region, pixel electrode part is covered by pellicle, for semi-transparent region 42.
Wherein, the via area on substrate corresponds to the region of the mistake sectional hole patterns on mask plate, and on substrate, the region at pixel electrode place corresponds to the region of pixel electrode pattern on mask plate.
Be described for Fig. 4 (b) mask plate, when light transmission as the array base palte of the mask plate of Fig. 4 (b) to such as Fig. 3 (b) carries out illumination, and to array base palte development after illumination, obtain the substrate as shown in Fig. 3 (c), wherein 31 and 32 is via area.
After obtaining the substrate as shown in Fig. 3 (c), 31 is via etch region, optionally, the gate insulation layer in via etch region is etched, exposes grid, contact with pixel electrode to make grid, thus formation via hole, as shown in Fig. 3 (d), wherein, the lithographic method that gate insulator layer adopts in embodiments of the present invention is SiNx dry etching.
On the array base palte forming via hole, PECVD is adopted to deposit ITO, obtain the substrate as shown in Fig. 3 (e), the ITO of deposition applies one deck photoresist, as shown in Fig. 3 (f), dissolved because photoresist develops after illumination, and the photoresist be not irradiated by light is not after development by colloidal sol, therefore, obtain the substrate as shown in Fig. 3 (g) after exposure and development, specifically, in exposure process, the mask plate adopted can for the mask plate such as shown in Fig. 4 (b), also can for the mask plate only with pixel electrode pattern such as shown in Fig. 4 (c), when adopting the mask plate as shown in Fig. 4 (b), double exposure process can adopt same mask plate, not only save a mask plate, reduce the capacity burden of exposure machine simultaneously, and reduce cost.
Then, etch ITO not covered by photoresist, obtain the substrate as shown in Fig. 3 (h), the method wherein etching adopted etching to ITO not covered by photoresist is wet etching.
Finally, photoresist is separated with array base palte, forms pixel electrode, obtain the final array base palte needed, as shown in Fig. 3 (i).
For the array base palte in Fig. 1 (a), array substrate manufacturing method of the present invention is described, after the array base palte in Fig. 1 (a) forms source electrode and drain electrode, adopt the manufacture method of the array base palte shown in Fig. 2, obtain the array base palte as shown in Fig. 5 (a), by comparison diagram 5 (a) and Fig. 1 (a), can find out, the array base palte surface adopting embodiment of the present invention manufacture method to obtain is comparatively smooth, its vertical view is as shown in Fig. 5 (b), wherein Fig. 1 (b) is the vertical view adopting the manufacture method of the array base palte of prior art to obtain array base palte, can be found out by comparison diagram 5 (b) and Fig. 1 (b), by adopting the manufacture method of the array base palte of the embodiment of the present invention, not only reduce cost, and improve aperture opening ratio and the transmitance of array base palte.
As shown in Figure 6, the manufacture method of embodiment of the present invention array base palte, comprising:
Step 600, the substrate forming source electrode and drain electrode applies negativity organic film.
Step 601, by adopting the mask plate with sectional hole patterns and pixel electrode pattern, exposing the array base palte of coating negativity organic film, and carrying out after exposure developing and etching, forming via hole.
Step 602, on the substrate forming via hole, depositing indium tin oxide ITO.
Step 603, coating photoresist, by having the mask plate of sectional hole patterns and pixel electrode pattern described in adopting, to the base board to explosure of coating photoresist, and develops to the substrate after exposure and etch, and formation ITO pixel electrode, this flow process terminates.
As shown in Fig. 4 (b), a kind of mask plate for above-mentioned array substrate manufacturing method of the embodiment of the present invention, comprising:
Light tight region 40, semi-transparent region 42 and transmission region 41;
Wherein, the pattern of the corresponding via hole in light tight region; The pattern of the corresponding ITO pixel electrode in semi-transparent region.
Optionally, light tight region 42 is made up of chromium film, and semi-transparent region 41 is made up of pellicle.
Based on same inventive concept, embodiments provide a kind of array base palte.Because this array base palte corresponds to the manufacture method of embodiment of the present invention array base palte, therefore the enforcement of this array base palte see the enforcement of said method, can repeat part and repeats no more.
Based on same inventive concept, embodiments provide a kind of display unit, comprise the above-mentioned arraying bread board that the embodiment of the present invention provides.This display unit can be: any product or parts with Presentation Function such as mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.The principle of dealing with problems due to this display unit is similar to display floater, and therefore the enforcement of this display unit see the enforcement of display floater, can repeat part and repeat no more.
It can be seen from the above: the embodiment of the present invention applies negativity organic film on the substrate forming source electrode and drain electrode; By mask plate to the base board to explosure being coated with negativity organic film, and exposure metacoxal plate is developed, remove the negativity organic film of via area; Via etch region in via area is etched, forms via hole; After formation via hole, form tin indium oxide ITO pixel electrode.This technical scheme is apply negativity organic film on the substrate forming source electrode and drain electrode due to what adopt, with the Compound Phase ratio adopting PECVD deposited silicon nitride on the substrate forming source electrode and drain electrode, not only simplify the manufacture craft of array base palte, and improve aperture opening ratio and the transmitance of array base palte.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. a method for array base palte making, it is characterized in that, the method comprises:
The substrate forming source electrode and drain electrode applies negativity organic film;
By mask plate to the base board to explosure being coated with negativity organic film, and exposure metacoxal plate is developed, remove the negativity organic film of via area;
Via etch region in described via area is etched, forms via hole;
After formation via hole, form tin indium oxide ITO pixel electrode.
2. the method for claim 1, is characterized in that, to the base board to explosure being coated with negativity organic film, specifically comprises:
By adopting the mask plate with sectional hole patterns and ITO pixel electrode pattern, to the base board to explosure being coated with negativity organic film;
Wherein, the region crossing sectional hole patterns in described mask plate is light tight region, and in described mask plate, the region of ITO pixel electrode pattern is semi-transparent region, and in described mask plate, other region is transmission region.
3. method as claimed in claim 2, is characterized in that, forms ITO pixel electrode, specifically comprises:
Depositing indium tin oxide ITO;
On the substrate of deposition ITO, coating photoresist;
By having the mask plate of sectional hole patterns and ITO pixel electrode pattern described in adopting, to the base board to explosure of coating photoresist, and the substrate after exposure is developed and etch, formation ITO pixel electrode.
4. method as claimed in claim 3, is characterized in that, etch, specifically comprise the via etch region in described via area:
SiNx dry etching is carried out to the via etch region in described via area;
Substrate after exposure is etched, specifically comprises:
Wet etching is carried out to the substrate after exposure.
5. the method as described in as arbitrary in claims 1 to 3, it is characterized in that, described negativity organic film is resin material.
6. the method for claim 1, is characterized in that, etches, specifically comprise the via etch region in described via area:
The gate insulation layer in via etch region in described via area is etched.
7., for a mask plate for described method arbitrary in claim 1 ~ 6, it is characterized in that, comprising:
Light tight region, semi-transparent region and transmission region;
Wherein, light tight region correspondence crosses sectional hole patterns; The corresponding ITO pixel electrode pattern in semi-transparent region.
8. mask plate as claimed in claim 7, it is characterized in that, described light tight region is made up of chromium film, and described semi-transparent region is made up of pellicle.
9. an array base palte, is characterized in that, adopts the arbitrary described method of claim 1 ~ 6 to make.
10. a display unit, is characterized in that, comprising: array base palte according to claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510369476.7A CN105185739A (en) | 2015-06-26 | 2015-06-26 | Array substrate making method, mask, array substrate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510369476.7A CN105185739A (en) | 2015-06-26 | 2015-06-26 | Array substrate making method, mask, array substrate and display device |
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| Publication Number | Publication Date |
|---|---|
| CN105185739A true CN105185739A (en) | 2015-12-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510369476.7A Pending CN105185739A (en) | 2015-06-26 | 2015-06-26 | Array substrate making method, mask, array substrate and display device |
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| CN101419366A (en) * | 2007-10-24 | 2009-04-29 | 精工爱普生株式会社 | Liquid crystal device and electric equipment with the same |
| US20090111199A1 (en) * | 2007-10-30 | 2009-04-30 | Chunghwa Picture Tubes, Ltd. | Method of manufacturing flat panel display |
| CN102629046A (en) * | 2011-06-29 | 2012-08-08 | 北京京东方光电科技有限公司 | Array substrate, manufacturing method of array substrate and liquid crystal display device |
| CN103489873A (en) * | 2013-09-18 | 2014-01-01 | 京东方科技集团股份有限公司 | Array substrate, manufacture method thereof and display device |
| CN104062794A (en) * | 2014-06-10 | 2014-09-24 | 深圳市华星光电技术有限公司 | Mask plate, manufacturing method of ultraviolet mask plate and manufacturing method of array substrate |
-
2015
- 2015-06-26 CN CN201510369476.7A patent/CN105185739A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101276103A (en) * | 2007-03-28 | 2008-10-01 | 爱普生映像元器件有限公司 | Liquid crystal device, method of manufacturing liquid crystal device, and electronic apparatus |
| CN101419366A (en) * | 2007-10-24 | 2009-04-29 | 精工爱普生株式会社 | Liquid crystal device and electric equipment with the same |
| US20090111199A1 (en) * | 2007-10-30 | 2009-04-30 | Chunghwa Picture Tubes, Ltd. | Method of manufacturing flat panel display |
| CN102629046A (en) * | 2011-06-29 | 2012-08-08 | 北京京东方光电科技有限公司 | Array substrate, manufacturing method of array substrate and liquid crystal display device |
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Application publication date: 20151223 |
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