CN105162475A - FPGA (Field Programmable Gate Array) based parameterized multi-standard decoder with high throughput rate - Google Patents
FPGA (Field Programmable Gate Array) based parameterized multi-standard decoder with high throughput rate Download PDFInfo
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Abstract
The invention provides an FPGA (Field Programmable Gate Array) based parameterized multi-standard decoder with a high throughput rate. The FPGA based parameterized multi-standard decoder with the high throughput rate comprises a codeword converting unit, a branch metric computing unit, a reconfigurable branch metric network, a radix-4 ACS (Add-Compare-Select) unit and a reconfigurable path metric network. Aiming at multiple communication protocols with 3-9 changeable constraint degrees and a 1/2 or 1/3 code rate, such as GPRS (General Packet Radio Service), WiMAX (Worldwide Interoperability for Microwave Access), LTE(Long Term Evolution), CDMA (Code Division Multiple Access) and 3G (The Third Generation Telecommunication), the provided FPGA based parameterized multi-standard decoder with the high throughput rate can realize decoding work of convolutional codes in the protocols. The decoder which realizes the working frequency up to 270.5 MHz and the throughput rate up to 541 Mbps on a Xilinx XC7VX485T platform is currently an FPGA platform based Viterbi decoder with the highest decoding rate.
Description
Technical field
The present invention relates to wireless communication technology field, specifically a kind of parametrization many standards high-throughput decoder based on FPGA.
Background technology
The birth of the innovation of making rapid progress along with the communication technology and various wireless device, communication standard more and more presents diversified feature, this just determines the adaptive ability that mobile terminal needs to possess for multiple network, is convenient to user under corresponding communication standard, realizes communication.The parameter that multi-mode wireless communications system only needs user to provide suitable, system just can just can real-time change structure according to parameter, realizes wherein certain function, to adapt to the communication requirement of contemporary communication standards.The multi-functional scheme of multi-mode only comprises a multipurpose multifunctional operating system, does not need extra structural design, switches in real time, thus effectively extend the multifunctionality of wireless device by the multiple function of less logic realization.
In various wireless communication standard now, Viterbi algorithm is due to the characteristic of its low complex degree, so it is widely used in the decoding algorithm of convolution code in digital communication system, and achieves good decoding performance.The decode procedure of Viterbi algorithm is L × R symbol of decoding input, recovers L bit during coding input.In grid chart, state transition repeats from left to right, and the migration number of times altogether carried out equals the length L of information bit.As can be seen from decoding procedure above, Viterbi decoding comprises two calculation procedures: forward process and reverse procedure.When forward process, a path metric (pathmetric, PM) is set for possible path each in examination network.In each moment, the migration between two states can calculate a point value metric (branchmetric, BM), by adding that BM value carrys out the PM value of more new route.In each state, only have minimum PM value could retain and be sent in next iteration.For each state, can be calculated BM value by Gabi selection (add-compare-select, ACS) operation and be selected suitable PM value, result of calculation forms up-to-date PM value and survival bit (survivedbits, SB).After forward direction computational process produces all grids, reverse procedure can start to carry out backtracking and find maximum likelihood path, and the SB in maximum likelihood path is exactly decoding bit.
Because two adjacent moment every in grid chart also exist dependence, the markoff process of traditional Viterbi decoding algorithm needs grid chart to traverse last moment from first moment.Meanwhile, reverse procedure also must wait until that forward process computation just can carry out after complete.Which has limited the concurrency of Viterbi algorithm.
Existing Chinese patent " heterogeneous Gabi selection forward back Viterbi decoder " (application number: 201110087983.3) point out, in the reverse procedure of Viterbi decoding, after backtracking one segment distance, all survivor paths will converge in a state, claim this stage to be the backtracking stage.Then continue backtracking from this state converged, obtain final coding sequence, this stage is referred to as decode stage.Like this, just the overall process of Viterbi decoding is divided into three phases: forward calculation stage, backtracking stage and decode stage, process as shown in Figure 1, claims such algorithm to be 3 Viterbi decoding algorithms.3 Viterbi decoding algorithm reverse procedures are divided into two stages, namely recall stage and decode stage.When forward direction calculation stages terminates, the backtracking stage starts to find merging phase, and this merging phase is exactly the initial state of decode stage.
Many standards Viterbi decoder needs to support code check, constraint degree, coding polynomial, block the restructural parameters such as length.By extracting the parameter information in communication standard, and provide it to the Viterbi decoder just decoding function of realization to multiple communication standard.Table 1 lists and uses Viterbi algorithm as the communication standard of decoding algorithm and relevant parameter thereof.Can see from table, general communication standard code check all changes between 1/2 and 1/3, and constraint degree changes between 5-9.The corresponding coding polynomial of each communication standard, produces corresponding code-word symbol during for encoding.For various criterion, corresponding grid chart is different.The status number of grid chart equals 2
k-1, wherein K is communication standard constraint degree; In communication standard, convolution coding multinomial is different, and in corresponding grid chart, its coding exports also different; The calculating of branch metric also can change along with the change of code check to some extent.
The substandard channel error correction encoding of table 1 different wireless communication and parameter thereof
Due to the popularity of application, the Viterbi decoder in recent years based on FPGA becomes study hotspot.According to the algorithm types realized and flexibility, related work can be divided three classes, respectively: base 2 fixed structure Viterbi decoder, base standard Viterbi more than 2 decoder [1-10], base 4 fixed structure Viterbi decoder.The each node of base 2 decoder has two inputs, completes the Gabi selection operation of two branch metrics and two path metrics.The each node of base 4 decoder has 4 inputs, completes the Gabi selection operation of 4 branch metrics and 4 path metrics.
The function that base 2 fixed structure Viterbi decoder realizes is fixed, and can only realize the channel decoding of a certain communication standard.This class research mainly concentrates on low-power consumption, high-throughput optimization aspect.(Ablock-basedparalleldecodingarchitectureforconvolutional codes [C] the .5thInternationalICSTConferenceonCommunicationsandNetwor kinginChina such as ZhangYu, Beijing, China, Aug.25-27,2010,1-4.) propose a kind of block-wise decoding strategy, by multiple Viterbi sub-decoder concurrence performance, can, to multiframe decoding simultaneously, the performance of decoder be made to reach 1.2Gbps.But the function that such decoder realizes is fixed, and can only realize the channel decoding of a certain communication standard.
Base standard Viterbi more than 2 decoder is identical with the algorithm that base 2 fixed structure Viterbi decoder realizes, but the structure of decoder can realize several functions, and the switching at runtime of several functions can be realized by real-time parameter adjustment, corresponding channel decoding can be realized for different communication standards.(the CavallaroJ.R. such as Cavallaro, VayaM..Viturbo:areconfigurablearchitectureforViterbiandt urbodecoding [C] .IEEEInternationalConferenceonAcoustics, Speech, andSignalProcessing, HongKong, China, April6-10, 2003, vol.2, 497-500) and (MangeshKKunchamwar such as Mangesh, DurgaPPrasad, et.al.Applicationspecificinstructionacceleratorformultis tandardViterbiandTurbodecoding [C] .39thInternationalConferenceonParallelProcessingWorkshop s, SanDiego, USA, Sept.13-16, 2010, on FPGA and ASIC, 34-43.) achieve the combination of turbo decoder and base 2Viterbi decoder respectively.The Viterbi decoder of Cavallaro design can support the constraint degree of 3 to 9, and 1/2 and 1/3 code check, the throughput of realization is 60.5Mbps.(the NiktashA. such as Niktash, PariziH.T., BagherzadehN..AMulti-StandardViterbiDecoderforMobileAppl icationsUsingaReconfigurableArchitecture [C] .IEEE64thVehicularTechnologyConference, Montreal, Canada, Sept.25-28,2006,1-5) on MorphoSys, achieve Viterbi decoder, can support 7 and 9 two kind of constraint degree, throughput is 27Mbps.The people such as Batcha (NiktashA., PariziH.T., BagherzadehN..AMulti-StandardViterbiDecoderforMobileAppl icationsUsingaReconfigurableArchitecture [C] .IEEE64thVehicularTechnologyConference, Montreal, Canada, Sept.25-28,2006, on FPGA, 1-5.) achieve the Viterbi decoder of 5 and 7 two kind of constraint degree, its throughput is 150Mbps, is that current FPGA realizes the fastest many standards Viterbi decoder of decoding speed.Although base standard Viterbi more than 2 decoder has good flexibility, its throughput is inadequate, can not meet some communication system at present, the 200Mbps decoding rate requirement of such as UWB.
3rd class is base 4 fixed structure Viterbi decoder.Relative to base 2Viterbi decoder, its performance is higher, but complexity slightly increases.When frequency is identical, the throughput of base 4 is twices of base 2.The people such as Santhi (SanthiM., LakshminarayananG., SundaramR., BalachanderN..Synchronouspipelinedtwo-stageradix-4200Mbp sMB-OFDMUWBViterbidecoderonFPGA [C] .InternationalSoCDesignConference, Busan, Korea, Nov.22-24, 2009, in FPGA platform, 468-471.) achieve constraint degree is 7, code check is the base 4Viterbi decoder of 1/3, decoder adopts two-stage flowing water ping-pong structure, support the decoding simultaneously of two frames, throughput is 274Mbps, it is the base 4Viterbi decoder of the most high-throughput that current FPGA platform realizes.Chinese patent " heterogeneous Gabi selection forward back Viterbi decoder " (application number: the base 4 fixed structure Viterbi decoder 201110087983.3) achieving forward back, proposes the method for forward back, decrease decoding delay.Sung-WooChoi (Sung-WooChoi, Kyu-MinKang, andSang-SungChoi.ATwo-stageRadix-4ViterbiDecoderforMulti bandOFDMUWBSystem [J] .ETRIJournal, 2008, 30 (6) :) and (Xin-RuLee such as Xin-RuLee, Hsie-ChiaChang, Chen-YiLee.Alow-powerradix-4ViterbidecoderbasedonDCVSPGp ulsedlatchwithsharingtechnique [C] .IEEEAsiaPacificConferenceonCircuitsandSystems, KualaLumpur, Malaysia, Dec.6-9, 2010, on ASIC, 1203-1206) achieve base 4 decoder, but its structure is also fixing.This kind of decoder can only carry out decoding for a certain communication standard, can not the communication requirement of compatible multiple communication standard, and flexibility is not enough.
Summary of the invention
The invention provides a kind of under many standard traffics environment, the parametrization many standards high-throughput decoder based on FPGA of instantaneous handoff protocol, obtaining good throughput simultaneously, can there is very strong flexibility, meet the decoding demand of multiple communication standard.
Based on parametrization many standards high-throughput decoder of FPGA, comprise code conversion unit, branch metric calculation unit, restructural branch metric network, base 4 acs unit, normalization judging unit, reconfigurable path tolerance network and traceback decoding unit, control unit.
Described code conversion unit, for receiving enter code word, and changes into signless integer by code word, then the signless integer of conversion is input to branch metric calculation unit;
Described branch metric calculation unit, the signless integer for transforming according to enter code word calculates the metric of each branch in base 4 grid chart;
Described restructural branch metric network, sends into corresponding base 4 acs unit respectively for choosing corresponding branched measurement value in the branched measurement value that often kind from described branch metric calculation unit calculating is possible;
Described base 4 acs unit, for being operated by Gabi selection, being calculated the path metric made new advances and being sent into normalization judging unit, and survival bit information is sent into traceback decoding unit;
Described normalization judging unit, judges whether the path metric value highest order of all inputs is 1, if be 1, then judges that path metric needs normalization, and the path metric value after normalization sends into reconfigurable path tolerance network; If be 0, then direct reconfigurable path of being sent into by path metric value measures network;
Described reconfigurable path tolerance network, for according to the adaptively selected suitable interconnecting relation of the change of constraint degree, then sends into new path metric value in base 4 acs unit and carries out iterative computation;
Described traceback decoding unit, for carrying out 3 back-track algorithms according to the survival bit information received, recalling and decoded operation grid, finally exporting decoding bit;
Described control unit, is connected with code conversion unit, branch metric calculation unit, base 4 acs unit, traceback decoding unit respectively, and the flowing water being responsible for 3 algorithms in whole decoder controls.
As above based on parametrization many standards high-throughput decoder of FPGA, described branch metric calculation unit supports the branch metric calculation unit of multi code Rate of Chinese character, the codeword information quantity of its input and the branch metric quantity of output can change according to code check R, when code check R is 1/2, the codeword information of input is two 3 bit codewords, altogether can form 4 base 2 branch metrics; When code check R is 1/3, the codeword information of input is three 3 bit codewords, altogether can form 8 base 2 branch metrics, when code check R is 1/2, always has 16 kinds of possible branch metrics; When code check is 1/3, always have 64 kinds of possible branch metrics.
As above based on parametrization many standards high-throughput decoder of FPGA, described restructural branch metric network can form corresponding mapping relations according to the change of constraint degree K, described restructural branch metric network has fixing interconnect architecture for often kind of constraint degree K, various code rate R and constraint degree K forms permutation and combination, for each Combination Design fixed structure, then selector is utilized to be integrated by these fixed structures, after receiving constraint degree K and code check R, restructural branch metric network utilisation selector and corresponding parameter select suitable interconnect architecture.
As above based on parametrization many standards high-throughput decoder of FPGA, described base 4 acs unit comprises a large amount of Gabi selection calculation module, and for calculating Gabi selection operation, Gabi selection calculation module number is relevant to constraint degree K, suppose that constraint degree is K, then Gabi selection calculation module number is 2
k-1, the maximum constrained degree of decoder support is 9, and Gabi selection calculation module maximum quantity is 256, and when after input constraint degree K, decoder selects front 2 in 256 Gabi selection calculation modules
k-1individual, the Gabi selection calculation module that shielding is remaining, thus realize the structure changing described base 4 acs unit 4 according to the change of constraint degree K.
As above based on parametrization many standards high-throughput decoder of FPGA, described reconfigurable path tolerance network is for connecting the path metric value of continuous two each states of timing node, suitable interconnect architecture is selected according to the change of constraint degree K, realize the interconnecting relation between base 4 grid adjacent moment state, concrete, after described reconfigurable path tolerance network reception constraint degree K, the path metric value of exact connect ion adjacent moment, its annexation is as follows: the input path tolerance of 4i state, 4i+1 state, 4i+2 state, 4i+3 state equals i state, i+2
k-3state, i+2
k-2state, i+3 × 2
k-3the outgoing route tolerance of state.
As above based on parametrization many standards high-throughput decoder of FPGA, described base 4 acs unit utilizes four adders 4 path metric values inputted and score value metric to be added, and then 4 addition results is sent into 6 comparators and compares between two; The result compared is sent into and selects logic, obtain survival bit information, then send into traceback decoding unit, utilize and select logic in 4 addition results, select maximum to export as last path metric.
The parametrization many standards high-throughput decoder based on FPGA that the present invention proposes, parameter configuration can be carried out when decoder works, decoder architecture can be changed online according to the parameter of user's setting, between multiple communication standard, realize switching at runtime, effectively realize the work decoding of respective communication standard; The convolution code decoding of many standards can be supported, decoder can realize 3-9 variable bound length, support 1/2,1/3 two kind of variable bit rate and block arbitrarily the error-correcting decoding of length, good error performance is all achieved to the multiple communication standard such as GPRS, WiMAX, LTE, CDMA, 3G, the decoding demand of multiple communication standard can be met; Have employed without symbol metric calculation and the design of new acs unit, substantially reduce critical path, and the mode adopting normalization decision logic to be separated realization significantly improves the operation of decoder frequently.
Accompanying drawing explanation
Fig. 1 is the principle schematic of existing 3 backtracking Viterbi algorithms;
Fig. 2 is the structural representation of the parametrization many standards high-throughput decoder that the present invention is based on FPGA; In figure: 1-code conversion unit, 2-branch metric calculation unit, 3-restructural branch metric network, 4-base 4 acs unit, 5-normalization judging unit, 6-reconfigurable path tolerance network, 7-traceback decoding unit, 8-control unit;
Fig. 3 is the structure chart of base 4 branch metric unit in the present invention, base 2 branch metric wherein dividing Fig. 3 (1) to represent code check 1/2 generates figure, Fig. 3 (2) represents that base 2 branch metric of code check 1/3 generates figure, Fig. 3 (3) represents that base 4 branch metric of code check 1/2 generates figure, and ((4) represent that base 4 branch metric of code check 1/3 generates figure to Fig. 3;
Fig. 4 is the structure chart of restructural branch metric network in the present invention;
Fig. 5 is the structure chart of reconfigurable path tolerance network in the present invention, and wherein Fig. 5 (1) represents the sub-grid tolerance network structure of base 4, and Fig. 5 (2) represents the overall structure figure of reconfigurable path tolerance network;
Fig. 6 is the structure chart without base 4 acs unit of symbolic operation in the present invention, wherein component (1) represents the structure chart of base 4 acs unit of the present invention's design, (2) represent traditional and have sign comparator structure chart, (4) represent the present invention's design without sign comparator structure chart;
Fig. 7 is the structure chart of normalization judging unit in the present invention;
Fig. 8 is 3 decoding algorithm pipeline organization figure in the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the present invention, the technical scheme in the present invention is clearly and completely described.
Figure 2 shows that the structural representation of the parametrization many standards high-throughput decoder that the present invention is based on FPGA, described parametrization many standards high-throughput decoder based on FPGA comprises 8 parts: code conversion unit 1, branch metric calculation unit 2 (BMU), restructural branch metric network 3 (CBMN), base 4 acs unit 4 (R4ACSU), normalization judging unit 5 (NDU), reconfigurable path tolerance network 6 (CPMN) and traceback decoding unit 7 (TDU), control unit 8.
Described code conversion unit 1, for receiving enter code word, and changes into signless integer by code word, then the signless integer of conversion is input to branch metric calculation unit 2; Concrete, described code conversion unit 1 realizes quantizing without symbol, is added quantized amplitudes, signed code word and code word complement code are changed into signless integer.Because decoder adopts 3 bit quantizations, so the expression scope of code word and code word complement code is-4 to 3, quantized amplitudes is 4.In order to convert it into signless integer, the present invention, in code conversion unit, first calculates the complement code of each code word, then code word and code word complement code is added quantized amplitudes simultaneously, converts it into the integer between 0 to 7.The object that code word transforms without symbol, can directly by comparing without symbol when carrying out Gabi selection calculation, thus simplify Gabi selection and realize logic, reduces critical path delay, improve frequency.
Described branch metric calculation unit 2, the signless integer for transforming according to enter code word calculates the metric of each branch in base 4 grid chart;
Described restructural branch metric network 3, sends into corresponding base 4 acs unit 4 respectively for choosing corresponding branched measurement value in the branched measurement value that often kind from described branch metric calculation unit 2 calculating is possible;
Described base 4 acs unit 4, is operated by Gabi selection, calculates the path metric made new advances and is sent into normalization judging unit 5, and survival bit information is sent into traceback decoding unit 7;
Described normalization judging unit 5, by judging whether the path metric value highest order of all inputs is 1, if be 1, then judges that path metric needs normalization, the path metric value after normalization sends into reconfigurable path tolerance network 6; If be 0, then direct reconfigurable path of being sent into by path metric value measures network 6;
Described reconfigurable path tolerance network 6 according to the adaptively selected suitable interconnecting relation of the change of constraint degree, then carries out iterative computation by new path metric value feeding base 4 acs unit 4;
Described traceback decoding unit 7, for carrying out 3 back-track algorithms according to the survival bit information received, recalling and decoded operation grid, finally exporting decoding bit;
Described control unit 8, is connected with code conversion unit 1, branch metric calculation unit 2, base 4 acs unit 4, traceback decoding unit 7 respectively, and the flowing water being responsible for 3 algorithms in whole decoder controls.
The parametrization many standards high-throughput decoder that the present invention is based on FPGA adopts configuration register to be used for depositing configuration parameter, and described configuration parameter comprises constraint degree K, code check R and blocks length L.When real-time restructural, upgrade the parameter of configuration register, decoder is according to new parameter Real-time Reconstruction decoder architecture.The present invention adopts the mode of Configuration Online to realize Real-time Reconstruction decoder architecture.First, decoder, when starting, first reads external parameter value, and parameter transmission is inner to decoder, and carry out assignment to corresponding parameter, decoder then selects corresponding selector option according to corresponding parameter value, thus obtains corresponding decoder architecture.Because Configuration Online mode reads in real time when protocol switching, the design logic of decoder remains unchanged simultaneously, so the switch operating of agreement does not need hardware logic to carry out secondary comprehension, improves operating efficiency.
Concrete parameter configuration is as follows: code check R is used for reconstructing described branch metric calculation unit 2 and restructural branch metric network 3.Exampleization 64 branch metric calculation unit 2 altogether in decoder, decoder selects wherein 4 in 64 branch metric calculation unit 2
rindividual; And select the 3rd code word in branch metric calculation according to R; Constraint degree K is used for reconstructing restructural branch metric network 3, base 4 acs unit 4, normalization judging unit 5, reconfigurable path tolerance network 6.Decoder reconstructs the interconnect architecture of restructural branch metric network 3 according to code check R and constraint degree K, reconstructs the interconnect architecture of reconfigurable path tolerance network 6 according to constraint degree K.Exampleization 256 base 4 acs units 4 altogether in decoder, decoder according to code check R select in 256 base 4 acs units 4 wherein 2
k-1individual.Decoder adopts the mode of blocking decoding, block length to decide according to the length L that blocks of input, control unit 8 and traceback decoding unit 7 is sent into when real-time restructural, flowing water realizes 3 decoding algorithms blocking length L, when constraint degree is different, length L configuration is blocked in utilization, effectively can realize the compromise of decoding precision and decoding latency.
Figure 3 shows that the structural representation of base 4 branch metric unit of the present invention.The signless integer that described branch metric calculation unit 2 transforms according to enter code word calculates each branched measurement value in base 4 grid chart, can support multi code Rate of Chinese character.The change of code check can change the quantity of the branch metric of input in branch metric calculation unit 2.When code check is 1/2, always have 4
2=16 kinds of possible branch metrics; When code check is 1/3, altogether generate 4
3branch metric possible in=64.Because certain branched measurement value of a timing node in base 4 grid is continuous two timing node corresponding trellis branch metric sums in base 2 grid, so when the calculating of branch metric, obtain the branched measurement value of corresponding two timing nodes under first calculating base 2 state.As shown in Fig. 3 (1) (2), when code check is 1/2, the codeword information of input is two 3 bit codewords, altogether can form 4 base 2 branch metrics; When code check is 1/3, the codeword information of input is three 3 bit codewords, altogether can form 8 base 2 branch metrics.Usually, when input bit is 0, measures as code word itself, represent with Sx0; When input bit is 1, measures as code word complement code, represent with Sx1.The all possible branch metric iterated to for t-2 time in base 4Viterbi algorithm between t iteration can be generated by the set of the cartesian product iterating to the branch metric λ n-1 × λ n between t iteration in base 2Viterbi algorithm for t-1 time.As shown in Fig. 3 (3) (4), when code check is 1/2, always have 4
2=16 kinds of possible branch metrics; When code check is 1/3, altogether generate 4
3branch metric possible in=64.64 branch metric calculation modules are set in decoder, centralized calculation branch metric, reduce the utilization of resource, improve area efficiency.The branch metric of centralized calculation can utilize restructural branch metric network 3 to be distributed in suitable base 4 acs unit 4 according to constraint degree change.
As shown in Figure 2, the structure of described branch metric calculation unit 2 is made up of two selectors and three adders, can change change structure according to code check.Selector selects corresponding enter code word quantity according to code check R.If code check is 1/2, then select two enter code words; If code check is 1/3, then select three enter code words.Then, the input of the enter code word of two or three signless integer forms is added by adder, obtains the branch metric of base 2; Again by the structure of Fig. 3 (3) (4), calculate corresponding base 4 branch metric.Described branch metric calculation unit 2 have employed flowing structure, and wherein t-1 moment and t two base 2 branch metrics calculate simultaneously.It is noted herein that because decoder adopts soft I/O mode, code word is 3 bits, so base 2 branch metric is 5 bits, base 4 branch metric is 6 bits.
Figure 4 shows that the structural representation of restructural branch metric network 3 of the present invention, described restructural branch metric network 3 is for being distributed in each base 4 acs unit 4 by the branch metric of centralized calculation, can support multi code Rate of Chinese character and multiple constraint degree, the change of code check R and constraint degree K makes the mapping relations of branch metric and Gabi selection calculation module change.Described restructural branch metric network 3 can form corresponding mapping relations according to the change of code check R and constraint degree K.Various code rate R and constraint degree K forms permutation and combination, for each Combination Design fixed structure, then utilizes selector to be integrated by these fixed structures.After receiving constraint degree K and code check R, restructural branch metric network 3 utilizes selector and corresponding parameter to select suitable interconnect architecture.As shown in Figure 4, be respectively 1/2 and 1/3 time, constraint degree 5,7 at code check, 9 have corresponding fixing interconnect architecture.Because restructural branch metric network 3 adopts flowing water to realize, make this part logic can not become logic bottleneck.
Described base 4 acs unit 4 is for path metrics.Can support multiple constraint degree, the change of constraint degree K can cause the change of Gabi selection calculation module number in base 4 acs unit 4.Given constraint degree is K, and base 4 acs unit 4 always has 2
k-1individual base 4 Gabi selection calculation module.The maximum constrained degree of decoder support is 9, so decoder example 256 Gabi selection calculation modules altogether.After constraint degree K inputs, decoder selects 2 above in 256 base 4 Gabi selection calculation modules
k-1individual, shield remaining base 4 Gabi selection calculation module.So just can according to the quantity of the change of constraint degree K real-time restructural Gabi selection calculation module.
Figure 5 shows that the structural representation of reconfigurable path of the present invention tolerance network 6, described reconfigurable path tolerance network 6 is for connecting the path metric value of continuous two each states of timing node, can support multiple constraint degree, constraint degree K change mainly causes described reconfigurable path to measure the interconnecting relation of path metric between adjacent two states in network 6.Described reconfigurable path tolerance network 6 can select suitable interconnect architecture according to the change of constraint degree K, realizes the interconnecting relation between base 4 grid chart adjacent moment state.Interconnecting relation between the connected adjacent moment state in base 2 grid is as shown in Fig. 5 (1), and the input path tolerance of 2i state and 2i+1 state equals i state and i+2
k-2the outgoing route tolerance of state.Because base 4 sub-grid of adjacent moment can be made up of base 2 sub-grid in continuous two moment, so merged by the grid chart in two moment in the t-2 moment to base 2 sub-grid of t, the interconnecting relation between adjacent moment state in base 4 grid can be obtained.As shown in Fig. 5 (2), the input path tolerance of 4i state, 4i+1 state, 4i+2 state, 4i+3 state equals i state, i+2
k-3state, i+2
k-2state, i+3 × 2
k-3the outgoing route tolerance of state.According to such interconnecting relation, the present invention constructs reconfigurable path tolerance network 6 (CPMN) as shown in Fig. 5 (3).CPMN receiving parameter constraint degree, the corresponding interconnect architecture of real-time transform, the path metric value of exact connect ion adjacent moment, the iterative computation of realizing route tolerance.
Figure 6 shows that the structural representation of the present invention without base 4 acs unit 4 of symbolic operation, described base 4 acs unit 4 completes Gabi selection operation.At present, the design of two kinds of more general base 4 acs units is two-stage cascade comparative structure and one-level comparative structure.Two-stage cascade comparative structure refers to the process having carried out 4 input maximizings with two-stage comparative structure, its simplicity of design, but is cascade owing to having two-stage comparative structure, thus increases critical path.In order to shorten the logical path of acs unit, the present invention adopts one-level comparative structure.The Gabi selection calculation structure of single status as shown in Figure 7.Utilize four adders 4 path metric values inputted and score value metric to be added, then 4 addition results are sent into 6 comparators and compare between two; The result compared is sent into and selects logic, obtain survival bit; The path metric selecting logic to select maximum the most last in 4 addition results is again utilized to export.Base 4 acs unit adopts combinational logic to realize, traditional implementation structure is all the comparison and the addition that adopt signed number complement form, the associative operation of symbol must be considered, as shown in Fig. 6 (1), there is the comparator of symbol by the is-not symbol position subtraction result of two numbers to be compared, carry out XOR with two sign bits, thus obtain last comparative result, make combinational logic circuit complicated; And design metric of the present invention is signless integer, just can realize so comparator directly adopts without sign comparator, as shown in Fig. 6 (2).Compare, the critical path of comparator reduces 4 gate delays, and the critical path of base 4 acs unit is reduced to 4 gate delays from 8 gate delays, simplifies and realizes logic.
Figure 7 shows that the structural representation of normalization judging unit 5 of the present invention, described normalization judging unit 5 is to prevent the spilling of path metric value from all state measurement values are all deducted a fixed value.At present, normalized method mainly contains following several: be reset to state 0 method, deduct minimum value method, MSB position zero method, mould method for normalizing and highest order clearing method.Wherein, highest order clearing method is fastest, least in power-consuming, area is minimum.The design adopts highest order to reset method.In the past direct carry out after acs unit combinational logic normalization unlike, normalization decision logic is separated with acs unit by the present invention.The present invention utilizes two-stage as shown in Figure 8 and logic to judge whether all path metric value highest orders are 1.If highest order is all 1, the next clock cycle resets the highest order of all tolerance metrics again.Decision logic adopts two-stage flowing water, effectively reduces logical delay.Normalization decision logic just postpones to get rid of outside critical path by the benefit of such design.Normalization judging unit only gets front 2
k-1highest order is carried out and operation.
Figure 8 shows that the structural representation of the present invention's 3 decoding algorithm streamlines.The general two kinds of backtracking implementations of Viterbi decoder: Register exchange method and backtracking method.Although Register exchange method realizes simple, amount of logic is too huge, and the switching network of its complexity also can affect to frequency.Comparatively speaking, though backtracking method realizes occupying certain storage resources, but there is low complex degree and high-frequency advantage.The present invention adopts backtracking method.Viterbi algorithm is when recalling, no matter recall from which state, after reaching certain length-specific, its backtracking state will be pooled to certain fixing state; Then can recall forward from this stationary state again and finally obtain decoding bit.According to the These characteristics of Viterbi algorithm, the operation of a block mainly divides three parts: forward calculation, backtracking, decoding.Forward calculation comprises branch metric calculation and Gabi selection calculation.Three part operations adopt flowing water to realize.The corresponding forward calculation of blocking length of each rectangular block, backtracking, decoded operation.It is characterized in that streamline comprises three phases: forward calculation, backtracking, decoding.Streamline achieves the full water operation of three calculation stages, and three phases realizes latency hiding.The length in each stage is L, as parameters input in decoder.The most suitable length of blocking of distinct communication standards is different, and be less than this length decoding precision and will cause certain loss, being greater than its decoding latency of this length can corresponding increase.In order to find the compromise of decoding precision and decoding latency, we will block length and input as parametrization, and like this for often kind of communication standard, we can find both optimal balance points.Block length L change by the counter upper limit value in controller is set to L to realize.The delay of streamline is 4L, after the clock delay through 4L, starts the bit translating first block.The streamline of design can realize each clock cycle decoding two bits.
Experimental verification and Performance comparision
The experiment porch of decoder of the present invention adopts the FPGA development platform researched and developed voluntarily, and have employed Large Copacity Virtex7 Series FPGA of new generation, model is XC7VX485T.Experiment porch is integrated with radio-frequency device, can realize the wireless receiving and dispatching of signal.System employs two pieces of FPGA development boards.Transmitting terminal first carries out convolution coding to binary source signal, then carries out modulating, sends into wireless channel after digital transmission; Receiving terminal carries out Viterbi decoding after carrying out digital received, demodulation to signal.After obtaining decode results, 2 binary signal of result and input are passed through comparison, obtains the error rate of decoder.The communication standard of employing is input to adaptive controller by user, and adaptive controller converts it into series of parameters, sends encoder and parametrization many standards Viterbi decoder to.Decoder can change self structure according to dynamic state of parameters, builds the channel decoder for certain communication standard when not needing to reconstruct in real time.Controller and the error rate relatively pass through software simulating.
The decoder of design is used that ISE10.1 tools chain carries out comprehensively, layout, wiring, finally obtain as shown in table 2 realizing result.For the ease of contrast, achieve simultaneously base 2 constraint degree K be 9 fixed structure, the many normal structures of base 2 parametrization, base 4 constraint degree K be the fixed structure of 9 and the Viterbi decoder of the many normal structures of base 4 parametrization.As can be seen from Table 2, base normal structure more than 2 is compared with fixed structure, and resource overhead increases by 23.6%, and base normal structure more than 4 is compared with fixed structure, and resource overhead increases by 30.1%, suitable with base 2.The part increased mainly concentrates on acs unit in logic.Base 4 parametrization many normal structures amount of logic reaches 7823 Slices, and main cause is that the amount of logic of itself CPMN and CBMN is huge, accounts for about 14% of all amount of logic.Because the present invention adopts the implementation realized without sign comparator and normalization decision logic flowing water, the frequency of critical path ACSU has had remarkable lifting.Experimental result shows, the frequency of base 4 parametrization many standards Viterbi decoder that XC7VX485T platform realizes reaches 270.50MHz, and throughput reaches 541Mbps, and compared with base standard Viterbi more than 2 decoder, throughput improves 2.67 times.
Table 2 base 2 and base 4Viterbi decoder FPGA realize result
In order to verify the error performance of decoder, the present invention achieves the channel decoding of five kinds of communication standards such as GPRS, WiMAX, LTE (3GPP-LongTermEvolution), CDMAIS-95A and 3G on parametrization many standards Viterbi decoder, channel adopts Gaussian channel, and signal to noise ratio is changed to 0 to 5dB.For often kind of communication standard, testing its error rate under blocking length at three kinds, is 5 times of constraint degree, 6 times and 7 times respectively.The hard-wired fixed point decoder error rate of the results show is suitable with the floating-point decoder of software simulation.This parametrization many standards Viterbi decoder also further demonstrating the present invention's proposition has good flexibility and practicality.
In order to compare with related work, the present invention lists and realizes based on the base decoder of standard Viterbi more than 2 of FPGA platform and the typical case of base 4Viterbi decoder.Main Comparative indices is radix, constraint degree, code check, frequency and throughput.Performance comparison result is as shown in table 3.Due at present not the FPGA of base standard Viterbi more than 4 decoder realize, so there is no the decoder that related work can propose with the present invention and directly contrast.As can be seen from Table 3, the Viterbi decoder of current base 4 structure, its structure is fixing, the channel decoding that constraint degree is the communication standard of 6 or 7 can only be realized, and the base 4 structure decoder that the present invention realizes can carry out channel decoding work for the communication standard in constraint degree 3 to 9 scope, support the communication standards such as GPRS, WiMAX, LTE, CDMAIS-95A, 3G.
Show relevant parameter and the Performance comparision of different Viterbi decoder on 3FPGA platform
The present invention is based on XilinxXC7VX485TFPGA chip propose first and achieve base 4 parametrization many standards Viterbi decoder.This decoder while work, by Dynamical parameter configuration real-time transform structure, can realize the switching between several functions, to adapt to the communication standard of current selection, and block length by self-defined, find suitable decoding precision and decoding latency, complete corresponding channel decoding work.The constraint degree of decoder can change between 3 to 9, supports 1/2 and 1/3 two kind of code check.The block decoding length of decoder can by user's free setting.Decoder adopts without symbol metric calculation and the design of new acs unit, substantially reduce critical path, and the mode adopting normalization decision logic to be separated realization further increases the running frequency of decoder.Experimental result shows, many Standard basis 4 decoder throughput that the present invention realizes can reach 541Mbps, and all achieves good error performance to multiple communication standard.Compare with the related work based on FPGA platform, the decoder that the present invention proposes is the most much higher standard Viterbi decoder of current decoding rate, is also the base 4Viterbi decoder that decoding rate is the highest simultaneously.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, anyly belongs to those skilled in the art in the technical scope that the present invention discloses; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (6)
1. the parametrization many standards high-throughput decoder based on FPGA, it is characterized in that: comprise code conversion unit (1), branch metric calculation unit (2), restructural branch metric network (3), base 4 acs unit (4), normalization judging unit (5), reconfigurable path tolerance network (6) and traceback decoding unit (7), control unit (8)
Described code conversion unit (1), for receiving enter code word, and changes into signless integer by code word, then the signless integer of conversion is input to branch metric calculation unit (2);
Described branch metric calculation unit (2), the signless integer for transforming according to enter code word calculates the metric of each branch in base 4 grid chart;
Described restructural branch metric network (3), chooses corresponding branched measurement value and sends into corresponding base 4 acs unit (4) respectively in often kind for calculating from described branch metric calculation unit (2) possible branched measurement value;
Described base 4 acs unit (4), for being operated by Gabi selection, being calculated the path metric made new advances and being sent into normalization judging unit (5), and survival bit information is sent into traceback decoding unit (7);
Described normalization judging unit (5), judges whether the path metric value highest order of all inputs is 1, if be 1, then judges that path metric needs normalization, and the path metric value after normalization sends into reconfigurable path tolerance network (6); If be 0, then direct reconfigurable path of being sent into by path metric value measures network (6);
Described reconfigurable path tolerance network (6), for according to the adaptively selected suitable interconnecting relation of the change of constraint degree, then sends into new path metric value in base 4 acs unit (4) and carries out iterative computation;
Described traceback decoding unit (7), for carrying out 3 back-track algorithms according to the survival bit information received, recalling and decoded operation grid, finally exporting decoding bit;
Described control unit (8), be connected with code conversion unit (1), branch metric calculation unit (2), base 4 acs unit (4), traceback decoding unit (7) respectively, the flowing water being responsible for 3 algorithms in whole decoder controls.
2. as claimed in claim 1 based on parametrization many standards high-throughput decoder of FPGA, it is characterized in that: described branch metric calculation unit (2) supports the branch metric calculation unit of multi code Rate of Chinese character, the codeword information quantity of its input and the branch metric quantity of output can change according to code check R, when code check R is 1/2, the codeword information of input is two 3 bit codewords, altogether can form 4 base 2 branch metrics; When code check R is 1/3, the codeword information of input is three 3 bit codewords, altogether can form 8 base 2 branch metrics, when code check R is 1/2, always has 16 kinds of possible branch metrics; When code check is 1/3, always have 64 kinds of possible branch metrics.
3. as claimed in claim 1 based on parametrization many standards high-throughput decoder of FPGA, it is characterized in that: described restructural branch metric network (3) can form corresponding mapping relations according to the change of constraint degree K, described restructural branch metric network (3) has fixing interconnect architecture for often kind of constraint degree K, various code rate R and constraint degree K forms permutation and combination, for each Combination Design fixed structure, then selector is utilized to be integrated by these fixed structures, after receiving constraint degree K and code check R, restructural branch metric network (3) utilizes selector and corresponding parameter to select suitable interconnect architecture.
4. as claimed in claim 1 based on parametrization many standards high-throughput decoder of FPGA, it is characterized in that: described base 4 acs unit (4) comprises a large amount of Gabi selection calculation module, for calculating Gabi selection operation, Gabi selection calculation module number is relevant to constraint degree K, suppose that constraint degree is K, then Gabi selection calculation module number is 2
k-1, the maximum constrained degree of decoder support is 9, and Gabi selection calculation module maximum quantity is 256, and when after input constraint degree K, decoder selects front 2 in 256 Gabi selection calculation modules
k-1individual, the Gabi selection calculation module that shielding is remaining, thus realize the structure changing described base 4 acs unit 4 according to the change of constraint degree K.
5. as claimed in claim 1 based on parametrization many standards high-throughput decoder of FPGA, it is characterized in that: described reconfigurable path tolerance network (6) is for connecting the path metric value of continuous two each states of timing node, suitable interconnect architecture is selected according to the change of constraint degree K, realize the interconnecting relation between base 4 grid adjacent moment state, concrete, after described reconfigurable path tolerance network (6) receives constraint degree K, the path metric value of exact connect ion adjacent moment, its annexation is as follows: 4i state, 4i+1 state, 4i+2 state, the input path tolerance of 4i+3 state equals i state, i+2
k-3state, i+2
k-2state, i+3 × 2
k-3the outgoing route tolerance of state.
6. as claimed in claim 1 based on parametrization many standards high-throughput decoder of FPGA, it is characterized in that: described base 4 acs unit (4) utilizes four adders 4 path metric values inputted and score value metric to be added, and then 4 addition results is sent into 6 comparators and compares between two; The result compared is sent into and selects logic, obtain survival bit information, then send into traceback decoding unit (7), utilize and select logic in 4 addition results, select maximum to export as last path metric.
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| CN112865815A (en) * | 2019-11-26 | 2021-05-28 | 广州海格通信集团股份有限公司 | Turbo decoding method, Turbo decoding device, Turbo decoder and storage medium |
| CN112865815B (en) * | 2019-11-26 | 2024-01-02 | 广州海格通信集团股份有限公司 | Turbo decoding method, device, turbo decoder and storage medium |
| CN117787662A (en) * | 2024-02-23 | 2024-03-29 | 中国人民解放军海军工程大学 | Space demand balance partitioning method, electronic equipment and storage medium |
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