CN105159779A - Method and system for improving data processing performance of multi-core CPU - Google Patents
Method and system for improving data processing performance of multi-core CPU Download PDFInfo
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- CN105159779A CN105159779A CN201510505760.2A CN201510505760A CN105159779A CN 105159779 A CN105159779 A CN 105159779A CN 201510505760 A CN201510505760 A CN 201510505760A CN 105159779 A CN105159779 A CN 105159779A
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Abstract
The present invention provides a method for improving data processing performance of a multi-core CPU, which comprises: setting a corresponding data cache queue for each data core of the multi-core CPU; partitioning all the data cache queues into a plurality of groups; and when a data packet reaches, distributing, according to a preset rule, all data messages in the data packet to a plurality of data cores to carry out processing. Correspondingly, the present invention also discloses a system for improving data processing performance of the multi-core CPU. According to the technical scheme disclosed by the present invention, when load balance of the multi-core CPU is ensured, the lock conflict among the plurality of data cores of the multi-core CPU can be effectively reduced so as to improve the concurrence data processing ability of the multi-core CPU, thereby further implementing high-speed data forwarding of the multi-core CPU.
Description
Technical field
The present invention relates to field of computer technology, improve the method for multi-core CPU data processing performance and a kind of system improving multi-core CPU data processing performance in particular to a kind of.
Background technology
At present, along with the development of X86 multi-core technology, the application of X86 multi-core CPU in network processing unit gets more and more.At X86 multi-core CPU in the process of processing data packets, often relate to the base conditioning of the business object such as convection current, IP, but, in order to ensure the accuracy of business processing, frequent convection current, IP carry out mutually exclusive operation, thus make X86 multi-core CPU often be in resource contention state, cause the advantage of X86 multi-core CPU to be given full play of.
In the related, during X86 multi-core CPU handle packet, adopt the mode of training in rotation Message processing, namely the sequencing of multi-core CPU is delivered to according to data message, data message is distributed to multiple data core process, such as: first data message is delivered to first data core and processed, second data message is delivered to second data core and is processed, by that analogy.But, when the throughput ratio of data message is larger, between multiple data core, very large lock conflict can be produced, thus inhibit the performance of X86 multi-core CPU.
Therefore, when multi-core CPU processes packet, the lock conflict between the multinuclear how reducing multi-core CPU, thus the performance improving the bulk treatment data of multi-core CPU, become problem demanding prompt solution.
Summary of the invention
The present invention is just based on the problems referred to above, propose a kind of method improving multi-core CPU data processing performance, while guarantee multi-core CPU load balancing, lock conflict between multiple data core that effectively can reduce multi-core CPU, thus improve the ability of multi-core CPU concurrent processing data, and the high-speed data realizing multi-core CPU further forwards.
In view of this, the present invention proposes a kind of method improving multi-core CPU data processing performance, comprising: each data core for described multi-core CPU arranges corresponding data buffer storage queue; All described data buffer storage queues are divided into multiple groups; When there being packet to arrive, according to preset rules, all data messages in described packet being dispensed to multiple described data core and processing.
In this technical scheme, by for multi-core CPU (such as, X86 multi-core CPU) each data core set up a data buffer queue accordingly, for data cached message before each data core process data message, and all data buffer storage queues are divided into multiple groups, preferably, data buffer storage queue is divided into multiple groups, namely each group has the data buffer storage queue of equal number, certainly, also can unequally distribute, so, packet can be carried out more distribute to balanced and reasonable, when there being packets need process, according to preset rules, the data message in packet is distributed to multiple data core to process, thus the multinuclear of complete paired data bag shunting process.By this technical scheme, while guarantee multi-core CPU load balancing, the lock conflict between the multinuclear that effectively can reduce multi-core CPU, thus improve the ability of multi-core CPU concurrent processing data, and the high-speed data realizing multi-core CPU further forwards.
In technique scheme, preferably, described preset rules specifically comprises: be dispensed to according to first order hash algorithm by all described data messages at least one group in described multiple groups and process.
In this technical scheme, process by all data messages in packet are assigned at least one group according to first order hash algorithm, for ensure multi-core CPU load balancing and reduce multi-core CPU multinuclear between lock conflict provide favourable prerequisite guarantee.
In technique scheme, preferably, described preset rules specifically also comprises: be dispensed to during described data message in described group is dispensed in described group data buffer storage queue described at least one according to second level hash algorithm, process for the described data core corresponding with described data buffer storage queue.
In this technical scheme, by data message being assigned at least one the data buffer storage queue in a group according to second level hash algorithm, process for the data core corresponding with this data buffer storage queue, for ensure multi-core CPU load balancing and reduce multi-core CPU multinuclear between lock conflict provide favourable prerequisite guarantee.
In technique scheme, preferably, described first order hash algorithm comprises: IP hash algorithm.
In this technical scheme, first order hash algorithm includes but not limited to: IP hash algorithm.
In technique scheme, preferably, described second level hash algorithm comprises: five-tuple hash algorithm.
In this technical scheme, second level hash algorithm includes but not limited to: five-tuple hash algorithm.
According to a further aspect in the invention, also proposed a kind of system improving multi-core CPU data processing performance, comprising: module is set, for arranging corresponding data buffer storage queue for each data core of described multi-core CPU; Grouping module, for being divided into multiple groups by all described data buffer storage queues; Distribution module, when there being packet to arrive, processes for the data message in described packet being dispensed to multiple described data core according to preset rules.
In this technical scheme, by for multi-core CPU (such as, X86 multi-core CPU) each data core set up a data buffer queue accordingly, for data cached message before each data core process data message, and all data buffer storage queues are divided into multiple groups, preferably, data buffer storage queue is divided into multiple groups, namely each group has the data buffer storage queue of equal number, certainly, also can unequally distribute, so, packet can be carried out more distribute to balanced and reasonable, when there being packets need process, according to preset rules, the data message in packet is distributed to multiple data core to process, thus the multinuclear of complete paired data bag shunting process.By this technical scheme, while guarantee multi-core CPU load balancing, the lock conflict between the multinuclear that effectively can reduce multi-core CPU, thus improve the ability of multi-core CPU concurrent processing data, and the high-speed data realizing multi-core CPU further forwards.
In technique scheme, preferably, described distribution module comprises: the first computing module, for being dispensed to according to first order hash algorithm by all described data messages at least one group in described multiple groups, processes for the described data core corresponding with described data buffer storage queue.
In this technical scheme, process by all data messages in packet are assigned at least one group according to first order hash algorithm, for ensure multi-core CPU load balancing and reduce multi-core CPU multinuclear between lock conflict provide favourable prerequisite guarantee.
In technique scheme, preferably, described distribution module also comprises: the second computing module, processes in the described data message be dispensed in described group is dispensed in described group data buffer storage queue described at least one according to second level hash algorithm.
In this technical scheme, by data message being assigned at least one the data buffer storage queue in a group according to second level hash algorithm, process for the data core corresponding with this data buffer storage queue, for ensure multi-core CPU load balancing and reduce multi-core CPU multinuclear between lock conflict provide favourable prerequisite guarantee.
In technique scheme, preferably, described first order hash algorithm comprises: IP hash algorithm.
In this technical scheme, first order hash algorithm includes but not limited to: IP hash algorithm.
In technique scheme, preferably, described second level hash algorithm comprises: five-tuple hash algorithm.
In this technical scheme, second level hash algorithm includes but not limited to: five-tuple hash algorithm.
By above technical scheme, while guarantee multi-core CPU load balancing, lock conflict between multiple data core that effectively can reduce multi-core CPU, thus the ability improving multi-core CPU concurrent processing data, and the high-speed data realizing multi-core CPU further forwards.
Accompanying drawing explanation
Fig. 1 shows the schematic flow sheet of the method for raising multi-core CPU data processing performance according to an embodiment of the invention;
Fig. 2 shows the structural representation of the system of raising multi-core CPU data processing performance according to an embodiment of the invention;
Fig. 3 shows the schematic flow sheet of the method for raising multi-core CPU data processing performance according to another embodiment of the invention.
Embodiment
In order to more clearly understand above-mentioned purpose of the present invention, feature and advantage, below in conjunction with the drawings and specific embodiments, the present invention is further described in detail.It should be noted that, when not conflicting, the feature in the embodiment of the application and embodiment can combine mutually.
Set forth a lot of detail in the following description so that fully understand the present invention; but; the present invention can also adopt other to be different from other modes described here and implement, and therefore, protection scope of the present invention is not by the restriction of following public specific embodiment.
Fig. 1 shows the schematic flow sheet of the method for raising multi-core CPU data processing performance according to an embodiment of the invention.
As shown in Figure 1, the method for raising multi-core CPU data processing performance according to an embodiment of the invention, comprising: step 102, and each data core for described multi-core CPU arranges corresponding data buffer storage queue; Step 104, is divided into multiple groups by all described data buffer storage queues; All data messages in described packet, when there being packet to arrive, being dispensed to multiple described data core according to preset rules and processing by step 106.
In this technical scheme, by for multi-core CPU (such as, X86 multi-core CPU) each data core set up a data buffer queue accordingly, for data cached message before each data core process data message, and all data buffer storage queues are divided into multiple groups, preferably, data buffer storage queue is divided into multiple groups, namely each group has the data buffer storage queue of equal number, certainly, also can unequally distribute, so, packet can be carried out more distribute to balanced and reasonable, when there being packets need process, according to preset rules, the data message in packet is distributed to multiple data core to process, thus the multinuclear of complete paired data bag shunting process.By this technical scheme, while guarantee multi-core CPU load balancing, the lock conflict between the multinuclear that effectively can reduce multi-core CPU, thus improve the ability of multi-core CPU concurrent processing data, and the high-speed data realizing multi-core CPU further forwards.
In technique scheme, preferably, described preset rules specifically comprises: be dispensed to according to first order hash algorithm by all described data messages at least one group in described multiple groups and process.
In this technical scheme, process by all data messages in packet are assigned at least one group according to first order hash algorithm, for ensure multi-core CPU load balancing and reduce multi-core CPU multinuclear between lock conflict provide favourable prerequisite guarantee.
In technique scheme, preferably, described preset rules specifically also comprises: be dispensed to during described data message in described group is dispensed in described group data buffer storage queue described at least one according to second level hash algorithm and process.
In this technical scheme, by data message being assigned at least one the data buffer storage queue in a group according to second level hash algorithm, process for the data core corresponding with this data buffer storage queue, for ensure multi-core CPU load balancing and reduce multi-core CPU multinuclear between lock conflict provide favourable prerequisite guarantee.
In technique scheme, preferably, described first order hash algorithm comprises: IP hash algorithm.
In this technical scheme, first order hash algorithm includes but not limited to: IP hash algorithm.
In technique scheme, preferably, described second level hash algorithm comprises: five-tuple hash algorithm.
In this technical scheme, second level hash algorithm includes but not limited to: five-tuple hash algorithm.
Fig. 2 shows the structural representation of the system of raising multi-core CPU data processing performance according to an embodiment of the invention.
As shown in Figure 2, the system 200 of raising multi-core CPU data processing performance according to an embodiment of the invention, comprising: arrange module 202, for arranging corresponding data buffer storage queue for each data core of described multi-core CPU; Grouping module 204, for being divided into multiple groups by all described data buffer storage queues; Distribution module 206, when there being packet to arrive, processes for the data message in described packet being dispensed to multiple described data core according to preset rules.
In this technical scheme, by for multi-core CPU (such as, X86 multi-core CPU) each data core set up a data buffer queue accordingly, for data cached message before each data core process data message, and all data buffer storage queues are divided into multiple groups, preferably, data buffer storage queue is divided into multiple groups, namely each group has the data buffer storage queue of equal number, certainly, also can unequally distribute, so, packet can be carried out more distribute to balanced and reasonable, when there being packets need process, according to preset rules, the data message in packet is distributed to multiple data core to process, thus the multinuclear of complete paired data bag shunting process.By this technical scheme, while guarantee multi-core CPU load balancing, the lock conflict between the multinuclear that effectively can reduce multi-core CPU, thus improve the ability of multi-core CPU concurrent processing data, and the high-speed data realizing multi-core CPU further forwards.
In technique scheme, preferably, described distribution module 206 comprises: the first computing module 2062, processes for being dispensed to according to first order hash algorithm by all described data messages at least one group in described multiple groups.
In this technical scheme, process by all data messages in packet are assigned at least one group according to first order hash algorithm, for ensure multi-core CPU load balancing and reduce multi-core CPU multinuclear between lock conflict provide favourable prerequisite guarantee.
In technique scheme, preferably, described distribution module 206 also comprises: the second computing module 2064, for the described data message be dispensed in described group is dispensed in described group data buffer storage queue described at least one according to second level hash algorithm, process in the described data core corresponding with described data buffer storage queue.
In this technical scheme, by data message being assigned at least one the data buffer storage queue in a group according to second level hash algorithm, process for the data core corresponding with this data buffer storage queue, for ensure multi-core CPU load balancing and reduce multi-core CPU multinuclear between lock conflict provide favourable prerequisite guarantee.
In technique scheme, preferably, described first order hash algorithm comprises: IP hash algorithm.
In this technical scheme, first order hash algorithm includes but not limited to: IP hash algorithm.
In technique scheme, preferably, described second level hash algorithm comprises: five-tuple hash algorithm.
In this technical scheme, second level hash algorithm includes but not limited to: five-tuple hash algorithm.
Fig. 3 shows the schematic flow sheet of the method for raising multi-core CPU data processing performance according to another embodiment of the invention.
As shown in Figure 3, the method of raising multi-core CPU data processing performance according to another embodiment of the invention, particularly for X86 multi-core CPU 16 core CPU, first be that each data core in 16 data core arranges data buffer storage queue corresponding with it, then 16 data buffer queues are divided into 4 groups, each group comprises 4 data buffer queues, then correspondingly all data core be also divided into 4 groups, each group comprises 4 data core; When there being packet to arrive, using IP hash algorithm to be assigned at least one group in 4 groups by all data messages of packet, such as, being assigned to group 1; Five-tuple hash algorithm is used to be sent into by data message at least one the data buffer storage queue in data buffer storage queue 0 to 3, such as be assigned to data buffer storage queue 0, then corresponding data core 0 just processes data message, thus completes the multinuclear shunting of packet.
More than be described with reference to the accompanying drawings technical scheme of the present invention, consider in correlation technique, due to multi-core CPU packet is processed time, very large lock conflict is there will be between multiple data core of multi-core CPU, thus inhibit the performance of multi-core CPU performance, therefore, the invention provides a kind of method improving multi-core CPU data processing performance, while guarantee multi-core CPU load balancing, lock conflict between multiple data core that effectively can reduce multi-core CPU, thus improve the ability of multi-core CPU concurrent processing data, and the high-speed data realizing multi-core CPU further forwards.
In the present invention, term " first ", " second " object only for describing, and instruction or hint relative importance can not be interpreted as; Term " multiple " represents two or more.For the ordinary skill in the art, above-mentioned term concrete meaning in the present invention can be understood as the case may be.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. improve a method for multi-core CPU data processing performance, it is characterized in that, comprising:
Each data core for described multi-core CPU arranges corresponding data buffer storage queue;
All described data buffer storage queues are divided into multiple groups;
When there being packet to arrive, according to preset rules, all data messages in described packet being dispensed to multiple described data core and processing.
2. the method for raising multi-core CPU data processing performance according to claim 1, it is characterized in that, described preset rules specifically comprises:
All described data messages are dispensed to according to first order hash algorithm at least one group in described multiple groups and process.
3. the method for raising multi-core CPU data processing performance according to claim 2, it is characterized in that, described preset rules specifically also comprises:
During the described data message be dispensed in described group is dispensed in described group data buffer storage queue described at least one according to second level hash algorithm, process for the described data core corresponding with described data buffer storage queue.
4. the method for the raising multi-core CPU data processing performance according to Claims 2 or 3, is characterized in that, described first order hash algorithm comprises: IP hash algorithm.
5. the method for described raising multi-core CPU data processing performance according to claim 3, it is characterized in that, described second level hash algorithm comprises: five-tuple hash algorithm.
6. improve a system for multi-core CPU data processing performance, it is characterized in that, comprising:
Module is set, for arranging corresponding data buffer storage queue for each data core of described multi-core CPU;
Grouping module, for being divided into multiple groups by all described data buffer storage queues;
Distribution module, when there being packet to arrive, processes for the data message in described packet being dispensed to multiple described data core according to preset rules.
7. the system of raising multi-core CPU data processing performance according to claim 6, it is characterized in that, described distribution module comprises:
First computing module, processes for being dispensed to according to first order hash algorithm by all described data messages at least one group in described multiple groups.
8. the system of raising multi-core CPU data processing performance according to claim 7, it is characterized in that, described distribution module also comprises:
Second computing module, in the described data message be dispensed in described group is dispensed in described group data buffer storage queue described at least one according to second level hash algorithm, processes for the described data core corresponding with described data buffer storage queue.
9. the system of the raising multi-core CPU data processing performance according to claim 7 or 8, is characterized in that, described first order hash algorithm comprises: IP hash algorithm.
10. the system of raising multi-core CPU data processing performance according to claim 8, is characterized in that, described second level hash algorithm comprises: five-tuple hash algorithm.
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