CN105159766B - Synchronous access method and synchronous access device for data - Google Patents

Synchronous access method and synchronous access device for data Download PDF

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Publication number
CN105159766B
CN105159766B CN201510548924.XA CN201510548924A CN105159766B CN 105159766 B CN105159766 B CN 105159766B CN 201510548924 A CN201510548924 A CN 201510548924A CN 105159766 B CN105159766 B CN 105159766B
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data
access
synchronized
atomic operation
bits
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CN105159766A (en
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易鸿斌
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Beijing Baidu Netcom Science and Technology Co Ltd
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Iyuntian Co ltd
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Priority to PCT/CN2015/099893 priority patent/WO2017036041A1/en
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt

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  • General Engineering & Computer Science (AREA)
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Abstract

The application discloses a synchronous access method and a synchronous access device of data. The synchronous access method of the data comprises the following steps: distributing continuous memory units to the data to be synchronously accessed, wherein the data bit number of the continuous memory units is the sum of the data bit numbers of the data to be synchronously accessed; dividing the atomic operation instruction into data segments corresponding to the number of the data to be synchronously accessed based on the number of the data to be synchronously accessed and the number of data bits of each data to be synchronously accessed, wherein the number of bits of each data segment is greater than or equal to the number of bits of the data to be synchronously accessed corresponding to the data segment; and accessing data to be synchronously accessed in an instruction cycle, wherein the instruction cycle is the time length for executing the atomic operation instruction. According to the scheme of the application, a plurality of data with incidence relation can be synchronously accessed in the same atomic operation instruction period, the data access efficiency is improved, and the data processing speed of the computer is accelerated.

Description

The synchronization of access method of data and synchronization of access device
Technical field
The disclosure relates generally to computer technology, and in particular to the synchronization of access of data access technology more particularly to data Method and synchronization of access device.
Background technology
In the prior art, data are located at some position of storage region, and each data correspond to one for the same of synchronization Walk object.
When to shared, variable data respective synchronization of access, it is no signal condition to set the corresponding synchronization object of data, It is instructed by atomic operation and accesses data, if judging that the value of data meets preassigned correspondence, set corresponding Synchronization object is to have signal condition.
To there are during the synchronization of access of incidence relation data, wait the corresponding synchronization object of every other data to have letter Number state, then pass through atomic operation instruction and access notebook data.
However, existing synchronization of access method for there are the synchronization of access of the data of incidence relation, it is necessary to wait to be synchronized Object influences efficiency.In addition, when the IRQ level of processor is on thread scheduling level is other, this method is unavailable.
The content of the invention
In view of drawbacks described above of the prior art or deficiency, a kind of synchronization of access method for being intended to provide data is visited with synchronous It asks device, access can be synchronized to multiple data there are incidence relation within the same atomic operation instruction cycle, improve The efficiency of data access, so as to accelerating the speed of computer digital animation.
In a first aspect, the embodiment of the present application provides a kind of synchronization of access method of data, including:To access to be synchronized Data distribute contiguous memory unit, wherein, the data bits of contiguous memory unit is the data bit of the data of each access to be synchronized The sum of number;The data bits of the quantity of data based on access to be synchronized and the data of each access to be synchronized, atomic operation is referred to Order is divided into data segment corresponding with the quantity of the data of access to be synchronized, wherein, the digit of each data segment be greater than or equal to Corresponding access to be synchronized data digit;And within an instruction cycle, the data of access to be synchronized are accessed, In, the instruction cycle is the duration for performing atomic operation instruction.
Second aspect, the embodiment of the present application additionally provide a kind of synchronization of access device of data, including:Distribution module is matched somebody with somebody It puts for distributing contiguous memory unit to the data of access to be synchronized, wherein, the data bits of contiguous memory unit is each data The sum of data bits;Division module is configured to the quantity of the data based on access to be synchronized and the number of each access to be synchronized According to data bits, by atomic operation instruction be divided into data segment corresponding with the quantity of the data of access to be synchronized, wherein, respectively The digit of data segment is greater than or equal to the digit of the data of corresponding access to be synchronized;And access modules, it is configured to Within an instruction cycle, the data of access to be synchronized are accessed, wherein, the duration that the instruction cycle instructs for execution atomic operation.
Scheme provided by the embodiments of the present application can access multiple data simultaneously in an atomic operation instruction cycle, Improve the efficiency of reading and writing data.
It is visited in addition, carrying out the synchronous of data on the premise of the total bit of data is less than or equal to atomic operation instruction digit It asks, can ensure that the correctness of incidence relation between each data to avoid modification of other threads to data.
In some realization methods of the embodiment of the present application, can also be determined by the instruction of atomic operation each data it Between incidence relation.
Description of the drawings
By reading the detailed description made to non-limiting example made with reference to the following drawings, the application's is other Feature, objects and advantages will become more apparent upon:
Fig. 1 shows the schematic flow chart of the synchronization of access method according to the data of the application one embodiment;
Fig. 2 shown in Fig. 1, the data bit of the data of the quantity of the data based on access to be synchronized and each access to be synchronized Atomic operation instruction is divided into the schematic flow chart of data segment corresponding with the quantity of the data of access to be synchronized by number;
Fig. 3 shows the schematic diagram of an application scenarios of the synchronization of access method according to the data of the embodiment of the present application;
Fig. 4 shows the schematic diagram of the synchronization of access device according to the data of the application one embodiment.
Specific embodiment
The application is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched The specific embodiment stated is used only for explaining related invention rather than the restriction to the invention.It also should be noted that in order to Convenient for description, illustrated only in attached drawing with inventing relevant part.
It should be noted that in the case where there is no conflict, the feature in embodiment and embodiment in the application can phase Mutually combination.The application is described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.
It is shown in Figure 1, it is the schematic flow chart according to the synchronization of access method of the data of the application one embodiment 100。
Specifically, in step 110, contiguous memory unit is distributed to the data of access to be synchronized.Wherein, contiguous memory The data bits of unit is the sum of data bits of data of each access to be synchronized.
Memory Allocation refers to distribution or the operation of recycling memory space during program performs.And the company of memory The continuous method of salary distribution refers to distribute a continuous memory headroom for a user program.The continuous dispensing mode of memory includes single One continuous dispensing, fixed partition distribution and dynamic partition distribution etc..
In the present embodiment, by data distribute contiguous memory unit, can in order in subsequent step to each data It fast and efficiently accesses, so as to improve treatment effeciency.
In some optional realization methods, for example, the common data there are four access to be synchronized, each access to be synchronized Data include 16.So, when carrying out the distribution of contiguous memory unit to these data, 64 contiguous memories can be distributed Unit (16 × 4), for storing the data of these access to be synchronized.
Then, in the step 120, the data of the quantity of the data based on access to be synchronized and the data of each access to be synchronized Atomic operation instruction is divided into data segment corresponding with the quantity of the data of access to be synchronized by digit, wherein, each data segment Digit is greater than or equal to the digit of the data of corresponding access to be synchronized.
Atomic operation refers to not interruptable one or sequence of operations, that is, will not be beaten by thread scheduling mechanism Disconnected operation will not have any context switching (context switch) during operation.
So, when being accessed using atomic operation instruction to the data of each access to be synchronized, which will not It is interrupted by other threads, in other words, before atomic operation instruction instruction is finished, the value of the data of internal storage location memory storage It will not be changed by other threads.
Equally with there are four the data of access to be synchronized, the data of each access to be synchronized are said comprising 16 altogether It is bright.In order to carry out concurrent access to the data of four access to be synchronized, atomic operation can be instructed and be divided into four data segments, To correspond to the data for accessing this four access to be synchronized respectively.Moreover, the data processing digit of each data segment is not less than 16.
Herein, it is necessary to explanation, data processing digit and access to be synchronized in order to illustrate atomic operation instruction The magnitude relationship of the data bits of data, this data for sentencing each access to be synchronized are illustrated including 16.However In a practical situation, the data of each access to be synchronized may have identical data bits, it is also possible to have different data bit Number.Correspondingly, in order to be adapted to the data bits of the data of each access to be synchronized, original corresponding with the data of each access to be synchronized The data processing digit of the data segment of child-operation instruction may also be identical or different.
Such as the data bits of the data A of access to be synchronized is 16, the data bits of the data B of access to be synchronized is 8 Position, then when carrying out data segment division, at least there are the data of 16 for accessing the data segment of the data A of access to be synchronized Digit is handled, and the data segment for being used to access the data B of access to be synchronized at least has the data processing digit of 8.
Then, in step 130, within an instruction cycle, the data of access to be synchronized are accessed, wherein, the instruction cycle To perform the duration of atomic operation instruction.
In other words, in this step, each data segment instructed by atomic operation accesses each visit to be synchronized to correspond to The data asked.
Herein, reading, write-in or other operations can for example be included to the access of the data of each access to be synchronized Classification.
Using the synchronization of access method of the data of the present embodiment, can be treated together within an instruction cycle, while to multiple The data that step accesses carry out parallel access.Further, since the number of these access to be synchronized is accessed by atomic operation instruction According to the access will not be interrupted by other thread scheduling mechanisms.
It is shown in Figure 2, in the synchronization of access method for the data of the present embodiment, based on the data bits of each data, adjust The step of being instructed with the atomic operation of processor (i.e. schematic flow Figure 200 of step 120) as shown in Figure 1.
Specifically, in step 210, the data bits of the data of each access to be synchronized is obtained.
In some optional realization methods, for example, the contiguous memory of the data distribution to access to be synchronized can be passed through The data bits of unit determines the data bits of the data of each access to be synchronized.
As shown in Figure 1, the data bits for having been based on data in step 110 is assigned with contiguous memory unit to data. So, data bits that can be based on contiguous memory unit and to each data storage allocation unit when it is shared memory it is empty Between size determine the data bits of the data of each access to be synchronized.
It returns with continued reference to Fig. 2.In a step 220, the sum of data bits of data of more each access to be synchronized and original The data processing digit of child-operation instruction.
Then, the data processing digit in step 230 based on atomic operation instruction is greater than or equal to each access to be synchronized The sum of the data bits of data, atomic operation instruction is divided into data segment corresponding with the quantity of data.
For example, equally with there are four the data (A~D) of access to be synchronized, each data are illustrated comprising 16 altogether. If the data processing digit of atomic operation instruction is 64, in other words, the data processing digit of atomic operation instruction is equal to respectively The sum of data bits of data of access to be synchronized (16 × 4), then atomic operation can be instructed and be divided into four data segments. Each data segment can correspond to the data for accessing one of them access to be synchronized respectively.
Conversely, if the data processing digit of atomic operation instruction is 32, in other words, at the data of atomic operation instruction It manages digit and is less than the sum of the data bits of data of each access to be synchronized (16 × 4), then do not carry out atomic operation instruction corresponding Data segment division.The reason is that the sum of data bits due to four access to be synchronized refers to beyond an atomic operation The upper limit for the data bits that the instruction cycle of order can be handled, these access data to be synchronized can not refer in same atomic operation Synchronization of access is completed in the instruction cycle of order.
It returns with continued reference to Fig. 1.In some optional realization methods, each atomic operation instruction of execution of step 130 is same The operation that step accesses corresponding data can for example include, and data are read and/or changed within an instruction cycle.At this In, the instruction cycle is the duration for performing atomic operation instruction.
For example, in some optional realization methods, the execution content of atomic operation instruction is " reading ".So, atom After operational order performs, it can be returned the numerical value of each data as return value.
Alternatively, in other realization methods, the execution content of atomic operation instruction is " modification ".So, atomic operation After instruction performs, the numerical value of each data will be changed accordingly.
In some optional realization methods, the synchronization of access method of the data of the present embodiment can also include step 140, Within the instruction cycle, based on the return value for the data for accessing access to be synchronized, determine that the association of the data of each access to be synchronized is closed System.
The incidence relation of the data of each access to be synchronized can for example include numerical operation relation or logical operation relation.
For example, equally with there are four the data (A~D) of access to be synchronized, each data are illustrated comprising 16 altogether. It, can be according to one of value in the data of this four access to be synchronized, to determine other treat in some optional realization methods The value of the data of synchronization of access, for example, when tri- access to be synchronized of B, C, D data numerical value for 0, then by access to be synchronized The value of data A is set to 1.It alternatively, can also be according to numerical value wherein several in the data of this four access to be synchronized, to calculate it The numerical value of remainder evidence, for example, to update the value of A, in other words, can be counted according to the value of the data of the access to be synchronized of A~D Calculate A=A+B+C+D.
In the following, the synchronization of access of the data of the embodiment of the present application will be expanded on further with reference to application scenarios shown in Fig. 3 The implementation procedure of method, so that its feature can more fully be illustrated.
As shown in Figure 3, it is assumed that there are four access data A, B, C, D to be synchronized.It is this first with reference to flow shown in FIG. 1 Four data A~D to be synchronized that access distribute continuous internal storage location 310 (as shown in the step 110 in Fig. 1).
Then, in order within the instruction cycle of atomic operation instruction to the data A~D of this four access to be synchronized into Row synchronization of access, if the sum of data bits of data A~D is no more than the data processing digit of atomic operation instruction, by atom Operational order is divided into four data segments 320, i.e., respectively data segment one corresponding with data A~D of four access to be synchronized, number According to section two, data segment three and data segment four (as shown in the step 120 in Fig. 1), and within an instruction cycle, pass through each data Section concurrently accesses data A~D of each access to be synchronized corresponding with each data segment (as shown in the step 130 in Fig. 1).
It then, can also be according to each data segment to each access to be synchronized for accessing data A~D as shown in reference numeral 330 As a result, in the same atomic operation instruction cycle, each incidence relation (such as Fig. 1 to be synchronized accessed between data A~D is determined In step 140 shown in).After incidence relation determines, it may be necessary to the data pair based on wherein one or more access to be synchronized Other data are updated.
Using the synchronization of access method of above-mentioned data, can simultaneously be accessed in an atomic operation instruction cycle multiple The data of access to be synchronized improve the efficiency of reading and writing data.
In addition, it is carried out on the premise of the total bit of data is less than or equal to the data processing digit of atomic operation instruction multiple The synchronization of access of the data of access to be synchronized, can to avoid modification of other threads to the data of these multiple access to be synchronized, It ensure that the correctness of incidence relation between the data of each access to be synchronized.
It is shown in Figure 4, it is the schematic diagram according to the synchronization of access device of the data of the application one embodiment 400。
The synchronization of access device of the data of the present embodiment can include distribution module 410, division module 420 and access modules 430。
Wherein, distribution module 410 is configurable to distribute contiguous memory unit to the data of access to be synchronized.
Herein, the data bits of contiguous memory unit is the sum of data bits of data of each access to be synchronized.
Division module 420 is configurable to the quantity of the data based on access to be synchronized and the data of each access to be synchronized Atomic operation instruction is divided into data segment corresponding with the quantity of the data of access to be synchronized by data bits.
Herein, the digit of each data segment is greater than or equal to the digit of the data of corresponding access to be synchronized.
Access modules 430 were configurable within an instruction cycle, accessed the data of access to be synchronized.
Herein, the duration that the instruction cycle instructs for execution atomic operation.
In some optional realization methods, division module 420 may further be configured to obtain each access to be synchronized Data data bits;Compare the data processing that the sum of data bits of data of each access to be synchronized is instructed with atomic operation Digit;And the data processing digit based on atomic operation instruction is greater than or equal to the data bits of the data of each access to be synchronized The sum of, atomic operation instruction is divided into data segment corresponding with the quantity of data.
In some optional realization methods, access modules 430 may further be configured within an instruction cycle Read and/or change the data of access to be synchronized.
In some optional realization methods, the synchronization of access device of the data of the present embodiment can also include incidence relation Determining module 440.
Incidence relation determining module 440 was configurable within the instruction cycle, based on the data for accessing access to be synchronized Return value determines the incidence relation of the data of each access to be synchronized.
Herein, incidence relation can for example include numerical operation relation or logical operation relation.
Flow chart and block diagram in attached drawing, it is illustrated that according to the system of various embodiments of the invention, method and computer journey Architectural framework in the cards, function and the operation of sequence product.In this regard, each box in flow chart or block diagram can generation The part of one module of table, program segment or code, a part for the module, program segment or code include one or more The executable instruction of logic function as defined in being used to implement.It should also be noted that some as replace realization in, institute in box The function of mark can also be occurred with being different from the order marked in attached drawing.For example, two boxes succeedingly represented are actual On can perform substantially in parallel, they can also be performed in the opposite order sometimes, this is depending on involved function.Also It is noted that the combination of each box in block diagram and/or flow chart and the box in block diagram and/or flow chart, Ke Yiyong The dedicated hardware based systems of functions or operations as defined in execution is realized or can referred to specialized hardware and computer The combination of order is realized.
Being described in unit or module involved in the embodiment of the present application can be realized by way of software, can also It is realized by way of hardware.Described unit or module can also be set in the processor, for example, can be described as: A kind of processor includes distribution module, division module and access modules.Wherein, the title of these units or module is in certain situation Under do not form restriction to the unit or module in itself, for example, distribution module is also described as " being used to distribute to data The module of contiguous memory unit ".
As on the other hand, present invention also provides a kind of computer readable storage medium, the computer-readable storage mediums Matter can be computer readable storage medium included in device described in above-described embodiment;Can also be individualism, not The computer readable storage medium being fitted into equipment.There are one computer-readable recording medium storages or more than one journey Sequence, described program are used for performing the formula input method for being described in the application by one or more than one processor.
The preferred embodiment and the explanation to institute's application technology principle that above description is only the application.People in the art Member should be appreciated that invention scope involved in the application, however it is not limited to the technology that the particular combination of above-mentioned technical characteristic forms Scheme, while should also cover in the case where not departing from the inventive concept, it is carried out by above-mentioned technical characteristic or its equivalent feature The other technical solutions for being combined and being formed.Such as features described above has similar work(with (but not limited to) disclosed herein The technical solution that the technical characteristic of energy is replaced mutually and formed.

Claims (10)

1. a kind of synchronization of access method of data, which is characterized in that including:
Contiguous memory unit is distributed to the data of access to be synchronized, wherein, the data bits of the contiguous memory unit is each institute State the sum of data bits of data of access to be synchronized;
The data bits of the quantity of data based on the access to be synchronized and the data of each access to be synchronized, atom is grasped Make instruction and be divided into data segment corresponding with the quantity of the data of access to be synchronized, wherein, the digit of each data segment is more than Or the data bits of the data equal to the corresponding access to be synchronized;And
Within an instruction cycle, the data of the access to be synchronized are accessed, wherein, the described instruction cycle is the execution atom The duration of operational order.
2. according to the method described in claim 1, it is characterized in that, the quantity of the data based on the access to be synchronized and Atomic operation instruction is divided into the quantity with the data of access to be synchronized by the data bits of the data of each access to be synchronized Corresponding data segment includes:
Obtain the data bits of the data of each access to be synchronized;
Compare the data processing digit that the sum of data bits of data of each access to be synchronized is instructed with the atomic operation; And
Data processing digit based on atomic operation instruction is greater than or equal to the data of the data of each access to be synchronized Atomic operation instruction is divided into data segment corresponding with the quantity of data by the sum of digit.
3. according to the method described in claim 1, it is characterized in that, described within an instruction cycle, access is described to be synchronized The data of access include:
The data of the access to be synchronized are read and/or changed within an instruction cycle.
4. according to the method described in claim 3, it is characterized in that, the method further includes:
Within the described instruction cycle, based on the return value for the data for accessing the access to be synchronized, each visit to be synchronized is determined The incidence relation for the data asked.
5. according to the method described in claim 4, it is characterized in that:
The incidence relation includes numerical operation relation or logical operation relation.
6. a kind of synchronization of access device of data, which is characterized in that including:
Distribution module is configured to distribute contiguous memory unit to the data of access to be synchronized, wherein, the contiguous memory unit Data bits for each data the sum of data bits;
Division module is configured to the quantity of the data based on the access to be synchronized and the data of each access to be synchronized Atomic operation instruction is divided into data segment corresponding with the quantity of the data of access to be synchronized by data bits, wherein, it is each described The digit of data segment is greater than or equal to the data bits of the data of the corresponding access to be synchronized;And
Access modules were configured within an instruction cycle, accessed the data of the access to be synchronized, wherein, described instruction The duration that cycle instructs for the execution atomic operation.
7. device according to claim 6, which is characterized in that the division module is further configured to:
Obtain the data bits of the data of each access to be synchronized;
Compare the data processing digit that the sum of data bits of data of each access to be synchronized is instructed with the atomic operation; And
Data processing digit based on atomic operation instruction is greater than or equal to the data of the data of each access to be synchronized Atomic operation instruction is divided into data segment corresponding with the quantity of data by the sum of digit.
8. device according to claim 6, which is characterized in that the access modules are further configured to:
The data of the access to be synchronized are read and/or changed within an instruction cycle.
9. according to the device described in claim 6-8 any one, which is characterized in that described device further includes:
Incidence relation determining module was configured within the described instruction cycle, based on the data for accessing the access to be synchronized Return value determines the incidence relation of the data of each access to be synchronized.
10. device according to claim 9, it is characterised in that:
The incidence relation includes numerical operation relation or logical operation relation.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101052947A (en) * 2004-11-03 2007-10-10 皇家飞利浦电子股份有限公司 Programmable data processing circuit that supports simd instruction
CN101133396A (en) * 2005-01-24 2008-02-27 国际商业机器公司 Method for managing access to shared resources in a multi-processor environment
CN103970506A (en) * 2008-03-28 2014-08-06 英特尔公司 Vector instruction to enable efficient synchronization and parallel reduction operations
CN104025031A (en) * 2011-12-28 2014-09-03 英特尔公司 Reducing the number of sequential operations in an application to be performed on a shared memory cell

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9256476B2 (en) * 2011-12-10 2016-02-09 International Business Machines Corporation Expedited module unloading for kernel modules that execute read-copy update callback processing code
US9218204B2 (en) * 2012-12-21 2015-12-22 Advanced Micro Devices, Inc. Processing engine for complex atomic operations
CN105159766B (en) * 2015-08-31 2018-05-25 安一恒通(北京)科技有限公司 Synchronous access method and synchronous access device for data

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101052947A (en) * 2004-11-03 2007-10-10 皇家飞利浦电子股份有限公司 Programmable data processing circuit that supports simd instruction
CN101133396A (en) * 2005-01-24 2008-02-27 国际商业机器公司 Method for managing access to shared resources in a multi-processor environment
CN103970506A (en) * 2008-03-28 2014-08-06 英特尔公司 Vector instruction to enable efficient synchronization and parallel reduction operations
CN104025031A (en) * 2011-12-28 2014-09-03 英特尔公司 Reducing the number of sequential operations in an application to be performed on a shared memory cell

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