CN105140177A - Preparation method of array substrate, array substrate, display panel and display device - Google Patents
Preparation method of array substrate, array substrate, display panel and display device Download PDFInfo
- Publication number
- CN105140177A CN105140177A CN201510434559.XA CN201510434559A CN105140177A CN 105140177 A CN105140177 A CN 105140177A CN 201510434559 A CN201510434559 A CN 201510434559A CN 105140177 A CN105140177 A CN 105140177A
- Authority
- CN
- China
- Prior art keywords
- amorphous silicon
- silicon layer
- layer
- array base
- base palte
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 21
- 230000008569 process Effects 0.000 claims abstract description 18
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 57
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 52
- 229920005591 polysilicon Polymers 0.000 claims description 52
- 229920002120 photoresistant polymer Polymers 0.000 claims description 27
- 239000011248 coating agent Substances 0.000 claims description 17
- 238000000576 coating method Methods 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 15
- FMGSKLZLMKYGDP-USOAJAOKSA-N dehydroepiandrosterone Chemical class C1[C@@H](O)CC[C@]2(C)[C@H]3CC[C@](C)(C(CC4)=O)[C@@H]4[C@@H]3CC=C21 FMGSKLZLMKYGDP-USOAJAOKSA-N 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000004380 ashing Methods 0.000 claims description 5
- 230000000903 blocking effect Effects 0.000 abstract description 13
- 238000000059 patterning Methods 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 99
- 238000001312 dry etching Methods 0.000 description 5
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000002346 layers by function Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention provides a preparation method of an array substrate, the array substrate, a display panel and a display device, belongs to the technical field of display, and can solve problems of complex technology and relatively high cost due to respective patterning of a light blocking layer and an active layer of the array substrate in the prior art. According to the preparation method of the array substrate, the array substrate, the display panel and the display device, the light blocking layer and the active layer of the array substrate are patterned by adopting the same mask plate so that the number of the mask plate is saved, one step of patterning technology is saved and cost is reduced. Meanwhile, an alignment problem in the process of the patterning technology does not need to be considered so that the equipment requirement and control precision can be reduced.
Description
Technical field
The invention belongs to Display Technique field, be specifically related to a kind of preparation method of array base palte, array base palte, display floater, display unit.
Background technology
Array base palte in display unit generally comprises the thin-film transistor that polysilicon is formed as active layer, the channel region being irradiated to polysilicon active layer of the high energy light in backlight or surround lighting, can the phenomenons such as electron transition be caused, thus affect the stability of thin-film transistor.
Generally light blocking layer is set at backlight or between surround lighting and active layer; in order to the channel region making light blocking layer protect active layer to greatest extent; general by the size being more than or equal to active layer of the size design of light blocking layer, and light blocking layer and active layer carry out alignment setting in the incident direction of light.
When generally preparing light blocking layer, use light blocking layer mask board to explosure, then carry out developing, the graphical treatment such as etching; Adopting active layer mask board to explosure when preparing active layer, then carrying out developing, the graphical treatment such as etching; That is light blocking layer and active layer adopt respective mask plate respectively, and graphical respectively, must use two mask plates in such preparation process, twice patterning processes, complicated process of preparation, preparation cost are higher;
Meanwhile, light blocking layer and active layer prepare the problem of the alignment pattern also related in preparation process respectively, higher to the required precision of alignment, accordingly to equipment and control overflow higher, cause cost higher, control complicated.
Summary of the invention
The object of the invention is to solve the light blocking layer of array base palte in prior art and active layer and graphically produce complex process, problem that cost is higher respectively.
The technical scheme that solution the technology of the present invention problem adopts is a kind of preparation method of array base palte, comprises the following steps:
Same mask plate is adopted to form the step of the figure of spaced apart amorphous silicon layer and polysilicon layer.
Preferably, the step that the same mask plate of described employing forms the figure of spaced apart amorphous silicon layer and polysilicon layer comprises:
Described polysilicon layer forms photoresist, and adopts mask board to explosure, development;
Described polysilicon layer and amorphous silicon layer are carried out to the figure of first time etching formation amorphous silicon;
Photoresist is carried out to the step of ashing process, photoresist is formed and polysilicon graphics graph of a correspondence;
The figure that second time etching forms polysilicon is carried out to polysilicon layer.
Preferably, the step that the same mask plate of described employing forms the figure of spaced apart amorphous silicon layer and polysilicon layer comprises:
Described polysilicon layer forms photoresist, and adopts semi-transparent mask board to explosure, development, make described photoresist formation central area thickness be greater than the figure of fringe region, wherein, the figure of described photoresist is corresponding with the figure of described amorphous silicon layer,
The figure of described central area is corresponding with the figure of described polysilicon layer;
Carry out described polysilicon layer and amorphous silicon layer etching the figure forming amorphous silicon layer and polysilicon layer.
Preferably, also comprised before the same mask plate of employing forms the step of the figure of spaced apart amorphous silicon layer and polysilicon layer:
Substrate deposits the step of the first resilient coating, the first amorphous silicon layer, the second resilient coating, the second amorphous silicon layer successively;
Second amorphous silicon layer is converted into the step of polysilicon layer;
The described step second amorphous silicon layer being converted into polysilicon layer comprises: carry out the step of Dehydroepiandrosterone derivative and the step of excimer laser process to the second amorphous silicon layer.
Another object of the present invention also comprises provides a kind of array base palte, and described array base palte adopts the preparation method of above-mentioned array base palte to prepare.
Another object of the present invention also comprises provides a kind of display floater, described display surface+comprise above-mentioned array base palte.
Another object of the present invention also comprises provides a kind of display unit, and described display unit comprises above-mentioned display floater.
The preparation method of array base palte of the present invention, array base palte, display floater, display unit, owing to adopting same mask plate to be undertaken graphically by the light blocking layer of array base palte and active layer, save the quantity of mask plate, save a step patterning processes, reduce cost; Simultaneously without the need to considering the alignment problem in patterning process, reduce the requirement to equipment and control precision.
Accompanying drawing explanation
Fig. 1 is the structural representation of array base palte that deposited the first resilient coating, the first amorphous silicon layer, the second resilient coating, the second amorphous silicon layer in the embodiment of the present invention 1 or embodiment 2.
Fig. 2 is the structural representation in the embodiment of the present invention 1 or embodiment 2, second amorphous silicon layer being carried out to the array base palte after Dehydroepiandrosterone derivative and excimer laser process.
Fig. 3 is the structural representation of the array base palte after adopting mask plate exposure, development in the embodiment of the present invention 1.
Fig. 4 is the structural representation carrying out the rear array base palte of first time etching in the embodiment of the present invention 1.
Fig. 5 is the structural representation in the embodiment of the present invention 1, photoresist being carried out to array base palte after ashing process.
Fig. 6 is the structural representation carrying out the rear array base palte of second time etching in the embodiment of the present invention 1.
Fig. 7 carries out the structural representation of array base palte after second time etching stripping photoresist in the embodiment of the present invention 1.
Fig. 8 is the structural representation adopting semi-transparent mask board to explosure, the rear array base palte of development in the embodiment of the present invention 2.
Fig. 9 is the structural representation carrying out etching rear array base palte in the embodiment of the present invention 2.
Figure 10 is the structural representation of array base palte after stripping photoresist in the embodiment of the present invention 2.
Wherein:
1. substrate; 2. the first resilient coating; 3. the first amorphous silicon layer; 4. the second resilient coating; 5. the second amorphous silicon layer; 51. polysilicon layers; 6. photoresist.
Embodiment
For making those skilled in the art understand technical scheme of the present invention better, below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Embodiment 1
As shown in Figure 1, the present embodiment provides a kind of preparation method of array base palte, comprises the following steps:
Same mask plate is adopted to form the step of the figure of spaced apart amorphous silicon layer and polysilicon layer.
The preparation method of the array base palte in the present embodiment, owing to adopting same mask plate to be undertaken graphically by the light blocking layer of array base palte and active layer, saves the quantity of mask plate, saves a step patterning processes, reduces cost; Simultaneously without the need to considering the alignment problem in patterning process, reduce the requirement to equipment and control precision.
Particularly, following steps can be adopted to carry out the preparation of array base palte:
S1: the step depositing the first resilient coating, the first amorphous silicon layer, the second resilient coating, the second amorphous silicon layer on substrate successively;
As shown in Figure 1, deposit the first resilient coating 2, first amorphous silicon layer 3, second resilient coating 4, second amorphous silicon layer 5 on substrate 1 successively,
Should be understood that, can prepare above-mentioned functions layer by using plasma enhancing chemical vapour deposition technique, concrete deposition process is prior art category, and this is no longer going to repeat them.
S2: the step the second amorphous silicon layer being converted into polysilicon layer;
As shown in Figure 2, carry out Dehydroepiandrosterone derivative and excimer laser process to the second amorphous silicon layer 5, make the second amorphous silicon layer 5 be converted into polysilicon layer 51, above-mentioned Dehydroepiandrosterone derivative and excimer laser are treated to prior art category, and this is no longer going to repeat them.
S3: form photoresist on described polysilicon layer 51, and adopt mask board to explosure, development;
As shown in Figure 3, make the figure of photoresist 6 identical with the figure of first amorphous silicon layer 3 that will be formed after adopting mask plate exposure, development.
S4: the figure described polysilicon layer and the first amorphous silicon layer being carried out to first time etching formation first amorphous silicon layer;
Adopt dry etching, particularly, chlorine can be adopted to etch polysilicon layer 51, second resilient coating 4 and the first amorphous silicon layer 3, form the figure of the first amorphous silicon layer 3 as shown in Figure 4.
S5: the step of photoresist being carried out to ashing process, makes photoresist be formed and polysilicon graphics graph of a correspondence;
As shown in Figure 5, particularly, ashing process can adopt oxygen to carry out dry etching to photoresist 6, makes the figure of photoresist 6 identical with the figure of the polysilicon layer 51 that will be formed.
S6: the figure that second time etching forms polysilicon is carried out to polysilicon layer;
Adopt dry etching, chlorine can be adopted particularly to etch polysilicon layer 51, form the figure of polysilicon layer 51 as shown in Figure 6.After further stripping photoresist 6, the structure of array base palte as shown in Figure 7.
Optionally, continue other the necessary functional layer preparing array base palte, this is no longer going to repeat them.
Embodiment 2
The present embodiment provides the preparation method of another kind of array base palte, particularly, following steps can be adopted to carry out the preparation of array base palte:
S1: the step depositing the first resilient coating, the first amorphous silicon layer, the second resilient coating, the second amorphous silicon layer on substrate successively;
As shown in Figure 1, deposit the first resilient coating 2, first amorphous silicon layer 3, second resilient coating 4, second amorphous silicon layer 5 on substrate 1 successively,
Should be understood that, can prepare above-mentioned functions layer by using plasma enhancing chemical vapour deposition technique, concrete deposition process is prior art category, and this is no longer going to repeat them.
S2: the step the second amorphous silicon layer being converted into polysilicon layer;
As shown in Figure 2, carry out Dehydroepiandrosterone derivative and excimer laser process to the second amorphous silicon layer 5, make the second amorphous silicon layer 5 be converted into polysilicon layer 51, above-mentioned Dehydroepiandrosterone derivative and excimer laser are treated to prior art category, and this is no longer going to repeat them.
S3: as shown in Figure 8, described polysilicon layer 51 forms photoresist 6, and adopts semi-transparent mask board to explosure, development; The figure making described photoresist 6 form central area thickness to be greater than fringe region, wherein, the figure of described photoresist 6 is corresponding with the figure of described first amorphous silicon layer 3, and the figure of described central area is corresponding with the figure of described polysilicon layer 51;
S4: the figure etching formation first amorphous silicon layer and polysilicon layer 51 is carried out to described polysilicon layer 51 and amorphous silicon layer.
As shown in Figure 9, by dry etching, concrete grammar can be identical with the dry etching in embodiment 1, once etches the figure simultaneously forming the first amorphous silicon layer 3 and polysilicon layer 51.
Array base palte is formed as shown in Figure 10 after stripping photoresist 6.
Optionally, continue other the necessary functional layer preparing array base palte, this is no longer going to repeat them.
Embodiment 3
The present embodiment provides a kind of array base palte, and described array base palte adopts the preparation method of above-mentioned array base palte to prepare.
Embodiment 4
The present embodiment provides a kind of display floater, and described display floater comprises above-mentioned array base palte.
Embodiment 5
The present embodiment provides a kind of display unit, and described display unit comprises above-mentioned display floater.
Be understandable that, the illustrative embodiments that above execution mode is only used to principle of the present invention is described and adopts, but the present invention is not limited thereto.This display unit can be: any product or parts with Presentation Function such as mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.The enforcement of this display unit see above-described embodiment, can repeat part and repeats no more.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.
Claims (7)
1. a preparation method for array base palte, is characterized in that, comprises the following steps:
Same mask plate is adopted to form the step of the figure of spaced apart amorphous silicon layer and polysilicon layer.
2. the preparation method of array base palte as claimed in claim 1, is characterized in that,
The step that the same mask plate of described employing forms the figure of spaced apart amorphous silicon layer and polysilicon layer comprises:
Described polysilicon layer forms photoresist, and adopts mask board to explosure, development;
Described polysilicon layer and amorphous silicon layer are carried out to the figure of first time etching formation amorphous silicon;
Photoresist is carried out to the step of ashing process, photoresist is formed and polysilicon graphics graph of a correspondence;
The figure that second time etching forms polysilicon is carried out to polysilicon layer.
3. the preparation method of array base palte as claimed in claim 1, is characterized in that,
The step that the same mask plate of described employing forms the figure of spaced apart amorphous silicon layer and polysilicon layer comprises:
Described polysilicon layer forms photoresist, and adopts semi-transparent mask board to explosure, development, make described photoresist formation central area thickness be greater than the figure of fringe region, wherein, the figure of described photoresist is corresponding with the figure of described amorphous silicon layer,
The figure of described central area is corresponding with the figure of described polysilicon layer;
Carry out described polysilicon layer and amorphous silicon layer etching the figure forming amorphous silicon layer and polysilicon layer.
4. the preparation method of array base palte as claimed in claim 1, is characterized in that,
Also comprised before the same mask plate of employing forms the step of the figure of spaced apart amorphous silicon layer and polysilicon layer:
Substrate deposits the step of the first resilient coating, the first amorphous silicon layer, the second resilient coating, the second amorphous silicon layer successively;
Second amorphous silicon layer is converted into the step of polysilicon layer;
The described step second amorphous silicon layer being converted into polysilicon layer comprises: carry out the step of Dehydroepiandrosterone derivative and the step of excimer laser process to the second amorphous silicon layer.
5. an array base palte, is characterized in that, described array base palte be adopt as arbitrary in claim 1-4 as described in the preparation method of array base palte prepare.
6. a display floater, is characterized in that, described display floater comprises array base palte as claimed in claim 5.
7. a display unit, is characterized in that, described display unit comprises display floater as claimed in claim 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510434559.XA CN105140177A (en) | 2015-07-22 | 2015-07-22 | Preparation method of array substrate, array substrate, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510434559.XA CN105140177A (en) | 2015-07-22 | 2015-07-22 | Preparation method of array substrate, array substrate, display panel and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105140177A true CN105140177A (en) | 2015-12-09 |
Family
ID=54725475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510434559.XA Pending CN105140177A (en) | 2015-07-22 | 2015-07-22 | Preparation method of array substrate, array substrate, display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105140177A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019051863A1 (en) * | 2017-09-15 | 2019-03-21 | 惠科股份有限公司 | Method for manufacturing active array switch |
| CN109786324A (en) * | 2019-03-15 | 2019-05-21 | 京东方科技集团股份有限公司 | A kind of low temperature polysilicon base plate and preparation method thereof, array substrate |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030143377A1 (en) * | 2002-01-30 | 2003-07-31 | Keiichi Sano | Display apparatus having a light shielding layer |
| CN101022085A (en) * | 2007-03-12 | 2007-08-22 | 友达光电股份有限公司 | Semiconductor element and producing method thereof |
| CN101345261A (en) * | 2007-07-09 | 2009-01-14 | Nec液晶技术株式会社 | Thin film transistor and manufacturing method of the same |
| US20090278131A1 (en) * | 2008-05-06 | 2009-11-12 | Kwon Do-Hyun | Thin film transistor array arrangement, organic light emitting display device having the same, and manufacturing method thereof |
| CN103268855A (en) * | 2012-12-19 | 2013-08-28 | 上海天马微电子有限公司 | Polycrystalline silicon forming method, TFT (thin film transistor) array substrate manufacturing method and display device |
| CN104409512A (en) * | 2014-11-11 | 2015-03-11 | 深圳市华星光电技术有限公司 | Low-temperature polycrystalline silicon thin-film transistor based on dual-gate structure and preparation method thereof |
| CN104779300A (en) * | 2015-04-16 | 2015-07-15 | 京东方科技集团股份有限公司 | Polycrystalline silicon thin film transistor and manufacturing method and display device thereof |
-
2015
- 2015-07-22 CN CN201510434559.XA patent/CN105140177A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030143377A1 (en) * | 2002-01-30 | 2003-07-31 | Keiichi Sano | Display apparatus having a light shielding layer |
| CN101022085A (en) * | 2007-03-12 | 2007-08-22 | 友达光电股份有限公司 | Semiconductor element and producing method thereof |
| CN101345261A (en) * | 2007-07-09 | 2009-01-14 | Nec液晶技术株式会社 | Thin film transistor and manufacturing method of the same |
| US20090278131A1 (en) * | 2008-05-06 | 2009-11-12 | Kwon Do-Hyun | Thin film transistor array arrangement, organic light emitting display device having the same, and manufacturing method thereof |
| CN103268855A (en) * | 2012-12-19 | 2013-08-28 | 上海天马微电子有限公司 | Polycrystalline silicon forming method, TFT (thin film transistor) array substrate manufacturing method and display device |
| CN104409512A (en) * | 2014-11-11 | 2015-03-11 | 深圳市华星光电技术有限公司 | Low-temperature polycrystalline silicon thin-film transistor based on dual-gate structure and preparation method thereof |
| CN104779300A (en) * | 2015-04-16 | 2015-07-15 | 京东方科技集团股份有限公司 | Polycrystalline silicon thin film transistor and manufacturing method and display device thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019051863A1 (en) * | 2017-09-15 | 2019-03-21 | 惠科股份有限公司 | Method for manufacturing active array switch |
| CN109786324A (en) * | 2019-03-15 | 2019-05-21 | 京东方科技集团股份有限公司 | A kind of low temperature polysilicon base plate and preparation method thereof, array substrate |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2020140366A1 (en) | Array substrate and manufacturing method thereof, display panel and display apparatus | |
| US9329445B2 (en) | Mask plate and processes for manufacturing ultraviolet mask plate and array substrate | |
| CN104102094B (en) | Mask baffle plate and manufacture method thereof | |
| US10503325B2 (en) | Display device, touch panel and method for manufacturing the same | |
| CN106653774B (en) | Array substrate and manufacturing method thereof, mask and display device | |
| US20180158953A1 (en) | Array substrate and method for manufacturing the same | |
| US8017460B2 (en) | Method of manufacturing flat panel display | |
| US20180233379A1 (en) | Method of forming via hole, array substrate and method of forming the same and display device | |
| WO2015096312A1 (en) | Array substrate and manufacturing method thereof, and display device | |
| CN102651322A (en) | Thin film transistor and manufacturing method thereof, array substrate and display device | |
| CN104934449A (en) | Display substrate and manufacturing method thereof, and display apparatus | |
| CN102608860B (en) | Lithographic methods, reticle combination and exposure system | |
| CN105655289A (en) | Array substrate, manufacturing method thereof and display device | |
| CN103560088B (en) | The manufacture method of array base palte | |
| CN105140177A (en) | Preparation method of array substrate, array substrate, display panel and display device | |
| CN105336684A (en) | Polysilicon array substrate manufacturing method, polysilicon array and display panel | |
| US20160240558A1 (en) | Manufacturing method for array substrate, array substrate and display device | |
| CN105206621B (en) | A kind of patterning process, array substrate and display device | |
| CN107564803B (en) | Etching method, process equipment, thin film transistor device and manufacturing method thereof | |
| CN100485861C (en) | Film etching method | |
| US9590231B2 (en) | Method of manufacturing 3D barrier substrate | |
| KR20120074695A (en) | Glass substrate comprising transparent electrode pattern | |
| CN105161454A (en) | Array substrate and manufacturing method thereof, display apparatus | |
| WO2020133827A1 (en) | Method for manufacturing blue phase liquid crystal panel, and method for manufacturing three-dimensional electrode of blue phase liquid crystal panel | |
| CN106200258B (en) | A kind of manufacturing method of mask plate, method and circuit board that it is exposed |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20151209 |
|
| RJ01 | Rejection of invention patent application after publication |