CN105138099B - Isolation circuit for solving overlarge voltage drop - Google Patents
Isolation circuit for solving overlarge voltage drop Download PDFInfo
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- CN105138099B CN105138099B CN201510495172.5A CN201510495172A CN105138099B CN 105138099 B CN105138099 B CN 105138099B CN 201510495172 A CN201510495172 A CN 201510495172A CN 105138099 B CN105138099 B CN 105138099B
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- 238000002955 isolation Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 claims description 43
- 230000002618 waking effect Effects 0.000 description 7
- 230000007423 decrease Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 230000037007 arousal Effects 0.000 description 1
- 210000005069 ears Anatomy 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000035611 feeding Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
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Abstract
The invention discloses an isolation circuit for solving the problem of overlarge voltage drop, which relates to the technical field of server power supply and mainly comprises a triode Q1, an MOS tube Q2, a P3V3_ BAT of a button battery on a mainboard and a P3V3 of the mainboard, wherein the P3V3_ BAT of the button battery is connected with a D pole of an MOS tube Q2, the P3V3 of the mainboard is connected with an S pole of an MOS tube Q2, a G pole of the MOS tube Q2 is connected with a collector of a triode Q1, an S pole of the MOS tube Q2 is connected with an IC power supply end of a wake-up chip on the mainboard, a base of the triode Q1 is connected with the P3V3_ BAT of the button battery, and an emitter of the triode Q1 is grounded. Because the voltage drop generated when the MOS tube is conducted is much smaller than that generated when the diode is conducted, the invention can ensure that the voltage of the power supply end of the awakening chip is controlled within a normal voltage range, effectively avoid the problem that the chip can not normally work due to too low voltage, and improve the stability and the safety of the system.
Description
Technical field
The present invention relates to server power supply technique fields, specifically a kind of to solve the excessive isolation circuit of pressure drop.
Background technology
In general, on server master board, it is all integrated on mainboard for power saving, while again in order to realize arousal function
There is corresponding wake up to control wake-up chip.This kind of operating voltage for waking up chip is 3.3V, and saving operation mode is in mainboard
When, all electricity are all cut off on mainboard, at this time, it may be necessary to the P3V3_BAT of the button cell on mainboard is to waking up chip power supply,
It is in normal operating conditions to ensure to wake up chip.After mainboard is switched on, with the P3V3 on mainboard to chip power supply is waken up, with section
Save the electric energy of battery.
Chip power supply is waken up since the P3V3 after P3V3_BAT and the mainboard booting of button cell gives, to prevent from being switched on
When, the P3V3_BAT of button cell is poured on mainboard All other routes on mainboard, is influenced electrifying timing sequence when mainboard booting, is needed
One isolation circuit of addition between P3V3 duplex feedings after P3V3_BAT and the mainboard booting of button cell.
The isolation circuit of use is directly to add an isolating diode between P3V3_BAT and P3V3.Wherein, P3V3_
BAT is connected on the anode of diode, and P3V3 is connected on the cathode of diode.Ensure：When mainboard is not switched on, by button cell
P3V3_BAT gives wake-up chip power supply；After booting, the P3V3_BAT of button cell is spaced, and wake-up core is given by the P3V3 of mainboard
Piece is powered.
This isolation circuit is since using isolating diode, when mainboard is not switched on, button cell passes through isolation two
Pole pipe forward conduction, due to will produce conduction voltage drop when diode current flow, after conducting, wakes up core to chip power supply is waken up
Piece power supply terminal voltage will decline 0.7V（If what diode was selected is silicone tube）.At this point, to the supply voltage of die terminals is waken up just
Supply voltage lower limit may be exceeded, cause to wake up chip operation exception.
Invention content
The shortcoming that the present invention develops for current needs and the prior art, provide a kind of solution pressure drop it is excessive every
From circuit.
A kind of isolation circuit that solution pressure drop is excessive of the present invention, solves the technical solution of above-mentioned technical problem use such as
Under：P3V3_BAT and mainboard of the isolation circuit mainly including button cell on a triode Q1, a metal-oxide-semiconductor Q2, mainboard
P3V3, wherein the poles D of the P3V3_BAT connection metal-oxide-semiconductors Q2 of the button cell, the S of the P3V3 connection metal-oxide-semiconductors Q2 of the mainboard
The poles G of pole, the metal-oxide-semiconductor Q2 are connected with the collector of triode Q1, and chip is waken up on the S grades connection mainboard of the metal-oxide-semiconductor Q2
IC feeder ears, while the base stage of the triode Q1 is connected to the P3V3_BAT of button cell, the emitter of the triode Q1
Ground connection；Chip IC feeder ear is waken up on mainboard and is also connected with a capacitance, and the capacitance other end is grounded.
Preferably, the metal-oxide-semiconductor Q2 is managed using P-MOS.
Preferably, the triode Q1 uses NPN type triode.
Preferably, which uses the MLCC capacitances of 0.1uf.
Preferably, a current-limiting resistance R is also set up between the metal-oxide-semiconductor Q2 and the P3V3_BAT of button cell.
Preferably, a resistance R1 is set between the base stage and the P3V3_BAT of button cell of the triode Q1, described three
One resistance R2 is set between the collector of pole pipe Q1 and the poles S of metal-oxide-semiconductor Q2, determines according to actual conditions parameter R1 R2.
A kind of isolation circuit that solution pressure drop is excessive of the present invention, has an advantageous effect in that compared with prior art：
Isolation circuit proposed by the present invention substitutes diode, due to the pressure generated when metal-oxide-semiconductor is connected using the isolation circuit with metal-oxide-semiconductor
Drop is more much smaller than what is generated when diode current flow, can ensure that the voltage for waking up chip power supply end is controlled in normal power supply voltage model
In enclosing, it is possible to prevente effectively from the problem of chip can not work normally caused by supply voltage is too low, improves the stability of system
And safety；Also, present inventive concept is novel, reasonable for structure, realization is simple, therefore has preferable application value.
Description of the drawings
Attached drawing 1 is isolation circuit structure chart of the present invention；
Attached drawing 2 is the isolation circuit structure chart before improving.
Specific implementation mode
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, to a kind of isolation circuit further description that solution pressure drop is excessive of the present invention.
Isolation circuit of the present invention substitutes isolating diode using the isolation circuit with metal-oxide-semiconductor, ensures that mainboard is not being opened
When machine, after metal-oxide-semiconductor circuit is isolated, metal-oxide-semiconductor can be connected button cell, and the P3V3_BAT of the button cell on realization mainboard is called out
Awake chip power supply；After mainboard is switched on, metal-oxide-semiconductor cut-off directly gives wake-up chip power supply by the P3V3 on mainboard.Due to isolation
When metal-oxide-semiconductor is connected, when pressure drop ratio diode current flow of generation, is generated much smaller, by the isolation circuit, can guarantee
Up to the voltage for waking up chip power supply end in the range of normal power supply voltage, it can effectively evade the wake-up chip on mainboard because supplying
Piezoelectric voltage too low the problem of causing can not work normally.
Embodiment：
It is a kind of described in the present embodiment to solve the excessive isolation circuit of pressure drop, include mainly a triode Q1, a metal-oxide-semiconductor Q2,
The P3V3_BAT of the P3V3 of the P3V3_BAT of button cell and mainboard on mainboard, the button cell are connected on the poles D of metal-oxide-semiconductor Q2,
The P3V3 of the mainboard is connected on the poles S of metal-oxide-semiconductor Q2, and the poles G of the metal-oxide-semiconductor Q2 are connected with the collector of triode Q1, institute
It states and wakes up chip IC feeder ear on the S grades connection mainboard of metal-oxide-semiconductor Q2, while the base stage of the triode Q1 is connected to button electricity
The emitter of the P3V3_BAT in pond, the triode Q1 are grounded；Chip IC feeder ear is waken up on mainboard is also connected with a capacitance, and
The capacitance other end ground connection.
In isolation circuit described in the present embodiment, the metal-oxide-semiconductor Q2 is managed using P-MOS, while can be according to wake-up chip
Rated operational current selects suitable P-MOS to manage, including：The specified conducting electric current of Ids, that is, metal-oxide-semiconductor, Rds (on) i.e. metal-oxide-semiconductors
Conduction impedance；The triode Q1 uses NPN type triode.Wake-up chip power supply end capacitance selection 0.1uf in the present embodiment
MLCC capacitances；A current-limiting resistance R, also, three pole are also set up between the metal-oxide-semiconductor Q2 and the P3V3_BAT of button cell
The collector and metal-oxide-semiconductor Q2 of one resistance R1, the triode Q1 are set between the base stage of pipe Q1 and the P3V3_BAT of button cell
The poles S between a resistance R2 is set, on mainboard in the practical application of isolation circuit, suitable current-limiting resistance R can be selected, and
Determine parameter R1 R2；As shown in Fig. 1.
Using isolation circuit described in the present embodiment, when mainboard is not switched on, knob battery is connected by triode Q1 base stages
P3V3_BAT, the triode Q1 conductings, the G extremely low levels of metal-oxide-semiconductor Q2；At this point, Vgs<0, metal-oxide-semiconductor Q2 conducting, electric current by
The poles D of metal-oxide-semiconductor Q2 flow into, and wake up chip power supply end by the poles the S flow direction of metal-oxide-semiconductor Q2, give wake-up chip power supply.Due at this point,
Metal-oxide-semiconductor Q2 is fully on, and conduction voltage drop is very low, generally in 20mv magnitudes.After mainboard is switched on, metal-oxide-semiconductor Q2 cut-offs, then directly
It connects and gives wake-up chip power supply by the P3V3 on mainboard.
And existing isolation circuit mainly uses isolating diode D2 as shown in Fig. 2, and the button cell on mainboard is supplied
Power supply P3V3 when electric P3V3_BAT is switched on mainboard directly keeps apart, wherein P3V3_BAT is connected on the anode of diode, P3V3
It is connected on the cathode of diode.But this isolation circuit is directly passed through when mainboard is not switched on by the P3V3_BAT of button cell
Diode D2 forward conductions are to chip power supply is waken up, and due to will produce conduction voltage drop when diode current flow, reach and wake up chip confession
The pressure drop at electric end is larger（Generally in 400mv ~ 700mv magnitudes）.If what diode was selected is silicone tube, after conducting, core is waken up
Piece power supply terminal voltage will decline 0.7V, at this point, may exceed under supply voltage to the supply voltage for waking up chip power supply end
Limit causes the risk for waking up chip cisco unity malfunction.
Isolation circuit of the present invention is improved existing isolation circuit compared with existing isolation circuit, improved
Isolation circuit is matched using a metal-oxide-semiconductor and a triode, and it is excessive to solve the problems, such as that wake-up chip power supply side pressure drops.In mainboard
When being not powered on, after metal-oxide-semiconductor circuit is isolated, metal-oxide-semiconductor can be connected button cell, since pressure drop caused by metal-oxide-semiconductor is lower, from
And ensure that the voltage for waking up chip power supply end can control within the scope of normal power supply, it can effectively evade and wake up chip because of power supply
The problem of brownout can not work normally.
Above-mentioned specific implementation mode is only the specific case of the present invention, and scope of patent protection of the invention includes but not limited to
Above-mentioned specific implementation mode, any person of an ordinary skill in the technical field that meet claims of the present invention and any
The appropriate change or replacement done to it, all shall fall within the protection scope of the present invention.
Claims (4)
1. a kind of solving the excessive isolation circuit of pressure drop, which is characterized in that including knob on a triode Q1, a metal-oxide-semiconductor Q2, mainboard
Detain the P3V3 of the P3V3_BAT and mainboard of battery, wherein the poles D of the P3V3_BAT connection metal-oxide-semiconductors Q2 of the button cell, it is described
The poles S of the P3V3 connection metal-oxide-semiconductors Q2 of mainboard, the poles G of the metal-oxide-semiconductor Q2 are connected with the collector of triode Q1, the metal-oxide-semiconductor Q2
The poles S connection mainboard on wake up chip IC feeder ear, while the base stage of the triode Q1 is connected to the P3V3_ of button cell
The emitter of BAT, the triode Q1 are grounded；Chip IC feeder ear is waken up on mainboard is also connected with a capacitance, and the capacitance
The other end is grounded；
A current-limiting resistance R is also set up between the metal-oxide-semiconductor Q2 and the P3V3_BAT of button cell；
One resistance R1, the current collection of the triode Q1 are set between the base stage and the P3V3_BAT of button cell of the triode Q1
One resistance R2 is set between pole and the poles S of metal-oxide-semiconductor Q2, determines according to actual conditions parameter R1 R2.
2. a kind of according to claim 1 solve the excessive isolation circuit of pressure drop, which is characterized in that the metal-oxide-semiconductor Q2 is used
P-MOS is managed.
3. a kind of according to claim 2 solve the excessive isolation circuit of pressure drop, which is characterized in that the triode Q1 is used
NPN type triode.
4. a kind of according to claim 3 solve the excessive isolation circuit of pressure drop, which is characterized in that the wake-up chip IC is powered
Capacitance is held to use the MLCC capacitances of 0.1uf.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510495172.5A CN105138099B (en) | 2015-08-13 | 2015-08-13 | Isolation circuit for solving overlarge voltage drop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510495172.5A CN105138099B (en) | 2015-08-13 | 2015-08-13 | Isolation circuit for solving overlarge voltage drop |
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| Publication Number | Publication Date |
|---|---|
| CN105138099A CN105138099A (en) | 2015-12-09 |
| CN105138099B true CN105138099B (en) | 2018-08-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510495172.5A Active CN105138099B (en) | 2015-08-13 | 2015-08-13 | Isolation circuit for solving overlarge voltage drop |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106230245B (en) * | 2016-08-30 | 2018-12-11 | 青岛歌尔声学科技有限公司 | A kind of protection circuit and electronic product |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5747891A (en) * | 1993-11-30 | 1998-05-05 | Siliconix Incorporated | Method of blocking bidirectional flow of current |
| CN2596670Y (en) * | 2002-12-17 | 2003-12-31 | 上海贝岭股份有限公司 | Two-way power automatic switching circuit on sheet |
| CN1627593A (en) * | 2003-12-11 | 2005-06-15 | 上海贝尔阿尔卡特股份有限公司 | Switching circuit for low voltage power supply in master-slave power supply mode |
| CN1983761A (en) * | 2006-05-29 | 2007-06-20 | 华为技术有限公司 | Controller for switching main power supply |
| CN202178607U (en) * | 2011-08-11 | 2012-03-28 | 深圳长城开发科技股份有限公司 | Handheld device and battery and external power source power supply switching circuit thereof |
| CN103915882A (en) * | 2014-04-01 | 2014-07-09 | 深圳市理邦精密仪器股份有限公司 | Input circuit with multiple power sources connected in parallel |
-
2015
- 2015-08-13 CN CN201510495172.5A patent/CN105138099B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5747891A (en) * | 1993-11-30 | 1998-05-05 | Siliconix Incorporated | Method of blocking bidirectional flow of current |
| CN2596670Y (en) * | 2002-12-17 | 2003-12-31 | 上海贝岭股份有限公司 | Two-way power automatic switching circuit on sheet |
| CN1627593A (en) * | 2003-12-11 | 2005-06-15 | 上海贝尔阿尔卡特股份有限公司 | Switching circuit for low voltage power supply in master-slave power supply mode |
| CN1983761A (en) * | 2006-05-29 | 2007-06-20 | 华为技术有限公司 | Controller for switching main power supply |
| CN202178607U (en) * | 2011-08-11 | 2012-03-28 | 深圳长城开发科技股份有限公司 | Handheld device and battery and external power source power supply switching circuit thereof |
| CN103915882A (en) * | 2014-04-01 | 2014-07-09 | 深圳市理邦精密仪器股份有限公司 | Input circuit with multiple power sources connected in parallel |
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| CN105138099A (en) | 2015-12-09 |
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