CN105118415B - Grid driving circuit and grid signal synchronization method thereof - Google Patents
Grid driving circuit and grid signal synchronization method thereof Download PDFInfo
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- CN105118415B CN105118415B CN201510609515.6A CN201510609515A CN105118415B CN 105118415 B CN105118415 B CN 105118415B CN 201510609515 A CN201510609515 A CN 201510609515A CN 105118415 B CN105118415 B CN 105118415B
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Abstract
A gate driving circuit and a gate signal synchronization method thereof are provided. The grid driving circuit is suitable for a touch panel and comprises a grid signal generating circuit and a grid signal synchronizing circuit. The gate signal generating circuit is used for receiving an input signal, a first timing signal and a second timing signal and outputting a gate signal according to the received input signal, the first timing signal and the second timing signal in a display period of the touch panel. The gate signal synchronization circuit is electrically connected to the gate signal generation circuit, and is configured to receive the control signal and the sensing signal during a sensing period of the touch panel, and to control the gate signal generation circuit to synchronously output the sensing signal during an enabling period of the control signal.
Description
Technical field
The present invention relates to a kind of gate driving circuit, more particularly to it is a kind of can be same during the sensing of contact panel
Walk the gate driving circuit of output sensing signal.
Background technology
In the prior art, contact panel has during display and during sensing, interior during display, and contact panel is used
With display picture, and during sensing in, contact panel is sensing touching signal.It is that touch sensing element is whole at present
The technology inside the image element circuit of contact panel is closed, this technology is to utilize the sensing signal positioned at contact panel periphery to supply
Circuit and during the sensing of contact panel in, sensing signal is provided to the common electrode to image element circuit, now when having
When e.g. the object such as finger touches contact panel, the change that capacitance is produced between common electrode and finger can be caused, by
This can learn touch coordinate via computing circuit.
However, when during contact panel being in sensing, common electrode can receive foregoing sensing signal, and data wire
And scan line not reception signal, so the parasitic capacitance between common electrode and data wire, scan line inside image element circuit
The transmission efficiency of sensing signal can be reduced and influence the sensing function of contact panel.Prior art utilizes and provides data-signal extremely
The data-signal supply circuit of data wire and contact panel be in sensing during when, synchronously provide with sensing signal essence
On upper identical data-signal to data wire, the potential difference for making the parasitic capacitance both ends between common electrode and data wire is used
It is identical to improve its influence to sensing signal, but there has been no be adapted to the parasitic capacitance between common electrode and scan line
Improving countermeasure.
The content of the invention
The present invention provides a kind of gate driving circuit, and it can improve the influence caused by above-mentioned parasitic capacitance.
The present invention also provides a kind of signal synchronous method suitable for above-mentioned gate driving circuit.
A kind of gate driving circuit proposed by the present invention is applied to contact panel, it include signal generation circuit with
And signal synchronous circuit.Signal generation circuit is receiving input signal, the first clock signal and the second sequential
Signal, and input signal, the first clock signal and the second sequential letter that interior foundation is received during the display of contact panel
Number and export signal.Signal synchronous circuit is electrically connected to signal generation circuit, and signal synchronous circuit is used
To receive control signal and sensing signal during the sensing of contact panel, signal synchronous circuit is in control letter
Number enable during control gate signal generating circuit synchronously output sensing signal.
In a preferred embodiment of the invention, above-mentioned gate driving circuit to sequentially operate in display during and feel
During survey, during display is operated in, control signal is in forbidden energy and signal generation circuit is according to input signal, first
Clock signal and the second clock signal and export signal at least once.During sensing is operated in, control signal is in
Enable, the first clock signal and the second clock signal are in forbidden energy, and signal generation circuit is synchronously outputted grid
The sensing signal that signal synchronization circuit is received.
The present invention also proposes a kind of signal synchronous method suitable for above-mentioned gate driving circuit, and the method includes
The following steps:During the display of contact panel, there is provided input signal, the first clock signal and the second clock signal to grid
Pole signal generating circuit simultaneously makes signal generation circuit export an at least signal according to this;And the sense in contact panel
During survey, the clock signal of forbidden energy first and the second clock signal, and control signal and sensing signal are provided to signal
Synchronous circuit, so that signal generation circuit synchronously outputs the sensing signal that signal synchronous circuit is received.
The gate driving circuit of the present invention is touching signal generation circuit because employing signal synchronous circuit
The synchronizing signal substantially the same with sensing signal is synchronously outputted in during controlling the sensing of panel, therefore touch-control can be improved
Influence of the parasitic capacitance between common electrode in image element circuit and scan line for sensing signal in panel.
Brief description of the drawings
Fig. 1 is the block diagram of the gate driving circuit of one embodiment of the invention;
Fig. 2 is the timing diagram of the gate driving circuit of one embodiment of the invention;
Fig. 3 is the circuit diagram of the gate driving circuit of one embodiment of the invention;
Fig. 4 is the flow chart of the signal synchronous method of one embodiment of the invention.
【Reference numeral explanation】
100:Gate driving circuit
101:Signal generation circuit
102:Signal synchronous circuit
Bi:Input signal
CK:First clock signal
XCK:Second clock signal
Gn、Gn-1、Gn+1:Signal
TP_EN:Control signal
TP_GOA:Sensing signal
10:Pull-up unit
20:Drop-down unit
30:Driver element
Vgl:Reference potential
S1:Pull up signal
C1、C2:Electric capacity
M1、M2、M3、M4、M5、M6、M7、MS:Transistor
M1-1、M2-1、M3-1、M4-1、M5-1、M6-1、M7-1、MS-1、C1-1、C2-1:First end
M1-2、M2-2、M3-2、M4-2、M5-2、M6-2、M7-2、MS-2、C1-2、C2-2:Second end
M1-3、M2-3、M3-3、M4-3、M5-3、M6-3、M7-3、MS-3:Control terminal
S401、S402:Step
Embodiment
Fig. 1 is the block diagram of the gate driving circuit of one embodiment of the invention.As shown in figure 1, gate driving circuit 100 is applicable
In contact panel (not shown), it includes signal generation circuit 101 and signal synchronous circuit 102.Signal
Generation circuit 101 is to receive input signal Bi, the first clock signal CK and the second clock signal XCK, and in contact panel
Display during interior foundation the input signal Bi, the first clock signal CK and the second clock signal XCK that are received and export grid
Pole signal Gn, this signal Gn are provided during the display of contact panel to the scan line (not shown) of contact panel.Grid
Signal synchronization circuit 102 is electrically connected to signal generation circuit 101.Signal synchronous circuit 102 is in contact panel
Sensing during receive control signal TP_EN and sensing signal TP_GOA, this sensing signal TP_GOA is contact panel periphery
Sensing signal supply circuit (not shown) interior during the sensing of contact panel provide to the common electrode of contact panel
The sensing signal of (not shown).Signal synchronous circuit 102 to during control signal TP_EN enable, that is,
During the sensing of contact panel, one end that control gate signal generating circuit 101 exports signal Gn synchronously outputs reality
In matter with sensing signal TP_GOA identical synchronizing signals.
Fig. 2 is the timing diagram of the gate driving circuit of one embodiment of the invention.Please reference picture 1 and Fig. 2 jointly, grid
Drive circuit 100 is to during sequentially operating in display and during sensing.During display is operated in, control signal TP_EN
In forbidden energy and signal generation circuit 101 is according to input signal Bi, the first clock signal CK and the second clock signal
XCK and export signal Gn at least once.During sensing is operated in, control signal TP_EN is in enable, the first sequential
Signal CK and the second clock signal XCK is in forbidden energy, therefore signal generation circuit 101 does not export grid letter now
Number Gn, but synchronously output the sensing signal TP_GOA that signal synchronous circuit 102 is received.
Hold above-mentioned, in the present embodiment, the first clock signal CK and the second clock signal XCK are anti-phase each other, therefore scheme
Second clock signal XCK waveform is only shown, in addition, the second clock signal XCK and sensing signal TP_GOA exist respectively in 2
During display and interior multiple enable during sensing, waveform quantity shown in Fig. 2 is only illustrating without limiting this hair
It is bright.Consequently, it is possible in during contact panel operates in sensing, the sensing letter on the signal and common electrode in its scan line
Number TP_GOA is substantially the same, that is to say, that the both ends of the parasitic capacitance between common electrode and scan line have substantial
Identical current potential, therefore influence of the described parasitic capacitance for sensing signal TP_GOA can be improved.
Fig. 3 is the circuit diagram of the gate driving circuit of one embodiment of the invention.Fig. 3 represents phase with identical label in Fig. 1
Same element or signal.As shown in figure 3, signal synchronous circuit 102 includes synchronization transistor MS.Synchronization transistor MS's
First end MS-1 is electrically connected to one end that signal generation circuit 101 exports signal Gn, synchronization transistor MS control
End MS-3 is to receive control signal TP_EN, and synchronization transistor MS the second end MS-2 is receiving sensing signal TP_GOA.
Fig. 3 is refer to, signal generation circuit 101 includes pull-up unit 10, drop-down unit 20 and driver element
30.Pull-up unit 10 pulls up signal S1 to receive input signal Bi and export.Driver element 30 is receiving and according to pull-up
Signal S1 and export signal Gn.Drop-down unit 20 is receiving pull-up signal S1 and signal Gn and to by institute
The pull-up signal S1 and signal Gn of reception are pulled down to reference potential Vgl.
Refer to Fig. 3, signal generation circuit 101 in the present embodiment exported for n-th grade of signal
Gn.Pull-up unit 10 includes the first transistor M1 and second transistor M2.The first transistor M1 first end M1-1 and
Two-transistor M2 first end M2-1 is electrically connected to each other and to receive input signal Bi.The first transistor M1 the second end M1-
2 and second transistor M2 the second end M2-2 is electrically connected to each other and to export pull-up signal S1.The first transistor M1's
Control terminal M1-3 to receive (n-1)th grade of signal Gn-1, second transistor M2 control terminal M2-3 to receive n-th+
1 grade of signal Gn+1, n is positive integer.Although the in addition, the first transistor in pull-up unit 10 described in the present embodiment
M1 and second transistor M2 first end M1-1 and M2-1 receives input signal Bi to common, but art technology
Personnel are appreciated that the first transistor M1 and second transistor M2 first end M1-1 and M2-1 can also be received respectively
Different input signal (not shown), therefore the present embodiment is only for example and is not used to the limitation present invention.
Fig. 3 is refer to, drop-down unit 20 includes third transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th
Transistor M6 and the first electric capacity C1.First electric capacity C1 first end C1-1 receives the first clock signal CK, third transistor M3
Control terminal M3-3 electrical connections second transistor M2 the second end M2-2, third transistor M3 first end M3-1 is electrically connected to
First electric capacity C1 the second end C1-2, the 4th transistor M4 first end M4-1 are electrically connected to second transistor M2 the second end
M2-2, the 4th transistor M4 control terminal M4-3 are electrically connected to third transistor M3 first end M3-1, the 5th transistor M5's
The control terminal M6-3 that control terminal M5-3 is electrically connected to third transistor M3 first end M3-1, the 6th transistor M6 receives second
Clock signal XCK, the 6th transistor M3 first end M6-1 are electrically connected to the 5th transistor M5 first end M5-1, and the 3rd is brilliant
Body pipe M3, the 4th transistor M4, the 5th transistor M5 and the 6th transistor M6 second end M3-2, M4-2, M5-2, M6-2
Receive reference potential Vgl.
Refer to Fig. 3, driver element 30 includes the 7th transistor M7 and the second electric capacity C2, and the of the 7th transistor M7
The second end M7-2 that one end M7-1 receives the first clock signal CK, the 7th transistor M7 electrically connects the first of the 6th transistor M6
End M6-1 simultaneously electrically connects second transistor M2 to export n-th grade of signal Gn, the 7th transistor M7 control terminal M7-3
The second end M2-2, the second electric capacity C2 first end C2-1 electrically connects the 7th transistor M7 control terminal M7-3, the second electric capacity
C2 the second end C2-2 is electrically connected to the 7th transistor M7 the second end M7-2.
The circuit framework of above-mentioned pull-up unit 10, drop-down unit 20 and driver element 30 is only the grid of the present invention
The preferred embodiment of signal generating circuit 101, is not intended to limit the invention.In addition, the technology of the present invention focuses on grid letter
The circuit framework and mode of operation of number synchronous circuit 102, and signal generation circuit 101 is to aid in illustrating, therefore
It is related to the details of operation of pull-up unit 10 in signal generation circuit 101, drop-down unit 20 and driver element 30 not
Repeat herein.In addition, any signal with pull-up unit 10, drop-down unit 20 and driver element 30 produces in every case
Circuit is suitable for being used cooperatively with signal synchronous circuit proposed by the invention, it is not necessary to extraly changes original grid
Pole signal generating circuit framework, which can also be reached, improves parasitic capacitance between common electrode and scan line for sensing signal institute band
The influence come.
Fig. 4 is the flow chart of the signal synchronous method of one embodiment of the invention.Above-mentioned gate driving circuit 100
It is same can to summarize a kind of signal for synchronism output sensing signal TP_GOA operation content during the sensing of contact panel
One step process, this signal synchronous method include step S401~S402 as shown in Figure 4.Please reference picture 1 and Fig. 4 jointly
To read the following description.Step S401:During the display of contact panel, there is provided input signal Bi, the first clock signal CK
And second clock signal XCK signal generation circuit 101 is exported at least
One signal Gn.Step S402:During the sensing of contact panel, forbidden energy the first clock signal CK and the second sequential letter
Number XCK, and control signal TP_EN and sensing signal TP_GOA are provided to signal synchronous circuit 102, so that grid is believed
Number generation circuit 101 synchronously outputs the sensing signal TP_GOA that signal synchronous circuit 102 is received.
Hold it is above-mentioned, in above-mentioned signal synchronous method, in a period of control signal TP_EN enables once, sense
It is multiple to survey signal TP_GOA enables.In addition, as shown in Fig. 2 the second clock signal XCK (or first clock signal CK) amplitude
More than sensing signal TP_GOA amplitude, therefore in general signal Gn amplitude can also be more than sensing signal TP_GOA
Amplitude.
In summary, signal generation circuit and grid are contained among gate driving circuit proposed by the invention
Pole signal synchronization circuit, and by signal synchronous circuit during the sensing of contact panel in come control gate signal produce
The output of raw circuit, it can synchronously output and sense so that signal generation circuit is interior during the sensing of contact panel
Substantially the same synchronizing signal of signal, therefore the scan line in contact panel can be made interior during the sensing of contact panel
Receive substantially with sensing signal identical synchronizing signal, thereby make the interior common electricity for receiving sensing signal during sensing
Parasitic capacitance both ends between pole and scan line have substantially the same current potential, thus can effectively improve this parasitic capacitance for
The influence of sensing signal, and make the transmission of sensing signal more efficiently.
Although the present invention is disclosed as above with preferred embodiment, so it is not limited to the present invention, people in the art
Member, without departing from the spirit and scope of the present invention, can make a little modification and retouching, therefore protection scope of the present invention is
Limited and be defined by the claim of the present invention.
Claims (10)
1. a kind of gate driving circuit, suitable for a contact panel, the gate driving circuit includes:
One signal generation circuit, to receive an input signal, one first clock signal and one second clock signal, and
The input signal, first clock signal and second sequential that interior foundation is received during a display of the contact panel
Signal and export a signal;And
One signal synchronous circuit, the signal generation circuit is electrically connected to, the signal synchronous circuit is at this
A control signal and a sensing signal are received during one sensing of contact panel, the signal synchronous circuit is in the control
The signal generation circuit is controlled to synchronously output the sensing signal during the enable of signal processed.
2. gate driving circuit as claimed in claim 1, the wherein gate driving circuit are sequentially operating in the display phase
Between and the sensing during, during the display is operated in, the control signal be in forbidden energy and the signal generation circuit according to
The signal is exported at least once according to the input signal, first clock signal and second clock signal, works as operation
During the sensing, the control signal is in enable, and first clock signal and second clock signal are in forbidden energy, and make
The signal generation circuit synchronously outputs the sensing signal that the signal synchronous circuit is received.
, should 3. gate driving circuit as claimed in claim 1, wherein the signal synchronous circuit include a synchronization transistor
Synchronization transistor has a first end, one second end and a control terminal, and the first end of the synchronization transistor electrically connects the grid
One end of pole signal generating circuit output signal, the control terminal of the synchronization transistor, should to receive the control signal
Second end of synchronization transistor is receiving the sensing signal.
4. gate driving circuit as claimed in claim 1, wherein the signal generation circuit include a pull-up unit, once
Unit and a driver element are drawn, the pull-up unit pulls up signal, the driver element to receive the input signal and export one
To receive and export the signal according to the pull-up signal, the drop-down unit is receiving the pull-up signal and the grid
Pole signal and the pull-up signal received and the signal are pulled down into a reference potential.
5. gate driving circuit as claimed in claim 4, wherein the signal generation circuit export the grid for n-th grade
Signal, pull-up unit include a first transistor and a second transistor, and the first transistor and the second transistor are each
Second crystal is electrically connected to from the first end with a first end, one second end and a control terminal, the first transistor
First end of pipe and to receive the input signal, second end of the first transistor is electrically connected to the second transistor
Second end and to export the pull-up signal, the control terminal of the first transistor to receive (n-1)th grade of signal,
For the control terminal of the second transistor to receive (n+1)th grade of signal, n is positive integer.
6. gate driving circuit as claimed in claim 5, the wherein drop-down unit include a third transistor, one the 4th crystal
Pipe, one the 5th transistor, one the 6th transistor and one first electric capacity, the third transistor, the 4th transistor, the 5th crystalline substance
Body pipe and the 6th transistor each have a first end, one second end and a control terminal, and wherein the one of first electric capacity
End receives first clock signal, and the control terminal of the third transistor electrically connects second end of the second transistor, and this
The first end of three transistors is electrically connected to the other end of first electric capacity, and the first end of the 4th transistor is electrically connected to
Second end of the second transistor, the control terminal of the 4th transistor are electrically connected to the first end of the third transistor,
The control terminal of 5th transistor is electrically connected to the first end of the third transistor, the control termination of the 6th transistor
Receive second clock signal, the first end of the 6th transistor is electrically connected to the first end of the 5th transistor, and the 3rd
Transistor, the 4th transistor, these second ends of the 5th transistor and the 6th transistor receive the reference potential.
7. gate driving circuit as claimed in claim 6, the wherein driver element include one the 7th transistor and one second
Electric capacity, the 7th transistor have a first end, one second end and a control terminal, and the first end of the 7th transistor receives
First clock signal, second end of the 7th transistor electrically connect the first end of the 6th transistor and to export this
N-th grade of signal, the control terminal of the 7th transistor electrically connect second end of the second transistor, second electric capacity
Wherein one end electrically connect the control terminal of the 7th transistor, the other end of second electric capacity is electrically connected to the 7th crystal
Second end of pipe.
8. a kind of signal synchronous method, suitable for the gate driving circuit of a contact panel, the gate driving circuit includes
One signal generation circuit and a signal synchronous circuit, the signal synchronous method include:
During a display of the contact panel, there is provided an input signal, one first clock signal and one second clock signal
The signal generation circuit is set to the signal generation circuit and according to this to export an at least signal;And
During a sensing of the contact panel, forbidden energy first clock signal and second clock signal, and a control is provided
Signal processed and a sensing signal are to the signal synchronous circuit, so that the signal generation circuit synchronously outputs the grid
The sensing signal that pole signal synchronization circuit is received.
9. signal synchronous method as claimed in claim 8, wherein in during an enable of the control signal, the sense
Signal is surveyed to be enabled repeatedly.
10. signal synchronous method as claimed in claim 8, the wherein amplitude of the signal are more than the sensing signal
Amplitude.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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TW104123445A TWI552131B (en) | 2015-07-20 | 2015-07-20 | Gate driving circuit and method of synchronizing gate signal thereof |
TW104123445 | 2015-07-20 |
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Publication Number | Publication Date |
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CN105118415A CN105118415A (en) | 2015-12-02 |
CN105118415B true CN105118415B (en) | 2018-01-09 |
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CN201510609515.6A Active CN105118415B (en) | 2015-07-20 | 2015-09-23 | Grid driving circuit and grid signal synchronization method thereof |
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CN (1) | CN105118415B (en) |
TW (1) | TWI552131B (en) |
Families Citing this family (2)
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TWI581155B (en) | 2016-03-23 | 2017-05-01 | 友達光電股份有限公司 | Touch display panel and controlling method thereof |
TWI613640B (en) | 2017-02-24 | 2018-02-01 | 友達光電股份有限公司 | Touch display apparatus |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102693703A (en) * | 2011-03-25 | 2012-09-26 | 乐金显示有限公司 | Display with integrated touch sensor and driving method thereof |
CN103870055A (en) * | 2012-12-11 | 2014-06-18 | 乐金显示有限公司 | Display device with integrated touch screen and method of driving same |
KR20140086192A (en) * | 2012-12-28 | 2014-07-08 | 엘지디스플레이 주식회사 | Shift register and method for driving the same |
CN103970386A (en) * | 2013-01-30 | 2014-08-06 | 乐金显示有限公司 | Display device integrated with touch screen and method of driving the same |
CN104345490A (en) * | 2013-08-01 | 2015-02-11 | 三星显示有限公司 | Liquid crystal display device integrated with touch sensor |
CN104516604A (en) * | 2013-10-04 | 2015-04-15 | 三星显示有限公司 | Liquid crystal display with touch sensor, and controller |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI549032B (en) * | 2014-10-28 | 2016-09-11 | 宏碁股份有限公司 | Touch display apparatus and operation method of touch device thereof |
-
2015
- 2015-07-20 TW TW104123445A patent/TWI552131B/en active
- 2015-09-23 CN CN201510609515.6A patent/CN105118415B/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102693703A (en) * | 2011-03-25 | 2012-09-26 | 乐金显示有限公司 | Display with integrated touch sensor and driving method thereof |
CN103870055A (en) * | 2012-12-11 | 2014-06-18 | 乐金显示有限公司 | Display device with integrated touch screen and method of driving same |
KR20140086192A (en) * | 2012-12-28 | 2014-07-08 | 엘지디스플레이 주식회사 | Shift register and method for driving the same |
CN103970386A (en) * | 2013-01-30 | 2014-08-06 | 乐金显示有限公司 | Display device integrated with touch screen and method of driving the same |
CN104345490A (en) * | 2013-08-01 | 2015-02-11 | 三星显示有限公司 | Liquid crystal display device integrated with touch sensor |
CN104516604A (en) * | 2013-10-04 | 2015-04-15 | 三星显示有限公司 | Liquid crystal display with touch sensor, and controller |
Also Published As
Publication number | Publication date |
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CN105118415A (en) | 2015-12-02 |
TWI552131B (en) | 2016-10-01 |
TW201705108A (en) | 2017-02-01 |
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