CN105097697B - A kind of device architecture that realizing high voltage integratecCMOS devices and preparation method - Google Patents
A kind of device architecture that realizing high voltage integratecCMOS devices and preparation method Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 6
- 238000000034 method Methods 0.000 claims abstract description 62
- 238000009413 insulation Methods 0.000 claims abstract description 11
- 238000002955 isolation Methods 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 53
- 229920005591 polysilicon Polymers 0.000 claims description 52
- 239000000758 substrate Substances 0.000 claims description 44
- 239000002184 metal Substances 0.000 claims description 31
- 229910052751 metal Inorganic materials 0.000 claims description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- 238000004528 spin coating Methods 0.000 claims description 10
- 238000011049 filling Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims description 3
- 238000000992 sputter etching Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract
The present invention relates to semiconductor devices manufacture technology fields, more particularly to a kind of device architecture for realizing high voltage integratecCMOS devices and preparation method, the present invention forms a kind of cmos device structure by deep plough groove etched technique, realize the problem that cannot achieve high drive transistor under advanced technologies, three-dimensional grid structure transistor is realized using deep trench isolation technique, the actual channel length and gate insulation layer thickness of transistor are increased under advanced technologies, to enable transistor to work normally at higher voltages, enhance its voltage driving capability.The present invention realizes the method compatibility standard CMOS technology of high voltage CMOS device using deep trench isolation technique, and processing step is simple, and cost is relatively low, and area is small, it can be achieved that Advanced CMOS Process integrates the function of high voltage drive.
Description
Technical field
The present invention relates to semiconductor devices manufacture technology fields, and in particular to a kind of integrated high voltage drive of realization cmos device
Dynamic method.
Background technique
As integrated circuit continues to high speed, low-power consumption, the development in low-voltage direction, the requirement to integrated circuit is more next
It is higher, while also constantly pushing the rapid development of integrated circuit processing technique, currently advanced silicon CMOS integrated technique into
Enter 28 nanometers and 14 nm regimes, and gradually moves towards the more advanced process such as 10 nanometers.As process constantly reduces,
Gate insulation layer is more and more thinner, and channel is shorter and shorter, and supply voltage must reduce, and otherwise transistor will cause because of voltage is excessive
Puncture and fails.Since the voltage driving capability of the transistor when voltage reduces also constantly is reducing, high pressure is driven under normal conditions
Dynamic transistor is difficult to realize under advanced technologies.For example, under 40nm and 28nm processing procedure, most of I/O in 2.5V or
It drives under 3.3V voltage, in order to realize the even higher voltage driving of 5V, just must additionally increase in addition a independent
Chip, this is a challenge to the trend of SoC (System-On-a-Chip).
Therefore, how to increase independent chip while CMOS transistor being made to have higher driving voltage to become art technology
The a great problem that personnel face.
Summary of the invention
In view of the above-mentioned problems, the present invention proposes a kind of method realized cmos device and integrate high voltage drive, by grid
Polar region carries out the high drive that deep trench isolation technique realizes cmos device, the technical solution specifically:
A kind of preparation method of device architecture that realizing high voltage integratecCMOS devices, wherein the described method includes:
Deep trench is formed in epitaxial layer region；
A gate oxide is deposited in the bottom and side wall of deep trench and the upper surface of cmos device；
It is deposited in the deep trench of gate oxide and fills polysilicon, and simultaneously in the gate oxide of cmos device upper surface
Surface deposits a polysilicon layer；
The upper surface of polysilicon layer described in planarization process；
A polysilicon oxide layer is adhered in upper surface after the planarization of polysilicon layer；
The ion implanting of source-drain area is carried out, source electrode and drain electrode is formed；
Metal pins are formed in grid, source electrode and drain electrode, form cmos device.
The method of above-mentioned realization cmos device, wherein in the method that epitaxial layer forms deep trench further include:
One photoresist layer of spin coating covers the upper surface of the substrate；
Using patterned photoresist as exposure mask, etching forms deep trench.
The method of above-mentioned realization cmos device, wherein the deep trench is formed using the method for deep reaction ion etching.
The method of above-mentioned realization cmos device, wherein the bottom and side wall of be set forth in deep trench and cmos device
The method that upper surface deposits a gate oxide further include:
A sacrificial oxide layer is deposited in the bottom and side wall of deep trench and the upper surface of cmos device；
Remove the sacrificial oxide layer；
A gate oxide is deposited in the bottom and side wall of deep trench and the upper surface of cmos device.
The method of above-mentioned realization cmos device, wherein according to the thickness for needing to control the gate oxide of voltage.
The method of above-mentioned realization cmos device, wherein the polysilicon is planarized using the method for chemically mechanical polishing
The upper surface of layer.
The method of above-mentioned realization cmos device, wherein the ion implanting for carrying out source-drain area forms source electrode and drain electrode
Method further include:
One layer photoresist of spin coating is covered in the upper surface of the substrate；
Using patterned photoresist as exposure mask, ion implanting forms source region and drain region.
The method of above-mentioned realization cmos device, wherein be set forth in grid, source electrode and drain electrode form metal pins, are formed
The method of cmos device further include:
A dielectric isolation layer is covered in the upper surface of the substrate；
The SI semi-insulation separation layer that etching removes above the source region, drain region and gate regions forms several openings；
In filling metal in the opening, to form Ohmic contact；
A metal is deposited in the upper surface of the filling metal, if dry sleeve is formed, by the source electrode, grid, drain electrode
It electrically draws, forms cmos device.
The method of above-mentioned realization cmos device, wherein the step of the upper surface of the planarization polysilicon layer also
Include:
It removes and is higher than the more of the upper surface of substrate part in the polysilicon and the deep trench of the upper surface of substrate
Crystal silicon.
A kind of device architecture for realizing high voltage integratecCMOS devices, wherein the structure includes:
Substrate is provided with deep groove structure, and active area is arranged in the two sides of the deep groove structure；
Polysilicon gate is full of the deep groove structure；
Gate oxide is arranged between the polysilicon gate and the substrate, by the substrate and the polysilicon gate
And source region insulation；
Insulating layer covers the upper surface of the substrate, gate insulation layer and polysilicon gate；
Multiple metal pins are set on the insulating layer, and are located at the active area and the polysilicon gate
Top electrically draws grid, source area and drain region.
Above-mentioned device architecture, wherein the depth of the deep trench is greater than the depth of the source region.
Above-mentioned device architecture, wherein several openings are provided on the insulating layer, the opening is located at gate regions, source
Insulating layer above polar region and drain region.
Above-mentioned device architecture, wherein metal is filled in the opening, to form Ohm connection.
Above-mentioned device architecture, wherein the metal is fitted closely with the metal pins.
The present invention have the advantage that and using the present invention reach the utility model has the advantages that
The present invention realizes that cmos device drives under high pressure by deep trench isolation technique, effectively overcomes in advanced technologies
Under cannot achieve high drive transistor problem, actual channel length and the grid that transistor is increased under advanced technologies are exhausted
Edge layer thickness enhances its voltage driving capability so that transistor be enable to work normally at higher voltages.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, the present invention and its feature, outer
Shape and advantage will become more apparent upon.Identical label indicates identical part in all the attached drawings.Not deliberately proportionally
Draw attached drawing, it is preferred that emphasis is show the gist of the present invention.
Fig. 1 is the flow chart of present invention production cmos device；
Fig. 2 is the structural schematic diagram of one photoresist layer of spin coating on the substrate provided in one embodiment of the invention；
Fig. 3 is to form the structural schematic diagram of deep trench in epitaxial layer region in one embodiment of the invention；
Fig. 4 is that a gate oxide is covered in one embodiment of the invention in the upper surface of substrate and the side wall of deep trench and bottom
Structural schematic diagram；
Fig. 5 is that deposit polycrystalline silicon layer in gate oxide upper surface and is filled the structure of deep trench and shown in one embodiment of the invention
It is intended to；
Fig. 6 is that structural schematic diagram after polysilicon layer is planarized in one embodiment of the invention；
Fig. 7 is to adhere to polysilicon oxide layer structural representation after substrate and zanjon rooved face in one embodiment of the invention
Figure；
Fig. 8 is the structure in one embodiment of the invention in one layer photoresist of polysilicon oxidation layer surface spin coating and after patterning
Schematic diagram；
Fig. 9 is Yu Yuanqu in one embodiment of the invention, structural schematic diagram after the ion implanting of drain region；
Figure 10 be in one embodiment of the invention Ohm connection and in source electrode, drain and gate formed metal gasket after structure show
It is intended to.
Specific embodiment
Structural schematic diagram shown in Figure 1, the present invention provide a kind of device architecture for realizing high voltage integratecCMOS devices
Preparation method, firstly, by etching technics epitaxial layer region formed deep trench；Continue at the bottom and side wall of deep trench with
And the upper surface of cmos device deposits a gate oxide；Continue to be deposited in the deep trench of gate oxide and fill polysilicon, and is same
When in cmos device upper surface gate oxide surface deposit a polysilicon layer；Continue polysilicon layer described in planarization process
Upper surface；A polysilicon oxide layer is adhered in upper surface after continuing at the planarization of polysilicon layer；Continue source-drain area from
Son injection, forms source electrode and drain electrode；Finally, forming metal pins in grid, source electrode and drain electrode, cmos device is formed.
As a preferred embodiment of the invention, in the method that epitaxial layer forms deep trench further include:
The upper surface of one photoresist layer of spin coating covering substrate；
Using patterned photoresist as exposure mask, etching forms deep trench.
As a preferred embodiment of the invention, deep trench is formed using the method for deep reaction ion etching.
As a preferred embodiment of the invention, deposited in the bottom and side wall of deep trench and the upper surface of cmos device
The method of one gate oxide further include:
A sacrificial oxide layer is deposited in the bottom and side wall of deep trench and the upper surface of cmos device；
Remove the sacrificial oxide layer；
A gate oxide is deposited in the bottom and side wall of deep trench and the upper surface of cmos device.
Why one layer of sacrificial oxide layer is deposited first, it is therefore intended that the defect on the capture surface Si.
As a preferred embodiment of the invention, according to the thickness for needing to control gate oxide of voltage.
As a preferred embodiment of the invention, using the upper table of the method planarization polysilicon layer of chemically mechanical polishing
Face.
As a preferred embodiment of the invention, the ion implanting of source-drain area is carried out, forms the method for source electrode and drain electrode also
Include:
One layer photoresist of spin coating is covered in the upper surface of substrate；
Using patterned photoresist as exposure mask, ion implanting forms source region and drain region.
As a preferred embodiment of the invention, be set forth in grid, source electrode and drain electrode form metal pins, form CMOS device
The method of part further include:
A dielectric isolation layer is covered in the upper surface of substrate；
SI semi-insulation separation layer above etching removal source region, drain region and gate regions forms several openings；
In filling metal in opening, to form Ohmic contact；
A metal is deposited in the upper surface of filling metal, forms several pins, electrically by the source electrode, grid, drain electrode
It draws, forms cmos device.
As a preferred embodiment of the invention, the step of planarizing the upper surface of polysilicon layer further include:
Remove the polysilicon for being higher than upper surface of substrate part in the polysilicon and the deep trench of upper surface of substrate.
It is described in detail so that one prepares NMOS device as an example below:
Structure shown in Figure 2 provides a substrate 1 first, it is preferred that and it is silicon substrate, continues to preset gate regions in substrate,
Patterned photoresist layer 2 is formed in one layer photoresist of upper surface of substrate spin coating, and in the top of preset gate regions.
Structural schematic diagram shown in Figure 3, using patterned photoresist as exposure mask, in preset gate regions using deep reaction
The method that ion is explained carries out deep plough groove etched, structural schematic diagram described in formation Fig. 3 to substrate.
Structure shown in Figure 4 adheres to one layer of gate oxide in the upper surface of silicon substrate and the side wall of deep trench and bottom
3, it is notable that in order to capture the defect on the surface Si, before adhering to gate oxide, firstly, in the upper surface of silicon substrate
And one sacrificial oxide layer of side wall and bottom surface attachment of deep trench, sacrificial oxide layer is then removed, finally, in the upper surface of silicon substrate
And one layer of gate oxide of side wall and bottom attachment of deep trench.
Structure shown in Figure 5 fills polysilicon gate 4, in deep trench to form the grid of NMOS device.
Structural schematic diagram shown in Figure 6 planarizes polysilicon gate 4, keeps the upper surface of silicon substrate exposed, and make zanjon
The upper surface of polysilicon gate and the upper surface of silicon substrate maintain an equal level in slot.
Structural schematic diagram shown in Figure 7, in the upper surface covering one of polysilicon layer in silicon substrate upper surface and deep trench
Polysilicon oxide layer 5, to buffer isolation polysilicon.
Structural schematic diagram shown in Figure 8, in one layer photoresist of upper surface spin coating of polysilicon oxide layer, in gate regions
Two sides preset source region and drain region position, and according to grid, source region and the position in drain region pattern photoresist layer 6.
Structure shown in Figure 9 carries out N+ ion implanting to preset source region and drain region, forms source area and drain region.
Structure shown in Figure 10 covers an insulating layer 7 in the upper surface of substrate for being formed with source area and drain region first,
It it is then spin coated onto the upper surface of layer photoresist covering insulating layer 7, patterns photoresist, etching source area, drain region and grid
The insulating layer of top forms an opening above grid, source area and drain region, forms ohm in filling metal in opening
Connection continues to deposit a metal in the upper surface of the metal 8 of filling, forms pin, and grid, source area and drain region is electrical
It draws.
Method in based on the above embodiment, present invention simultaneously discloses a kind of devices for realizing high voltage integratecCMOS devices
Structure, i.e., structure shown in Figure 10, the structure include substrate 1, polysilicon layer 4, gate oxide 3, insulating layer 7 and multiple metals
Pin 8.
It is provided with deep groove structure on substrate 1, and active area is set in the two sides of deep groove structure.Polysilicon gate 4 is full of
The deep groove structure being arranged on substrate.Gate oxide 3 is arranged between polysilicon gate 4 and substrate 1 and source region, by the substrate
It insulate with the polysilicon gate and source region.Insulating layer 7 covers the upper surface of substrate, gate insulation layer and polysilicon gate.Multiple gold
Belong to pin 8 to be set on insulating layer, and be located above active area and polysilicon gate, by grid, source area and drain electrode
It electrically draws in area.
In the present invention, the depth of deep trench is greater than the depth of source region.
As a preferred embodiment of the invention, several openings are provided on insulating layer 7, opening is located at gate regions, source electrode
Insulating layer above area and drain region.
As a preferred embodiment of the invention, be open interior filling metal, to form Ohm connection.
As a preferred embodiment of the invention, the metal is fitted closely with the metal pins.
In conclusion the present invention makes a kind of cmos device structure by deep plough groove etched technique, realize in advanced work
The problem that cannot achieve the transistor of high drive under skill realizes three-dimensional grid structure transistor using deep trench isolation technique,
The actual channel length and gate insulation layer thickness that transistor is increased under advanced technologies, to enable transistor in high voltage
Lower normal work, enhances its voltage driving capability.The method that the present invention realizes high voltage CMOS device using deep trench isolation technique
Compatibility standard CMOS technology, processing step is simple, and cost is relatively low, and area is small, it can be achieved that Advanced CMOS Process integrates high voltage drive
Dynamic function.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, devices and structures not described in detail herein should be understood as gives reality with the common mode in this field
It applies；Anyone skilled in the art, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this is not affected the essence of the present invention.Therefore, anything that does not depart from the technical scheme of the invention, foundation
Technical spirit of the invention any simple modifications, equivalents, and modifications made to the above embodiment, still fall within the present invention
In the range of technical solution protection.
Claims (14)
1. a kind of preparation method for realizing high voltage integratecCMOS devices, which is characterized in that the described method includes:
Deep trench is formed in epitaxial layer region；
A gate oxide is deposited in the bottom and side wall of deep trench and the upper surface of cmos device；
Be deposited in the deep trench of gate oxide and fill polysilicon, and simultaneously in cmos device upper surface gate oxide surface
Deposit a polysilicon layer；
The upper surface of polysilicon layer described in planarization process；
A polysilicon oxide layer is adhered in upper surface after the planarization of polysilicon layer；
The ion implanting of source-drain area is carried out, source electrode and drain electrode is formed；
Metal pins are formed in grid, source electrode and drain electrode, form cmos device.
2. realizing the method for cmos device as described in claim 1, which is characterized in that in the method that epitaxial layer forms deep trench
Further include:
The upper surface of one photoresist layer of spin coating covering substrate；
Using patterned photoresist as exposure mask, etching forms deep trench.
3. realizing the method for cmos device as claimed in claim 2, which is characterized in that using the method for deep reaction ion etching
Form the deep trench.
4. realizing the method for cmos device as described in claim 1, which is characterized in that the bottom and side wall of be set forth in deep trench
And the method that the upper surface of cmos device deposits a gate oxide further include:
A sacrificial oxide layer is deposited in the bottom and side wall of deep trench and the upper surface of cmos device；
Remove the sacrificial oxide layer；
A gate oxide is deposited in the bottom and side wall of deep trench and the upper surface of cmos device.
5. realizing the method for cmos device as claimed in claim 4, which is characterized in that need to control the grid according to voltage
The thickness of oxide layer.
6. realizing the method for cmos device as described in claim 1, which is characterized in that flat using the method for chemically mechanical polishing
The upper surface of the smoothization polysilicon layer.
7. realizing the method for cmos device as described in claim 1, which is characterized in that the ion note for carrying out source-drain area
Enter, the method for forming source electrode and drain electrode further include:
One layer photoresist of spin coating is covered in the upper surface of substrate；
Using patterned photoresist as exposure mask, ion implanting forms source region and drain region.
8. realizing the method for cmos device as described in claim 1, which is characterized in that be set forth in grid, source electrode and drain electrode shape
At metal pins, the method for forming cmos device further include:
A dielectric isolation layer is covered in the upper surface of substrate；
The SI semi-insulation separation layer that etching removes above the source region, drain region and gate regions forms several openings；
In filling metal in the opening, to form Ohmic contact；
Deposit a metal in the upper surface of the filling metal, if forming dry sleeve, electrically by the source electrode, grid, drain electrode
It draws, forms cmos device.
9. realizing the method for cmos device as described in claim 1, which is characterized in that the planarization polysilicon layer
The step of upper surface further include:
Remove the polysilicon for being higher than the upper surface of substrate part in the polysilicon and the deep trench of upper surface of substrate.
10. a kind of device architecture for realizing high voltage integratecCMOS devices, which is characterized in that the structure includes:
Substrate is provided with deep groove structure, and active area is arranged in the two sides of the deep groove structure；
Polysilicon gate is full of the deep groove structure；
Gate oxide is arranged between the polysilicon gate and the substrate, by the substrate and the polysilicon gate and
Source region insulation；
Insulating layer covers the upper surface of the substrate, gate insulation layer and polysilicon gate；
Multiple metal pins are set on the insulating layer, and are located above the active area and the polysilicon gate,
Grid, source area and drain region electrically to be drawn.
11. device architecture as claimed in claim 10, which is characterized in that the depth of the deep trench is greater than the depth of the source region
Degree.
12. device architecture as claimed in claim 10, which is characterized in that several openings are provided on the insulating layer, it is described
Opening is located at the insulating layer above gate regions, source area and drain region.
13. device architecture as claimed in claim 12, which is characterized in that metal is filled in the opening, to form ohm company
It connects.
14. device architecture as claimed in claim 13, which is characterized in that the metal is fitted closely with the metal pins.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101410987A (en) * | 2006-03-28 | 2009-04-15 | Nxp股份有限公司 | Trench-gate semiconductor device and method of fabrication thereof |
| CN102194694A (en) * | 2010-03-05 | 2011-09-21 | 世界先进积体电路股份有限公司 | Method for manufacturing groove-type metal-oxide-semiconductor field-effect transistor |
| CN103413765A (en) * | 2013-08-27 | 2013-11-27 | 矽力杰半导体技术(杭州)有限公司 | Groove MOSFET device and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7585705B2 (en) * | 2007-11-29 | 2009-09-08 | Alpha & Omega Semiconductor, Inc. | Method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop |
-
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101410987A (en) * | 2006-03-28 | 2009-04-15 | Nxp股份有限公司 | Trench-gate semiconductor device and method of fabrication thereof |
| CN102194694A (en) * | 2010-03-05 | 2011-09-21 | 世界先进积体电路股份有限公司 | Method for manufacturing groove-type metal-oxide-semiconductor field-effect transistor |
| CN103413765A (en) * | 2013-08-27 | 2013-11-27 | 矽力杰半导体技术(杭州)有限公司 | Groove MOSFET device and manufacturing method thereof |
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