CN105097688A - Semiconductor device and manufacturing method thereof, electronic apparatus - Google Patents
Semiconductor device and manufacturing method thereof, electronic apparatus Download PDFInfo
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Abstract
The invention provides a semiconductor device and a manufacturing method thereof, and an electronic apparatus. The method comprises the following steps of providing a semiconductor substrate having a first transistor zone and a second transistor zone; forming a dummy gate structure on the semiconductor substrate, wherein the dummy gate structure comprises a high k dielectric layer and a sacrificial gate electrode layer stacked from the bottom up; forming an interlayer dielectric layer on the semiconductor substrate and covering the dummy gate structure; removing the sacrificial gate electrode layer located on the first transistor zone to obtain a first gate groove; making a sacrificial material layer grow in an epitaxial growth way on the top of the dummy gate structure located in the second transistor zone; depositing a first metal gate material layer and fully filling the first gate groove; removing the sacrificial material layer and the sacrificial gate electrode layer located on the second transistor zone to obtain a second gate groove; depositing a second metal gate material layer and fully filling the second gate groove. A gate height decrease caused by a loss of the interlayer dielectric layer during a grinding process can be prevented. The gate resistance is further reduced.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of semiconductor device and manufacture method, electronic installation.
Background technology
In the manufacturing process of integrated circuit of future generation, for the making of the grid of complementary metal oxide semiconductors (CMOS) (CMOS), usually adopt high k-metal gate process.For the transistor arrangement had compared with the process node of fractional value, described high k-metal gate process is generally post tensioned unbonded prestressed concrete (gate-last) technique, its typical implementation process comprises: first, form dummy gate structure on a semiconductor substrate, described dummy gate structure is made up of boundary layer from bottom to top, high k dielectric layer, cover layer and sacrificial gate dielectric layer; Then, form gate pitch wall construction in the both sides of described dummy gate structure, remove the sacrificial gate dielectric layer in described dummy gate structure afterwards, between described gate pitch wall construction, leave a groove; Then, in described groove, deposit workfunction layers (workfunctionmetallayer), barrier layer (barrierlayer) and soakage layer (wettinglayer) successively; Finally carry out the filling of metal gate (being generally aluminium).
Above-mentioned technical process can cause the decline of comparatively serious gate height, when contact hole is shared in follow-up formation, will cause the loss of substrate silicon material, affect the performance of CMOS.The reason causing described gate height to decline has two: the first, after forming the gate pitch wall construction of described dummy gate structure and both sides, form contact etch stop layer and interlayer dielectric layer successively on the semiconductor substrate, then cmp is implemented, to expose the top of described dummy gate structure, this process of lapping also can remove the described dummy gate structure of part, causes the decline of gate height thus; Second, because the PMOS part of CMOS and the metal gate structure of NMOS part need to have different work functions, therefore, the metal gate structure of the two is formed respectively, need execution twice or process of lapping repeatedly removing in the groove formed after described dummy gate structure in the process forming workfunction layers, barrier layer, soakage layer and metal gate successively, these process of lapping also can cause the decline of gate height.
Therefore, need to propose a kind of method, to solve the problem.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprise: the Semiconductor substrate with first crystal area under control and transistor seconds district is provided, be formed on the semiconductor substrate and comprise stacked high k dielectric layer and the dummy gate structure of sacrificial gate dielectric layer from bottom to top; Form interlayer dielectric layer on the semiconductor substrate, to cover described dummy gate structure; Remove the sacrificial gate dielectric layer being arranged in the dummy gate structure in described first crystal area under control, obtain first grid groove; Be positioned at the top epitaxial growth sacrificial material layer of dummy gate structure in described transistor seconds district; Deposit the first metal gate material layer, to fill described first grid groove completely; Remove described sacrificial material layer and be arranged in the sacrificial gate dielectric layer of dummy gate structure in described transistor seconds district, obtain second gate groove; Deposit the second metal gate material layer, to fill described second gate groove completely.
In one example, described the first transistor is PFET, and described transistor seconds is NFET, or described the first transistor is NFET, and described transistor seconds is PFET.
In one example, between described high k dielectric layer and described Semiconductor substrate, be also formed with boundary layer, between described high k dielectric layer and described sacrificial gate dielectric layer, be also formed with cover layer.
In one example, described sacrificial material layer is silicon layer, germanium silicon layer or carbon silicon layer, and thickness is 50-300 dust.
In one example, after forming described interlayer dielectric layer, also comprise the step of execution first cmp, until expose the top of described dummy gate structure.
In one example, after depositing described first metal gate material layer, the step of execution second cmp is also comprised, until expose the top of described sacrificial material layer.
In one example, after depositing described second metal gate material layer, the step of execution the 3rd cmp is also comprised, until expose the top of described interlayer dielectric layer.
In one example, before depositing described first metal gate material layer, be also included in the step that the first workfunction setting metal layer, barrier layer and soakage layer are formed successively on the sidewall of described first grid groove and bottom; Before depositing described second metal gate material layer, be also included in the step that the second workfunction setting metal layer, described barrier layer and described soakage layer are formed successively on the sidewall of described second gate groove and bottom.
In one embodiment, the present invention also provides a kind of semiconductor device adopting said method to manufacture.
In one embodiment, the present invention also provides a kind of electronic installation, and described electronic installation comprises described semiconductor device.
According to the present invention, due to the existence of described sacrificial material layer, the loss that described interlayer dielectric layer caused by described process of lapping can be avoided and the reduction of the gate height caused, reduce resistance further.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 G for according to an exemplary embodiment of the present one the schematic cross sectional view of device that obtains respectively of the step implemented successively of method;
Fig. 2 is the flow chart of step implemented successively of method of according to an exemplary embodiment of the present.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to explain semiconductor device and manufacture method, the electronic installation of the present invention's proposition.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
[exemplary embodiment one]
With reference to Figure 1A-Fig. 1 G, the schematic cross sectional view of the device that the step that the method that illustrated therein is according to an exemplary embodiment of the present is implemented successively obtains respectively.
First, as shown in Figure 1A, provide Semiconductor substrate 100, the constituent material of Semiconductor substrate 100 can adopt unadulterated monocrystalline silicon, monocrystalline silicon, silicon-on-insulator (SOI) etc. doped with impurity.Exemplarily, in the present embodiment, Semiconductor substrate 100 selects single crystal silicon material to form.In Semiconductor substrate 100, be formed with isolation structure 101, exemplarily, isolation structure 101 is that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure.Semiconductor substrate 100 is divided into the first transistor (FET1) district and transistor seconds (FET2) district by isolation structure 101, wherein, described the first transistor is PFET, described transistor seconds is NFET, or, described the first transistor is NFET, and described transistor seconds is PFET.In Semiconductor substrate 100, also be formed with various trap (well) structure, in order to simplify, be omitted in diagram.
Be formed with dummy gate structure 102 on a semiconductor substrate 100, as an example, dummy gate structure 102 can comprise the high k dielectric layer 102a and sacrificial gate dielectric layer 102b that stack gradually from bottom to top.The material of high k dielectric layer 102a can comprise hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc., particularly preferably is hafnium oxide, zirconia and aluminium oxide.The material of sacrificial gate dielectric layer 102b can comprise polysilicon.As another example, also boundary layer is formed with between high k dielectric layer 102a and Semiconductor substrate 100, between high k dielectric layer 102a and sacrificial gate dielectric layer 102b, also be formed with cover layer (cappinglayer), in order to simplify, be omitted in diagram.Boundary layer can improve the interfacial characteristics between high k dielectric layer 102a and Semiconductor substrate 100, and cover layer can suppress the metal gate material in the metal gate structure of follow-up formation (being generally aluminium) to the diffusion in high k dielectric layer 102a.The material of boundary layer can comprise Si oxide (SiO
x).Tectal material can comprise titanium nitride and tantalum nitride.Form the various suitable technology that above each layer can adopt those skilled in the art to have the knack of, thermal oxidation technology is such as adopted to form boundary layer, adopt chemical vapor deposition method to form high k dielectric layer 102a and sacrificial gate dielectric layer 102b, adopt physical gas-phase deposition, chemical vapor deposition method or atom layer deposition process to form cover layer.
In addition, exemplarily, be formed with side wall construction 103 in the both sides of dummy gate structure 102, wherein, side wall construction 103 at least comprises oxide skin(coating) and/or nitride layer.The method forming side wall construction 103 is conventionally known to one of skill in the art, is no longer repeated at this.
Then, as shown in Figure 1B, form interlayer dielectric layer 105 on a semiconductor substrate 100, cover dummy gate structure 102 and side wall construction 103.Then, cmp is performed, until expose the top of dummy gate structure 102.Before formation interlayer dielectric layer 105, contact etch stop layer 104 can also be formed on a semiconductor substrate 100, cover dummy gate structure 102 and side wall construction 103.The various suitable technique adopting those skilled in the art to have the knack of forms contact etch stop layer 104 and interlayer dielectric layer 105 respectively, such as, adopt conformal deposition process to form contact etch stop layer 104, adopt chemical vapor deposition method to form interlayer dielectric layer 105; Wherein, the material of contact etch stop layer 104 can select silicon nitride (SiN), and the material of interlayer dielectric layer 105 can select oxide.
Then, as shown in Figure 1 C, remove the sacrificial gate dielectric layer 102b being arranged in the dummy gate structure 102 in FET1 district, obtain first grid groove 106.Employing traditional handicraft completes the removal to sacrificial gate dielectric layer 102b, such as dry etching or wet etching, wherein, the etching gas that dry etching uses can be fluorine-based, chloro or bromine-based gas, and the corrosive liquid that wet etching uses can be tetramethyl ammonium hydroxide solution (TMAH).Then, perform wet cleaning processes, to remove etch residues in first grid groove 106 and impurity.Before the described removal of enforcement, form the photoresist layer of patterning, only to cover FET2 district; After the described removal of enforcement, cineration technics is adopted to remove described photoresist layer.
Then, as shown in figure ip, the top epitaxial growth sacrificial material layer 107 of dummy gate structure 102 in FET2 district is being positioned at.Exemplarily, sacrificial material layer 107 can be silicon layer, germanium silicon layer, carbon silicon layer etc., and thickness is 50-300 dust.Described epitaxial growth technology can adopt the one in low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) and molecular beam epitaxy (MBE).
Then, as referring to figure 1e, the first metal gate material layer 108 is deposited, to fill first grid groove 106 completely.Then, cmp is performed, until expose the top of sacrificial material layer 107.Before the described deposition of enforcement, also be included in the step that the first workfunction setting metal layer, barrier layer and soakage layer are formed successively on the sidewall of first grid groove 106 and bottom, in order to simplify, not give in figure and the first workfunction setting metal layer, barrier layer and soakage layer are shown.Wherein, first workfunction setting metal layer comprises one or more layers metal or metallic compound, if FET1 is NFET, then the constituent material of the first workfunction setting metal layer is the metal material being applicable to NFET, comprise titanium, tantalum, aluminium, zirconium, hafnium and alloy thereof, also comprise the carbide of above-mentioned metallic element, nitride etc., if FET1 is PFET, then the constituent material of the first workfunction setting metal layer is the metal material being applicable to PFET, comprise titanium, ruthenium, palladium, platinum, tungsten and alloy thereof, also comprise the carbide of above-mentioned metallic element, nitride etc.; The material on barrier layer comprises tantalum nitride or titanium nitride; The material of soakage layer comprises titanium or titanium-aluminium alloy; The constituent material of the first metal gate material layer 108 comprises aluminium.Adopt atom layer deposition process or physical gas-phase deposition to form the first workfunction setting metal layer, adopt atom layer deposition process or physical gas-phase deposition to form barrier layer and soakage layer; Chemical vapor deposition method or physical gas-phase deposition is adopted to form the first metal gate material layer 108.
Then, as shown in fig. 1f, remove sacrificial material layer 107 and be arranged in the sacrificial gate dielectric layer 102b of dummy gate structure 102 in FET2 district, obtain second gate groove 109.Traditional handicraft is adopted to complete described removal, such as dry etching or wet etching, wherein, the etching gas that dry etching uses can be fluorine-based, chloro or bromine-based gas, and the corrosive liquid that wet etching uses can be tetramethyl ammonium hydroxide solution (TMAH).Then, perform wet cleaning processes, to remove etch residues in second gate groove 109 and impurity.
Then, as shown in Figure 1 G, the second metal gate material layer 110 is deposited, to fill second gate groove 109 completely.Then, cmp is performed, until expose the top of interlayer dielectric layer 105.Before the described deposition of enforcement, also be included in the step that the second workfunction setting metal layer, barrier layer and soakage layer are formed successively on the sidewall of second gate groove 109 and bottom, in order to simplify, not give in figure and the second workfunction setting metal layer, barrier layer and soakage layer are shown.Wherein, second workfunction setting metal layer comprises one or more layers metal or metallic compound, if FET2 is NFET, then the constituent material of the second workfunction setting metal layer is the metal material being applicable to NFET, comprise titanium, tantalum, aluminium, zirconium, hafnium and alloy thereof, also comprise the carbide of above-mentioned metallic element, nitride etc., if FET2 is PFET, then the constituent material of the second workfunction setting metal layer is the metal material being applicable to PFET, comprise titanium, ruthenium, palladium, platinum, tungsten and alloy thereof, also comprise the carbide of above-mentioned metallic element, nitride etc.; The material on barrier layer comprises tantalum nitride or titanium nitride; The material of soakage layer comprises titanium or titanium-aluminium alloy; The constituent material of the second metal gate material layer 110 comprises aluminium.Adopt atom layer deposition process or physical gas-phase deposition to form the second workfunction setting metal layer, adopt atom layer deposition process or physical gas-phase deposition to form barrier layer and soakage layer; Chemical vapor deposition method or physical gas-phase deposition is adopted to form the second metal gate material layer 110.
So far, the processing step that the method completing according to an exemplary embodiment of the present is implemented.That above-described embodiment is explained is the sacrificial gate dielectric layer 102b first removing the dummy gate structure 102 being arranged in FET1 district, be positioned at the top epitaxial growth sacrificial material layer 107 of dummy gate structure 102 in FET2 district again, form the implementation process of metal gate material floor afterwards successively in FET1 district and FET2 district; What those skilled in the art can know is, also the sacrificial gate dielectric layer 102b of the dummy gate structure 102 being arranged in FET2 district can first be removed, be positioned at the top epitaxial growth sacrificial material layer 107 of dummy gate structure 102 in FET1 district again, form metal gate material floor in FET2 district and FET1 district successively afterwards.According to the present invention, due to the existence of sacrificial material layer 107, the loss that interlayer dielectric layer 105 caused by described process of lapping can be avoided and the reduction of the gate height caused, reduce resistance further.
With reference to Fig. 2, the flow chart of the step that the method that illustrated therein is according to an exemplary embodiment of the present is implemented successively, for schematically illustrating the flow process of manufacturing process.
In step 201, provide the Semiconductor substrate with first crystal area under control and transistor seconds district, be formed on a semiconductor substrate and comprise stacked high k dielectric layer and the dummy gate structure of sacrificial gate dielectric layer from bottom to top;
In step 202., form interlayer dielectric layer on a semiconductor substrate, cover dummy gate structure;
In step 203, remove the sacrificial gate dielectric layer being arranged in the dummy gate structure in first crystal area under control, obtain first grid groove;
In step 204, the top epitaxial growth sacrificial material layer of dummy gate structure in transistor seconds district is being positioned at;
In step 205, deposit the first metal gate material layer, to fill first grid groove completely;
In step 206, remove described sacrificial material layer and be arranged in the sacrificial gate dielectric layer of dummy gate structure in transistor seconds district, obtain second gate groove;
In step 207, deposit the second metal gate material layer, to fill second gate groove completely.
[exemplary embodiment two]
Next, the making of whole semiconductor device can be completed by subsequent technique, comprising: on interlayer insulating film 105, form another interlayer insulating film, cover the top of the first metal gate material layer 108 and the second metal gate material layer 110; In described interlayer insulating film, form contact hole, expose the top of the first metal gate material layer 108 and the second metal gate material layer 110 and be formed at the top of the source/drain region in Semiconductor substrate 100, and form self-aligned silicide in the bottom of contact hole; Fill metal (being generally tungsten) in contact hole, form the connection interconnecting metal layer of follow-up formation and the contact plug of self-aligned silicide; Form multiple interconnecting metal layer, usually adopt dual damascene process; Form metal pad, for wire bonding during subsequent implementation device package.
[exemplary embodiment three]
The present invention also provides a kind of electronic installation, the semiconductor device that it method comprising according to an exemplary embodiment of the present two manufactures.Described electronic installation can be mobile phone, panel computer, notebook computer, net book, game machine, television set, VCD, DVD, navigator, camera, video camera, recording pen, any electronic product such as MP3, MP4, PSP or equipment, also can be any intermediate products comprising described semiconductor device.Described electronic installation, owing to employing described semiconductor device, thus has better performance.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (10)
1. a manufacture method for semiconductor device, comprising:
The Semiconductor substrate with first crystal area under control and transistor seconds district is provided, is formed on the semiconductor substrate and comprises stacked high k dielectric layer and the dummy gate structure of sacrificial gate dielectric layer from bottom to top;
Form interlayer dielectric layer on the semiconductor substrate, to cover described dummy gate structure;
Remove the sacrificial gate dielectric layer being arranged in the dummy gate structure in described first crystal area under control, obtain first grid groove;
Be positioned at the top epitaxial growth sacrificial material layer of dummy gate structure in described transistor seconds district;
Deposit the first metal gate material layer, to fill described first grid groove completely;
Remove described sacrificial material layer and be arranged in the sacrificial gate dielectric layer of dummy gate structure in described transistor seconds district, obtain second gate groove;
Deposit the second metal gate material layer, to fill described second gate groove completely.
2. method according to claim 1, is characterized in that, described the first transistor is PFET, and described transistor seconds is NFET, or described the first transistor is NFET, and described transistor seconds is PFET.
3. method according to claim 1, is characterized in that, between described high k dielectric layer and described Semiconductor substrate, be also formed with boundary layer, between described high k dielectric layer and described sacrificial gate dielectric layer, be also formed with cover layer.
4. method according to claim 1, is characterized in that, described sacrificial material layer is silicon layer, germanium silicon layer or carbon silicon layer, and thickness is 50-300 dust.
5. method according to claim 1, is characterized in that, after forming described interlayer dielectric layer, also comprises the step of execution first cmp, until expose the top of described dummy gate structure.
6. method according to claim 1, is characterized in that, after depositing described first metal gate material layer, also comprises the step of execution second cmp, until expose the top of described sacrificial material layer.
7. method according to claim 1, is characterized in that, after depositing described second metal gate material layer, also comprises the step of execution the 3rd cmp, until expose the top of described interlayer dielectric layer.
8. method according to claim 1, is characterized in that, before depositing described first metal gate material layer, is also included in the step that the first workfunction setting metal layer, barrier layer and soakage layer are formed successively on the sidewall of described first grid groove and bottom; Before depositing described second metal gate material layer, be also included in the step that the second workfunction setting metal layer, described barrier layer and described soakage layer are formed successively on the sidewall of described second gate groove and bottom.
9. the semiconductor device of the method manufacture adopting one of claim 1-8 described.
10. an electronic installation, described electronic installation comprises semiconductor device according to claim 9.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113496885A (en) * | 2020-04-07 | 2021-10-12 | 中芯北方集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
| CN113643980A (en) * | 2021-07-27 | 2021-11-12 | 上海华力集成电路制造有限公司 | Semiconductor device and forming method thereof |
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| CN1282098A (en) * | 1999-07-21 | 2001-01-31 | 摩托罗拉公司 | Method for forming semiconductor device |
| US20080173947A1 (en) * | 2007-01-23 | 2008-07-24 | Yong-Tian Hou | Hybrid process for forming metal gates |
| CN103151249A (en) * | 2011-12-06 | 2013-06-12 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
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| CN1282098A (en) * | 1999-07-21 | 2001-01-31 | 摩托罗拉公司 | Method for forming semiconductor device |
| US20080173947A1 (en) * | 2007-01-23 | 2008-07-24 | Yong-Tian Hou | Hybrid process for forming metal gates |
| CN103151249A (en) * | 2011-12-06 | 2013-06-12 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113496885A (en) * | 2020-04-07 | 2021-10-12 | 中芯北方集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
| CN113496885B (en) * | 2020-04-07 | 2024-03-22 | 中芯北方集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
| CN113643980A (en) * | 2021-07-27 | 2021-11-12 | 上海华力集成电路制造有限公司 | Semiconductor device and forming method thereof |
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