CN105097566A - Fabrication method for wafer-level fan-out package - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1017—Shape being a sphere
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
The invention discloses a fabrication method for a wafer-level fan-out package. The fabrication method comprises the following steps of mounting chips on the upper surface of a substrate by using a binding agent; carrying out plastic packaging and forming on the upper surface of the substrate and packaging the chips by a plastic package material layer; coating a dielectric material on the upper surface of the plastic package material layer to form a dielectric layer; removing the dielectric layer corresponding to input-output end positions of the chips and then forming leading-out lines and welding balls on removal parts; thinning along the lower surface of the substrate, removing the substrate, the binding agent, a part of plastic package material layer and the lower surfaces of the chips, and finally leading grinding surfaces to be reserved at chip setting positions to form a package semi-finished product; and cutting the package semi-finished product along a cutting line between two adjacent chips on the package semi-finished into single package structures. According to the fabrication method, the fabrication process steps of the fan-out package can be greatly reduced, the package cost of the fan-out package is greatly reduced, and meanwhile, the package reliability is ensured.
Description
Technical field
The invention discloses the manufacture method of a kind of wafer scale fan-out encapsulation, the invention belongs to the technical field of microelectronics Packaging.
Background technology
Along with people are to the development of the requirement of electronic product to directions such as miniaturized, multi-functional, environment-friendly types, people make great efforts to seek electronic system to do less and less, integrated level is more and more higher, function does more and more, more and more stronger, thereby produce many new technologies, new material and newly design, wherein fan-out package technology is exactly the Typical Representative of these technology.
As single chips encapsulation technology of extensive use, conventional package has presented the drawback that the low and cost of packaging efficiency continues to rise at present gradually.Wafer level packaging, as a kind of novel packaged type, because reducing chip package size significantly, and is extensively adopted by industry.Existing BGA package technology is subject to the restriction of organic substrate performance.Transfer to fan-out WLP contributes to overcoming these restrictions, and can simplify supply chain.The major advantage of fan-out WLP can control warpage well, and this just can realize high assembling yield.Allow in less metal level, realize higher integrated and wiring density from setting up substrate with it in encapsulation.Fan-out WLP is the platform of future generation supporting following integrated (particularly for wireless devices).
One of foremost example of fan-out WLP structure is the eWLB technology developed by company of Infineon (InfineonTechnologiesAG).Whole chips before and after this technology adopts on road manufacturing technology integrating parallel processing wafer, can reduce manufacturing cost greatly.Its advantage is: compare with the lead frame of routine or stacked package, package area be less, I/O quantity therefrom wait until height, Connection Density maximize and can obtain needed for electricity and hot property.It also can provide high-performance and energy-conservation solution for wireless market.But its shortcoming is also obvious, when its technology designs, only considered the ventricumbent technology mode of chip functions, this application just limits the supine product of function to a great extent; This technology needs to be applied to interim bonding and the technique of tearing bonding open in addition, so also have very large difficulty in the cost calculation of final fan-out encapsulation, directly results in this encapsulation technology production cost high.
To the research of fan-out formula encapsulation technology still in continuation, due to the multiple unfavorable factor of the method for these techniques, to rate of finished products and the reliability of product, and finally go out commodity price and all cause great impact.Various new encapsulating structure and special process method are also progressively suggested and discuss.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of method for packing of wafer level packaging structure is provided.
According to technical scheme provided by the invention, a kind of manufacture method of wafer scale fan-out encapsulation comprises the following steps:
A, at the upper surface of substrate by chip by being fixed on desired location containing with chip with the binding agent of homalographic, the input/output terminal of chip is upward;
B, form capsulation material layer at the upper surface of substrate, capsulation material layer is by chip package, and the input/output terminal of chip exposes;
C, coat dielectric material at the upper surface of capsulation material layer, form dielectric layer;
D, remove corresponding chip input and output end position above dielectric layer, then form lead-out wire and soldered ball at removal position, one end of lead-out wire is connected with the input/output terminal of chip;
E, carry out thinning along the lower surface of substrate, the capsulation material layer of substrate, binding agent and part and the lower surface of chip are removed, the desired location that final grinding face rests on chip forms packaging semi-finished product;
F, on packaging semi-finished product, along the line of cut between adjacent two chips, packaging semi-finished product is cut into single package structure.
As preferably: the material of described substrate is silicon, pottery, sapphire or glass material, and the thickness of substrate is 100um-1mm.
As preferably: the material of described binding agent is epoxy resin or earth silicon material is main aqueous or membranaceous material, and the thickness of binding agent is 5um-50um.
As preferably: the material of described capsulation material layer is the resin of main body by epoxy resin, and the thickness of capsulation material layer flushes with chip upper surface.
As preferably: described capsulation material layer is completed by conventional fill process, spraying coating process, press mold technique or typography.
As preferably: the material of described dielectric layer is silicon dioxide, phenol resin or polyimides, and the thickness of dielectric layer is 1um-20um.
As preferably: described lead-out wire is formed by conventional plating, printing or depositing operation.
As preferably: in step c, cover layer protective layer at the upper surface of dielectric layer.
As preferably: the material silicon dioxide of described protective layer, silicon nitride, phenol resin or polyimides, the thickness of protective layer is 2um-20um.
Method for packing of the present invention greatly can reduce the processing step of fan-out formula encapsulation procedure, greatly reduces its packaging cost expenditure, ensure that the reliability of encapsulation simultaneously.
Accompanying drawing explanation
Fig. 1 is the structural representation of the packaging body that step a of the present invention obtains.
Fig. 2 is the structural representation of the packaging body that step b of the present invention obtains.
Fig. 3 is the structural representation of the packaging body that step c of the present invention obtains.
Fig. 4 is the structural representation of the packaging body that steps d of the present invention obtains.
Fig. 5 is the structural representation of the packaging body that step e of the present invention obtains.
Fig. 6 is the structural representation of the packaging body that step f of the present invention obtains.
Embodiment
Below in conjunction with specific embodiment, the invention will be further described.
Embodiment 1
A kind of manufacture method of wafer scale fan-out encapsulation comprises the following steps:
A, at the upper surface of substrate 6 by binding agent 7 pasting chip 1, upward, the material of substrate 6 is silicon and thickness is 100um for the input/output terminal of chip 1, and the material of binding agent 7 is epoxy resin and thickness is 5um, as shown in Figure 1;
B, form capsulation material layer 2 at the fill process of the upper surface routine of substrate 6, chip 1 encapsulates by capsulation material layer 2, and the input/output terminal of chip 1 exposes, and the material of capsulation material layer 2 is the resin of main body by epoxy resin, as shown in Figure 2;
C, coat dielectric material at the upper surface of capsulation material layer 2, form dielectric layer 4, the material of dielectric layer 4 is silicon dioxide and thickness is 1um, covers layer protective layer 5 at the upper surface of dielectric layer 4, the material of protective layer 5 is silicon dioxide and thickness is 2um, as shown in Figure 3;
D, remove the dielectric layer 4 of the input and output end position of corresponding chip 1, then adopt conventional electroplating technology to form lead-out wire 3 and soldered ball 8 removing position, one end of lead-out wire 3 is connected with the input/output terminal of chip 1, as shown in Figure 4;
E, carry out thinning along the lower surface of substrate 6, the capsulation material layer 2 of substrate 6, binding agent 7 and part and the lower surface of chip 1 are removed, the desired location that final grinding face rests on chip 1 forms packaging semi-finished product, as shown in Figure 5;
F, on packaging semi-finished product, along the line of cut between adjacent two chips 1, packaging semi-finished product is cut into single package structure, as shown in Figure 6.
Embodiment 2
A kind of manufacture method of wafer scale fan-out encapsulation comprises the following steps:
A, at the upper surface of substrate 6 by binding agent 7 pasting chip 1, upward, the material of substrate 6 is for pottery and thickness is 400um for the input/output terminal of chip 1, and to be earth silicon material be main aqueous material to the material of binding agent 7 and thickness is 20um, as shown in Figure 1;
B, form capsulation material layer 2 at the upper surface of substrate 6 by conventional spraying coating process, chip 1 encapsulates by capsulation material layer 2, and the input/output terminal of chip 1 exposes, as shown in Figure 2;
C, coat dielectric material at the upper surface of capsulation material layer 2, form dielectric layer 4, the material of dielectric layer 4 is phenol resin and thickness is 5um, and cover layer protective layer 5 at the upper surface of dielectric layer 4, the material of protective layer 5 is silicon nitride and thickness is 5um, as shown in Figure 3;
D, remove the dielectric layer 4 of the input and output end position of corresponding chip 1, then adopt conventional depositing operation to form lead-out wire 3 and soldered ball 8 removing position, one end of lead-out wire 3 is connected with the input/output terminal of chip 1, as shown in Figure 4;
E, carry out thinning along the lower surface of substrate 6, the capsulation material layer 2 of substrate 6, binding agent 7 and part and the lower surface of chip 1 are removed, the desired location that final grinding face rests on chip 1 forms packaging semi-finished product, as shown in Figure 5;
F, on packaging semi-finished product, along the line of cut between adjacent two chips 1, packaging semi-finished product is cut into single package structure, as shown in Figure 6.
Embodiment 3
A kind of manufacture method of wafer scale fan-out encapsulation comprises the following steps:
A, at the upper surface of substrate 6 by binding agent 7 pasting chip 1, upward, the material of substrate 6 is sapphire and thickness is 700um for the input/output terminal of chip 1, and to be earth silicon material be main membranaceous material to the material of binding agent 7 and thickness is 40um, as shown in Figure 1;
B, form capsulation material layer 2 at the upper surface of substrate 6 by conventional press mold technique, chip 1 encapsulates by capsulation material layer 2, and the input/output terminal of chip 1 exposes, as shown in Figure 2;
C, coat dielectric material at the upper surface of capsulation material layer 2, form dielectric layer 4, the material of dielectric layer 4 is polyimides and thickness is 15um, covers layer protective layer 5 at the upper surface of dielectric layer 4, the material of protective layer 5 is phenol resin and thickness is 15um, as shown in Figure 3;
D, remove the dielectric layer 4 of the input and output end position of corresponding chip 1, then adopt conventional typography to form lead-out wire 3 and soldered ball 8 removing position, one end of lead-out wire 3 is connected with the input/output terminal of chip 1, as shown in Figure 4;
E, carry out thinning along the lower surface of substrate 6, the capsulation material layer 2 of substrate 6, binding agent 7 and part and the lower surface of chip 1 are removed, the desired location that final grinding face rests on chip 1 forms packaging semi-finished product, as shown in Figure 5;
F, on packaging semi-finished product, along the line of cut between adjacent two chips 1, packaging semi-finished product is cut into single package structure, as shown in Figure 6.
Embodiment 4
A kind of manufacture method of wafer scale fan-out encapsulation comprises the following steps:
A, at the upper surface of substrate 6 by binding agent 7 pasting chip 1, upward, the material of substrate 6 is glass material and thickness is 1mm for the input/output terminal of chip 1, and to be earth silicon material be main membranaceous material to the material of binding agent 7 and thickness is 50um, as shown in Figure 1;
B, form capsulation material layer 2 at the upper surface of substrate 6 by conventional typography, chip 1 encapsulates by capsulation material layer 2, and the input/output terminal of chip 1 exposes, as shown in Figure 2;
C, coat dielectric material at the upper surface of capsulation material layer 2, form dielectric layer 4, the material of dielectric layer 4 is polyimides and thickness is 20um, covers layer protective layer 5 at the upper surface of dielectric layer 4, the material of protective layer 5 is polyimides and thickness is 20um, as shown in Figure 3;
D, remove the dielectric layer 4 of the input and output end position of corresponding chip 1, then adopt conventional typography to form lead-out wire 3 and soldered ball 8 removing position, one end of lead-out wire 3 is connected with the input/output terminal of chip 1, as shown in Figure 4;
F, carry out thinning along the lower surface of substrate 6, the capsulation material layer 2 of substrate 6, binding agent 7 and part and the lower surface of chip 1 are removed, the desired location that final grinding face rests on chip 1 forms packaging semi-finished product, as shown in Figure 5;
G, on packaging semi-finished product, along the line of cut between adjacent two chips 1, packaging semi-finished product is cut into single package structure, as shown in Figure 6.
Claims (9)
1. a manufacture method for wafer scale fan-out encapsulation, is characterized in that this method for packing comprises the following steps:
A, at the upper surface of substrate (6) by chip (1) by being fixed on desired location containing with chip (1) with the binding agent (7) of homalographic, the input/output terminal of chip (1) is upward;
B, substrate (6) upper surface formed capsulation material layer (2), capsulation material layer (2) by chip (1) encapsulate, the input/output terminal of chip (1) exposes;
C, coat dielectric material at the upper surface of capsulation material layer (2), form dielectric layer (4);
D, remove corresponding chip (1) input and output end position above dielectric layer (4), then form lead-out wire (3) and soldered ball (8) at removal position, one end of lead-out wire (3) is connected with the input/output terminal of chip (1);
E, carry out thinning along the lower surface of substrate (6), the capsulation material layer (2) of substrate (6), binding agent (7) and part and the lower surface of chip (1) are removed, final grinding face rests on the desired location formation packaging semi-finished product of chip (1);
F, on packaging semi-finished product, along the line of cut between adjacent two chips (1), packaging semi-finished product is cut into single package structure.
2. the manufacture method of a kind of wafer scale fan-out encapsulation according to claim 1, is characterized in that: the material of described substrate (6) is silicon, pottery, sapphire or glass material, and the thickness of substrate (6) is 100um-1mm.
3. the manufacture method of a kind of wafer scale fan-out encapsulation according to claim 1, it is characterized in that: the material of described binding agent (7) is epoxy resin or earth silicon material is main aqueous or membranaceous material, and the thickness of binding agent (7) is 5um-50um.
4. the manufacture method of a kind of wafer scale fan-out encapsulation according to claim 1, is characterized in that: the material of described capsulation material layer (2) is the resin of main body by epoxy resin, and the thickness of capsulation material layer (2) flushes with chip upper surface.
5. the manufacture method of a kind of wafer scale fan-out encapsulation according to claim 1, is characterized in that: described capsulation material layer (2) is completed by conventional fill process, spraying coating process, press mold technique or typography.
6. the manufacture method of a kind of wafer scale fan-out encapsulation according to claim 1, is characterized in that: the material of described dielectric layer (4) is silicon dioxide, phenol resin or polyimides, and the thickness of dielectric layer (4) is 1um-20um.
7. the manufacture method of a kind of wafer scale fan-out encapsulation according to claim 1, is characterized in that: described lead-out wire (3) is formed by conventional plating, printing or depositing operation.
8. the manufacture method of a kind of wafer scale fan-out encapsulation according to claim 1, is characterized in that: in step c, covers layer protective layer (5) at the upper surface of dielectric layer (4).
9. the manufacture method of a kind of wafer scale fan-out encapsulation according to claim 8, it is characterized in that: the material of described protective layer (5) is silicon dioxide, silicon nitride, phenol resin or polyimides, the thickness of protective layer (5) is 2um-20um.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510377660.6A CN105097566A (en) | 2015-07-01 | 2015-07-01 | Fabrication method for wafer-level fan-out package |
| PCT/CN2016/087232 WO2017000852A1 (en) | 2015-07-01 | 2016-06-27 | Method of manufacturing fan-out wafer-level package |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510377660.6A CN105097566A (en) | 2015-07-01 | 2015-07-01 | Fabrication method for wafer-level fan-out package |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017000852A1 (en) * | 2015-07-01 | 2017-01-05 | 华进半导体封装先导技术研发中心有限公司 | Method of manufacturing fan-out wafer-level package |
| CN106876291A (en) * | 2016-12-30 | 2017-06-20 | 清华大学 | A kind of thin chip flexibility is fanned out to method for packing and prepared encapsulating structure |
| CN107300807A (en) * | 2017-06-01 | 2017-10-27 | 武汉华星光电技术有限公司 | A kind of preparation method of optical element, liquid crystal display module and moth eye micro-structural |
| CN107863363A (en) * | 2017-11-20 | 2018-03-30 | 苏州晶方半导体科技股份有限公司 | Encapsulating structure of chip and preparation method thereof |
| CN108108681A (en) * | 2017-12-14 | 2018-06-01 | 江西合力泰科技有限公司 | With high bio-identification module for resisting external force ability and preparation method thereof |
| CN108321215A (en) * | 2018-03-07 | 2018-07-24 | 苏州晶方半导体科技股份有限公司 | The encapsulating structure and preparation method thereof of optical finger print identification chip |
| CN109659278A (en) * | 2018-12-26 | 2019-04-19 | 合肥矽迈微电子科技有限公司 | Multichip stacking encapsulation method and Multichip stacking encapsulation body |
| CN111128918A (en) * | 2019-12-31 | 2020-05-08 | 山东盛品电子技术有限公司 | Chip packaging method and chip |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2017000852A1 (en) * | 2015-07-01 | 2017-01-05 | 华进半导体封装先导技术研发中心有限公司 | Method of manufacturing fan-out wafer-level package |
| CN106876291A (en) * | 2016-12-30 | 2017-06-20 | 清华大学 | A kind of thin chip flexibility is fanned out to method for packing and prepared encapsulating structure |
| CN107300807A (en) * | 2017-06-01 | 2017-10-27 | 武汉华星光电技术有限公司 | A kind of preparation method of optical element, liquid crystal display module and moth eye micro-structural |
| CN107863363A (en) * | 2017-11-20 | 2018-03-30 | 苏州晶方半导体科技股份有限公司 | Encapsulating structure of chip and preparation method thereof |
| CN108108681A (en) * | 2017-12-14 | 2018-06-01 | 江西合力泰科技有限公司 | With high bio-identification module for resisting external force ability and preparation method thereof |
| CN108321215A (en) * | 2018-03-07 | 2018-07-24 | 苏州晶方半导体科技股份有限公司 | The encapsulating structure and preparation method thereof of optical finger print identification chip |
| CN109659278A (en) * | 2018-12-26 | 2019-04-19 | 合肥矽迈微电子科技有限公司 | Multichip stacking encapsulation method and Multichip stacking encapsulation body |
| CN111128918A (en) * | 2019-12-31 | 2020-05-08 | 山东盛品电子技术有限公司 | Chip packaging method and chip |
| CN111128918B (en) * | 2019-12-31 | 2021-10-26 | 山东盛品电子技术有限公司 | Chip packaging method and chip |
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