CN105095636B - A kind of integer calculation method, device and medical treatment detection device - Google Patents
A kind of integer calculation method, device and medical treatment detection device Download PDFInfo
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Abstract
A kind of integer computing device, including the first computing module, the second computing module, summer and combiner, first computing module, for by the signal sampling value (X at current time and the preceding n moment at current time0,X1,...,Xn) it is expressed as the subsignal sequence with the predetermined truth of a matter and index, by the amplification factor (b of amplifiers at different levels0,b1,...,bn) it is expressed as the sub- amplification sequence with the predetermined truth of a matter and index, operation, which is amplified, using the first type amplification arithmetic unit obtains the first summing value Sx；Second computing module, for by the amplification factor (a of amplifiers at different levels0,a1,...,an) it is expressed as the sub- amplification sequence with the predetermined truth of a matter and index, operation, which is amplified, using second type amplification arithmetic unit obtains the second summing value Sy；The summer is used for the second summing value SyWith the first summing value SxIt is added, obtains third summing value Sy0, the combiner, for obtaining the third summing value Sy0Integer part Y, using as current time system output.
Description
Technical field
The present invention relates to medical electronics field more particularly to a kind of integer calculation methods, device and medical treatment detection device.
Background technique
During signal acquisition, analysis and display, due to the spectral characteristic of complicated site environment and signal itself,
It generally requires to make limitation to the bandwidth of system input signal, that is, needs to be filtered system input signal with filter,
Such as system input signal is filtered using iir digital filter to limit the bandwidth of system input signal.
For iir digital filter, filtering accuracy is influenced by truncated error.It is existing in order to obtain high precision
Iir digital filter mainly have the following two kinds processing scheme: one is in iir digital filter operation use floating type transport
It calculates, the advantage of doing so is that filter accuracies are high, but for not supporting that it is slow that the CPU of floating type operation will lead to CPU operation.
Another kind is the precision of restriction filter and system input signal, is calculated in iir digital filter operation using integer, the party
The advantages of method is the CPU for not supporting floating type operation, and CPU is calculated rapidly, the disadvantage is that filter accuracies are not high.
Summary of the invention
In view of the above-mentioned problems, not propped up the purpose of the present invention is to provide a kind of integer computing device and method for guaranteeing
While holding the filtering accuracy of the CPU of floating type operation, the calculating speed of CPU is improved.
In a first aspect, a kind of integer computing device, including the first computing module, the second computing module, summer and combination
Device, wherein
First computing module, for by the signal sampling value at current time and the preceding n+1 moment at current time
(X0,X1,...,Xn) it is expressed as the subsignal sequence with the predetermined truth of a matter and index, by the amplification factor of amplifiers at different levels
(b0,b1,...,bn) it is expressed as the sub- amplification sequence with the predetermined truth of a matter and index, amplify arithmetic unit pair using the first type
The subsignal sequence and sub- amplification sequence amplify operation, generate the first output sequence (Sx0,Sx1,...,Sxn), and by institute
State the first output sequence (Sx0,Sx1,...,Sxn) be added obtain the first summing value Sx, wherein the subsignal sequence and the son
Data in amplification sequence are integer data；
Second computing module, for by the amplification factor (a of amplifiers at different levels0,a1,...,an) be expressed as having
There is the sub- amplification sequence of the predetermined truth of a matter and index, amplifies arithmetic unit for the output at the preceding m moment at current time using second type
It is worth (Sy1,...,Sym) respectively with and the sub- amplification sequence of amplification factor of the amplifier at different levels amplify operation, generate the
Two output sequence (Sy'1,...,Sy'm), and by the second output sequence (Sy'1,...,Sy'm) it is added the second obtained summing value
Sy；
The summer is used for the second summing value SyWith the first summing value SxIt is added, obtains third summing value
Sy0, wherein the third summing value Sy0For the output valve at current time；
The combiner, for obtaining the third summing value Sy0Integer part Y, it is defeated using the system as current time
Out.
Optionally, first computing module is specifically used for, by each signal sampling value Xi(0≤i≤n) is expressed as having
Sub- signal sequence (the X of the predetermined truth of a matter and indexi-seg0, Xi-seg1..., Xi-segk), by the amplification factor b of each amplifieri
It is expressed as the sub- amplification sequence (B with the predetermined truth of a matter and exponential representationi-seg0, Bi-seg1..., Bi-segt), (X described in orderi-seg0,
Xi-seg1..., Xi-segk) each subsignal one by one with the sub- amplification sequence (Bi-seg0, Bi-seg1..., Bi-segl) by finger
Number relationship carries out multiplying, generates Sxi；By the SxiThe first summing value S is obtained by index summation operationx, wherein institute
State SxiAnd the first summing value SxIt is sequence.
Optionally, second computing module is specifically used for, by the amplification factor a of each amplifieriIt is expressed as having pre-
Determine t sub- amplification sequence (A of the truth of a matter and exponential representationi-seg0,Ai-seg1,...,Ai-segt), by the preceding m moment at current time
Output valve Syj(0≤j≤m) respectively with the sub- amplification sequence (Ai-seg0,Ai-seg1,...,Ai-segt) carried out by exponential relationship
Multiplying generates Sy'j, by the Sy'jThe second summing value S is obtained by index summation operationy, wherein the second summing value Sy
And Sy'jIt is sequence.
Optionally, the combiner is specifically used for, by the third summing value Sy0In data corresponding with negative exponent cast out,
To obtain the third summing value Sy0Integer part Y, and as the system at current time export.
Optionally, the signal sampling value is integer data, and the amplification factor of the amplifier is integer data or floating-point
Type data.
Second aspect provides a kind of integer calculation method, includes at least following steps:
By the signal sampling value (X at current time and the preceding n+1 moment at current time0,X1,...,Xn) respectively indicate
At the subsignal sequence with the predetermined truth of a matter and index, by the amplification factor (b of amplifiers at different levels0,b1,...,bn) respectively indicate
At the sub- amplification sequence with the predetermined truth of a matter and index, the subsignal sequence and son are amplified using the first type amplification arithmetic unit
Sequence carries out operation, generates the first output sequence (Sx0,Sx1,...,Sxn), and by the first output sequence (Sx0,Sx1,...,
Sxn) be added obtain the first summing value Sx, wherein the data in the subsignal sequence and the sub- amplification sequence are integer
According to；
By the amplification factor (a of amplifiers at different levels0,a1,...,an) it is expressed as that there is the son of the predetermined truth of a matter and index to put
Big sequence, using second type amplification arithmetic unit to the output valve (S at the preceding m moment at current timey1,...,Sym) with and it is described
The amplification factor of amplifiers at different levels amplifies operation, generates the second output sequence (Sy'1,...,Sy'm), and it is defeated by described second
Sequence (S outy'1,...,Sy'm) it is added the second obtained summing value Sy；
By the second summing value SyWith the first summing value SxIt is added, obtains third summing value Sy0, wherein described
Three summing value Sy0For the output valve at current time；
Obtain the third summing value Sy0Integer part Y, using as current time system output.
Optionally, the signal sampling value (X by current time and the preceding n+1 moment at current time0,X1,...,
Xn) it is expressed as the subsignal sequence with the predetermined truth of a matter and index, by the amplification factor (b of amplifiers at different levels0,b1,...,
bn) it is expressed as the sub- amplification sequence with the predetermined truth of a matter and index, using the first type amplification arithmetic unit to the subsignal
Sequence and sub- amplification sequence carry out operation, generate the first output sequence (Sx0,Sx1,...,Sxn), and by first output sequence
(Sx0,Sx1,...,Sxn) be added obtain the first summing value Sx, comprising:
By signal sampling value Xi(0≤i≤n) is expressed as the subsignal sequence (X with the predetermined truth of a matter and indexi-seg0,
Xi-seg1..., Xi-segk) and by the amplification factor b of each amplifieriIt is expressed as that there is the son of the predetermined truth of a matter and exponential representation to put
Big sequence (Bi-seg0, Bi-seg1..., Bi-segt)；
(the X by described ini-seg0, Xi-seg1..., Xi-segk) each subsignal one by one with the (Bi-seg0,
Bi-seg1..., Bi-segt) by exponential relationship progress multiplying, generate Sxi；And
By the Sxi(0≤i≤n) obtains the first summing value S by index summation operationx。
Optionally, the amplification factor (a by amplifiers at different levels0,a1,...,an) it is expressed as that there is the predetermined truth of a matter
With the sub- amplification sequence of index, amplify arithmetic unit to the output valve (S at the preceding m moment at current time using second typey1,...,
Sym) with and the amplification factor of the amplifier at different levels amplify operation, generate the second output sequence (Sy'1,...,Sy'm), and
By the second output sequence (Sy'1,...,Sy'm) it is added the second obtained summing value Sy, comprising:
By the amplification factor a of each amplifieriIt is expressed as that there is the predetermined truth of a matter and the n of exponential representation sub- amplification sequences
(Ai-seg0,Ai-seg1,...,Ai-segt)；
By the output valve S at the preceding m moment at current timeyjThe subsignal that (0≤j≤m) includes one by one with the (Ai-seg0,
Ai-seg1,...,Ai-segt) by exponential relationship progress multiplying, generate Sy'j；And
By the Sy'jIt is added to obtain the second summing value S by exponential relationshipy。
Optionally, the signal sampling value is integer data, and the amplification factor of the amplifier is integer data or floating-point
Type data.
The third aspect, provides a kind of medical treatment detection device, and the medical treatment detection device includes above-mentioned integer computing device.
Integer computing device provided in an embodiment of the present invention, by by the amplification factor of the signal sampling value and amplifier
It is split as the integer subsequence with the predetermined truth of a matter and index, multiplication then is carried out to the subsequence and amplifies operation, is obtained defeated
Value S outy0.The output valve S is cast out by the combiner againy0Fractional part (such as exponent bits be negative part), thus
Obtain third summing value Sy0Integer part Y.Due to not being related to Floating-point Computation in entire calculating process, thus can enable not
It supports the CPU of floating type operation while guaranteeing filter accuracies, improves the calculating speed of CPU.
Detailed description of the invention
In order to illustrate more clearly of technical solution of the present invention, attached drawing needed in embodiment will be made below
Simply introduce, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, general for this field
For logical technical staff, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is the schematic diagram of integer computing device provided in an embodiment of the present invention.
Fig. 2 is the concrete structure schematic diagram of integer computing device shown in FIG. 1.
Fig. 3 is the working principle diagram of the first type operational amplifier shown in Fig. 2.
Fig. 4 is the working principle diagram of second type operational amplifier shown in Fig. 2.
Fig. 5 is the flow chart of integer calculation method provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Fig. 1 and Fig. 2 is please referred to, the present invention provides a kind of integer computing device 100, and the integer computing device 100 includes
The output end of first computing module 10, the second computing module 20, summer 30 and combiner 40, first computing module 10 connects
The input terminal of the summer 30 is connect, the output end of second computing module 20 connects the input terminal of the summer 30, institute
The output end for stating summer 30 connects the input terminal and the combiner 40 of second computing module 20.Wherein:
First computing module 10, for by the signal sampling at current time and the preceding n+1 moment at current time
It is worth (X0,X1,...,Xn) it is expressed as the subsignal sequence with the predetermined truth of a matter and index, by the times magnification of amplifiers at different levels
Number (b0,b1,...,bn) it is expressed as the sub- amplification sequence with the predetermined truth of a matter and index, amplify arithmetic unit using the first type
Operation is amplified to the subsignal sequence and sub- amplification sequence, generates the first output sequence (Sx0,Sx1,...,Sxn), and will
First output sequence (the Sx0,Sx1,...,Sxn) be added obtain the first summing value Sx, wherein the subsignal sequence and son are put
Data in big sequence are integer data.
Specifically, in embodiments of the present invention, in the input terminal of first computing module 10, signal sampling value Xn,
Xn-1... X0It is located at corresponding input terminal delay amplification branch.When obtaining the signal sampling value X at current time, Xn-1It is logical
It crosses on the delayer 11 of the n-th input terminal delay amplification branch as Xn, and with amplifier bnAmplification factor bnIt is input to together
One type amplifies in arithmetic unit 14, Xn-2It is delayed on the delayer 11 of amplification branch by the (n-1)th input terminal as Xn-1, and with amplification
Device bnAmplification factor bnIt is input in the first type amplification arithmetic unit 14 together ..., X0It is delayed by first input end and amplifies branch
Delayer 11 on be used as X1, and with amplifier b1Amplification factor b1It is input in the first type amplification arithmetic unit 14 together, currently
The signal sampling value X of sampling instant is then used as X0With amplifier b0Amplification factor b0The first type amplification arithmetic unit 14 is inputted together
In.
Also referring to Fig. 3, in embodiments of the present invention, the working principle of the first type amplification arithmetic unit 14 are as follows:
The first type amplification arithmetic unit 14 has the first splitter and the second splitter, and first splitter is used for will
The signal sampling value Xi(0≤i≤n) is split as having the k+1 of the predetermined truth of a matter and index sub- signal sequence (Xi-seg0,
Xi-seg1..., Xi-segk), by the amplification factor b of each amplifieriIt is split as that there is t+1 son of the predetermined truth of a matter and index to put
Big sequence (Bi-seg0, Bi-seg1..., Bi-segt), then will described in (Xi-seg0, Xi-seg1..., Xi-segk) each subsignal
One by one with the (Bi-seg0, Bi-seg1..., Bi-segt) by exponential relationship carry out multiplying after, generate Sxi。
For example, it is assumed that signal sampling value X0It is 2109, and amplifier a0Amplification factor 1.468, the predetermined truth of a matter be 10
(i.e. the decimal system).Then first splitter is according to the truth of a matter by the signal sampling value X0It is split as 2*103+1*102+0*
101+9*100, i.e., the described signal sampling value X0Corresponding subsignal sequence is (2,1,0,9).Second splitter is put described
Big multiple b0It is split as 1*100+4*10-1+6*10-2+8*10-3, i.e., the described amplification factor a0Corresponding sub- amplification sequence be (Isosorbide-5-Nitrae,
6,8), at this point, calculating 2109*1.468 is equivalent to calculating:
(2,1,0,9) * (Isosorbide-5-Nitrae, 6,8)
={ 2*1,2*4,2*6,2*8,1*1,1*4,1*6,1*8,9*1,9*4,9*6,9*8 }
=2*103+8*102+12*101+16*100+1*102+4*101+6*100+8*10-1+9*100+36*10-1
+54*10-2+72*10-3
=3*103+0*102+9*101+6*100+0*10-1+1*10-2+2*10-3
In Fig. 3, the S of the sub- output of output 11For the data " 3 " (corresponding index is 3) with highest index position, sub- output 2
The S of output2The S exported for " 0 " (corresponding exponent bits are 2), sub- output 33For " 9 " (corresponding exponent bits are 1), remaining is according to this
Analogize.In calculating process, the first type amplification arithmetic unit 14 also needs to store the corresponding index of each data simultaneously, in order to
Subsequent index read group total is carried out, in subsequent calculating process, should ensure that the principle that same index is added.
It should be noted that in other embodiments of the invention, the first type amplification arithmetic unit 14 can also have other
Operation method.For example, it is assumed that signal sampling value X0It is 2109, and amplifier a0Amplification factor be 1.468, the predetermined bottom
Number is 10 (i.e. the decimal systems).Then first splitter is according to the truth of a matter by the signal sampling value X0It is split as 2*103+1*
102+0*101+9*100, i.e., the described signal sampling value X0Corresponding subsignal sequence is (2,1,0,9).Wherein, for the ease of area
Separate index number position, first splitter can also be designed as follows, it is assumed that the accessible maximum integer position of the first splitter
It is 5, maximum decimal place is 5, then first splitter is filled with 0 pair of subsignal sequence, makes the sub- letter
The digit of number sequence is 10, if the present embodiment is by filling, the subsignal sequence can be expressed as (0,2,1,0,9,0,0,
0,0,0), from left to right, the corresponding index of first subsignal " 0 " is 4, and the corresponding index of second subsignal " 2 " is 3 ... the
The corresponding index of ten subsignals " 0 " is -5.Second splitter is by the amplification factor b0It is split as 1*100+4*10-1+
6*10-2+8*10-3, i.e., at this point, sub- amplification sequence is (Isosorbide-5-Nitrae, 6,8), wherein and for discrimination index position, second splitter
It can be designed as follows, it is assumed that the accessible maximum integer position of the second splitter is 5, and maximum decimal place is 5, then will
The sub- amplification sequence is filled with 0 pair of sub- amplification sequence, makes digit 10 of the sub- amplification sequence, such as this reality
Example is applied by filling, the sub- amplification sequence can be expressed as to (0,0,0,0, Isosorbide-5-Nitrae, 6,8,0,0), from left to right, first son
Amplifying " 0 " corresponding index is 4, and the corresponding index of second son amplification " 0 " is 3 ..., and the 5th son amplifies " 1 " corresponding index
It is 0, and so on；At this point, calculating 2109*1.468 is equivalent to calculating:
(0,2,1,0,9,0,0,0,0,0) * (0,0,0,0, Isosorbide-5-Nitrae, 6,8,0,0)
Then, it is described first amplification arithmetic unit 14 calculated as follows, by each subsignal of the subsignal sequence by
One carries out multiplying according to exponential relationship with all sub- amplifications in sub- amplification sequence, it may be assumed that
(0,2,1,0,9,0,0,0,0,0) * (0,0,0,0, Isosorbide-5-Nitrae, 6,8,0,0)
=(0,2,0,0,0,0,0,0,0,0) * (0,0,0,0, Isosorbide-5-Nitrae, 6,8,0,
0)+(0,0,1,0,0,0,0,0,0,0) * (0,0,0,0, Isosorbide-5-Nitrae, 6,8,
0,0)
+ (0,0,0,0,9,0,0,0,0,0) * (0,0,0,0, Isosorbide-5-Nitrae, 6,8,0,
0)
=(0,2,9,3,6,0,0,0,0,0)
+ (0,0, Isosorbide-5-Nitrae, 6,8,0,0,0,0)
+ (0,0,0,1,3,2,1,2,0,0)
=(0,3,0,9,6,0,1,2,0,0)
At this point, the S of 1 output of son output1=0, the S that sub- output 2 exports2=3, the S that sub- output 3 exports3=0, sub- output 4
The S of output4=9, the S that sub- output 5 exports5=6, the S that sub- output 6 exports6=0, the S that sub- output 7 exports7=1, sub- output 8 is defeated
S out8=2, the S that sub- output 9 exports9=0, the S that sub- output 10 exports10=0, therefore, the S exported at this timex0For (0,3,0,9,
6,0,1,2,0,0).
In above-described embodiment, according to same calculating process, first computing module 10 can calculate separately the first input
The output valve S of end delay amplification branchx1, the output valve S of the second input terminal delay amplification branchx2..., the delay of the n-th input terminal is put
The output result S of big branchxn, in this way, can be obtained the first output sequence (Sx0,Sx1,...,Sxn).First operation
Module 10 is also by the first output sequence (Sx0,Sx1,...,Sxn) be added by exponential relationship, obtain the first summing value Sx,
Wherein, the Sx0,Sx1,...,SxnAnd the first summing value SxIt is sequence, is added the summation operation for meeting exponential relationship.
It should be noted that the predetermined truth of a matter is not limited to 10 in above-described embodiment, it can also be 2 (binary systems), 8 (eight
System), 16 (hexadecimals) or any other integer system.The sequence that first splitter and the second splitter define is most
Big digit is also not necessarily limited to ten, can also be 15,20 or any other digit, the digit indicate first splitter and
The maximum data that second splitter can be handled can be defined according to the actual situation, and the present invention is without limitation.
Second computing module 20, for by the amplification factor (a of amplifiers at different levels0,a1,...,an) be expressed as
Sub- amplification sequence with the predetermined truth of a matter and index, and using second type amplification arithmetic unit to preceding m moment at current time
Output valve (Sy1,...,Sym) with and the amplification factor of the amplifier at different levels amplify operation, generate the second output sequence
(Sy'1,...,Sy'm), and by the second output sequence (Sy'1,...,Sy'm) it is added the second obtained summing value Sy。
Specifically, in embodiments of the present invention, in the input terminal of second computing module 20, output valve Sym, Sym- 1..Sy1It is located at corresponding delay amplification branch road.As the output valve S for acquiring current timey0When, output valve Sym-1It is logical
It crosses on the delayer 21 of m input terminal delay amplification branch as Sym, and with amplifier amAmplification factor amIt is input to together
In the second type amplification arithmetic unit 24 ..., Sy0It is delayed on the delayer 21 of amplification branch by first input end as Sy1, and
With amplifier a1Amplification factor a1It is input in second type amplification arithmetic unit 24 together.
Referring to Figure 4 together, in embodiments of the present invention, the working principle of the second type amplification arithmetic unit 24 are as follows:
The second type amplification arithmetic unit 24 has third splitter, and the third splitter is used for each amplifier
Amplification factor aj(0≤j≤m) is split as having the t+1 of the predetermined truth of a matter and index sub- amplification sequence (Ai-seg0, Ai-seg1...,
Ai-segt), then by the output valve SyjEach subsignal one by one with the sub- amplification sequence (Ai-seg0, Ai-seg1...,
Ai-segt) by exponential relationship progress multiplying, generate Sy'j, due to the output valve SyiThis as sequence, therefore, there is no need into
Row is split.
In embodiments of the present invention, the output valve SyiEach subsignal one by one with the (Ai-seg0,
Ai-seg1..., Ai-segt) by exponential relationship progress multiplication amplification operation, the process and first type calculated amplifies arithmetic unit
The 14 processing subsignal sequence (Xi-seg0, Xi-seg1..., Xi-segk) and the sub- amplification sequence (Bi-seg0, Bi-seg1...,
Bi-segt) calculating process it is similar with principle, details are not described herein.Second computing module 20 is available described by calculating
Second output sequence (Sy'1,...,Sy'm), second computing module 20 is also by the second output sequence (Sy'1,...,
Sy'm), the second summing value S being addedy, wherein the Sy'1,...,Sy'mAnd the second summing value SyIt is sequence,
It is added the summation operation for meeting exponential relationship.
The summer 30 is used for the second summing value SyWith the first summing value SxIt is added, obtains third summation
Value Sy0, wherein the third summing value Sy0For the output valve at current time.
In embodiments of the present invention, the first summing value SxIt is pushed to the summer 30, the second summing value Sy
Be pushed to the summer 30, the summer 30 according to exponential relationship (be added with index bit digital, and full system into
Position) to the second summing value SyWith the first summing value SxIt is added, generates the third summing value Sy0, wherein institute
State third summing value Sy0For the output valve at current time, and the third summing value Sy0It is pushed to second computing module
20 input terminal and the combiner 40.
The combiner 40, for obtaining the third summing value Sy0Integer part Y, using the system as current time
Output.
In embodiments of the present invention, the combiner 40 is summed according to the output valve at the current time received, i.e. third
Value Sy0, by the third summing value Sy0Fractional part is removed by exponential relationship, is such as that the corresponding data of negative are gone by exponential part
Fall, calculating then is combined to the part that exponential part is positive number, obtains the third summing value Sy0Integer part, and it is defeated
Out.For example, it is assumed that the third summing value Sy0For (3,0,9,6,0,1,2), by analysis above it is found that rear three indexes
For negative, latter three are cast out, i.e., third summing value S at this timey0Integer part Y be 3096.
In conclusion integer computing device 100 provided in an embodiment of the present invention, by by the signal sampling value and amplification
The amplification factor of device is split as the integer subsequence with the predetermined truth of a matter and index, then carries out multiplication amplification to the subsequence
Operation obtains output valve Sy0.The output valve S is cast out by the combiner 40 againy0Fractional part (such as exponent bits are negative
Several parts), to obtain third summing value Sy0Integer part Y.Due to not being related to floating-point meter in entire calculating process
It calculates, thus can enable and not support the CPU of floating type operation while guaranteeing filter accuracies, improve the calculating speed of CPU.
Referring to Fig. 5, the embodiment of the present invention provides a kind of integer calculation method, following steps are included at least:
S201, by the signal sampling value (X at current time and the preceding n+1 moment at current time0,X1,...,Xn) respectively
It is illustrated as having the subsignal sequence of the predetermined truth of a matter and index, by the amplification factor (b of amplifiers at different levels0,b1,...,bn) respectively
It is illustrated as having the sub- amplification sequence of the predetermined truth of a matter and index, using the first type amplification arithmetic unit to the subsignal sequence and son
Amplification sequence carries out operation, generates the first output sequence (Sx0,Sx1,...,Sxn), and by the first output sequence (Sx0,
Sx1,...,Sxn) be added obtain the first summing value Sx, wherein the data in the subsignal sequence and the sub- amplification sequence are equal
For integer data；
Specifically:
Firstly, by signal sampling value Xi(0≤i≤n) is expressed as the subsignal sequence with the predetermined truth of a matter and index
(Xi-seg0, Xi-seg1..., Xi-segk) and by the amplification factor b of each amplifieriIt is expressed as that there is the predetermined truth of a matter and exponential representation
Sub- amplification sequence (Bi-seg0, Bi-seg1..., Bi-segt)；
In embodiments of the present invention, in the input terminal of first computing module 10, signal sampling value Xn, Xn-1... X0Point
It Wei Yu not corresponding input terminal delay amplification branch.When obtaining the signal sampling value X at current time, Xn-1Pass through the n-th input terminal
X is used as on the delayer 11 of delay amplification branchn, and with amplifier bnAmplification factor bnIt is input to the first type amplification fortune together
It calculates in device 14, Xn-2It is delayed on the delayer 11 of amplification branch by the (n-1)th input terminal as Xn-1, and with amplifier bnAmplification
Multiple bnIt is input in the first type amplification arithmetic unit 14 together ..., X0It is delayed by first input end and amplifies the delayer 11 of branch
It is upper to be used as X1, and with amplifier b1Amplification factor b1It is input in the first type amplification arithmetic unit 14 together, current sample time
Signal sampling value X is then used as X0With amplifier b0Amplification factor b0It is inputted in the first type amplification arithmetic unit 14 together.
In embodiments of the present invention, the first type amplification arithmetic unit 14 has the first splitter and the second splitter, institute
The first splitter is stated to be used for the signal sampling value Xi(0≤i≤n) is split as the k+1 son with the predetermined truth of a matter and index
Signal sequence (Xi-seg0, Xi-seg1..., Xi-segk), by the amplification factor b of each amplifieriBe split as having the predetermined truth of a matter and
T+1 sub- amplification sequence (B of indexi-seg0, Bi-seg1..., Bi-segt)。
Secondly, (the X by described ini-seg0, Xi-seg1..., Xi-segk) each subsignal one by one with the (Bi-seg0,
Bi-seg1..., Bi-segt) by exponential relationship progress multiplying, generate Sxi。
With the signal sampling value X at current time0For, it is assumed that signal sampling value X0It is 2109, and amplifier a0Times magnification
Number 1.468, the predetermined truth of a matter are 10 (i.e. the decimal systems).Then first splitter is according to the truth of a matter by the signal sampling
Value X0It is split as 2*103+1*102+0*101+9*100, i.e., the described signal sampling value X0Corresponding subsignal sequence be (2,1,0,
9).Second splitter is by the amplification factor b0It is split as 1*100+4*10-1+6*10-2+8*10-3, i.e., the described amplification factor
a0Corresponding sub- amplification sequence is (Isosorbide-5-Nitrae, 6,8), at this point, calculating 2109*1.468 is equivalent to calculating:
(2,1,0,9) * (Isosorbide-5-Nitrae, 6,8)
={ 2*1,2*4,2*6,2*8,1*1,1*4,1*6,1*8,9*1,9*4,9*6,9*8 }
=2*103+8*102+12*101+16*100+1*102+4*101+6*100+8*10-1+9*100+36*10-1
+54*10-2+72*10-3
=3*103+0*102+9*101+6*100+0*10-1+1*10-2+2*10-3
In Fig. 3, the S of the sub- output of output 11For the data " 3 " (corresponding index is 3) with highest index position, sub- output 2
The S of output2The S exported for " 0 " (corresponding exponent bits are 2), sub- output 33For " 9 " (corresponding exponent bits are 1), remaining is according to this
Analogize.In calculating process, the first type amplification arithmetic unit 14 also needs to store the corresponding index of each data simultaneously, in order to
Subsequent index read group total is carried out, in subsequent calculating process, should ensure that the principle that same index is added.
It should be noted that in other embodiments of the invention, the first type amplification arithmetic unit 14 can also have other
Operation method.For example, it is assumed that signal sampling value X0It is 2109, and amplifier a0Amplification factor be 1.468, the predetermined bottom
Number is 10 (i.e. the decimal systems).Then first splitter is according to the truth of a matter by the signal sampling value X0It is split as 2*103+1*
102+0*101+9*100, i.e., the described signal sampling value X0Corresponding subsignal sequence is (2,1,0,9).Wherein, for the ease of area
Separate index number position, first splitter can also be designed as follows, it is assumed that the accessible maximum integer position of the first splitter
It is 5, maximum decimal place is 5, then first splitter is filled with 0 pair of subsignal sequence, makes the sub- letter
The digit of number sequence is 10, if the present embodiment is by filling, the subsignal sequence can be expressed as (0,2,1,0,9,0,0,
0,0,0), from left to right, the corresponding index of first subsignal " 0 " is 4, and the corresponding index of second subsignal " 2 " is 3 ... the
The corresponding index of ten subsignals " 0 " is -5.Second splitter is by the amplification factor b0It is split as 1*100+4*10-1+
6*10-2+8*10-3, i.e., at this point, sub- amplification sequence is (Isosorbide-5-Nitrae, 6,8), wherein and for discrimination index position, second splitter
It can be designed as follows, it is assumed that the accessible maximum integer position of the second splitter is 5, and maximum decimal place is 5, then will
The sub- amplification sequence is filled with 0 pair of sub- amplification sequence, makes digit 10 of the sub- amplification sequence, such as this reality
Example is applied by filling, the sub- amplification sequence can be expressed as to (0,0,0,0, Isosorbide-5-Nitrae, 6,8,0,0), from left to right, first son
Amplifying " 0 " corresponding index is 4, and the corresponding index of second son amplification " 0 " is 3 ..., and the 5th son amplifies " 1 " corresponding index
It is 0, and so on；At this point, calculating 2109*1.468 is equivalent to calculating:
(0,2,1,0,9,0,0,0,0,0) * (0,0,0,0, Isosorbide-5-Nitrae, 6,8,0,0)
Then, it is described first amplification arithmetic unit 14 calculated as follows, by each subsignal of the subsignal sequence by
One carries out multiplying according to exponential relationship with all sub- amplifications in sub- amplification sequence, it may be assumed that
(0,2,1,0,9,0,0,0,0,0) * (0,0,0,0, Isosorbide-5-Nitrae, 6,8,0,0)
=(0,2,0,0,0,0,0,0,0,0) * (0,0,0,0, Isosorbide-5-Nitrae, 6,8,0,
0)+(0,0,1,0,0,0,0,0,0,0) * (0,0,0,0, Isosorbide-5-Nitrae, 6,8,
0,0)
+ (0,0,0,0,9,0,0,0,0,0) * (0,0,0,0, Isosorbide-5-Nitrae, 6,8,0,
0)
=(0,2,9,3,6,0,0,0,0,0)
+ (0,0, Isosorbide-5-Nitrae, 6,8,0,0,0,0)
+ (0,0,0,1,3,2,1,2,0,0)
=(0,3,0,9,6,0,1,2,0,0)
At this point, the S of 1 output of son output1=0, the S that sub- output 2 exports2=3, the S that sub- output 3 exports3=0, sub- output 4
The S of output4=9, the S that sub- output 5 exports5=6, the S that sub- output 6 exports6=0, the S that sub- output 7 exports7=1, sub- output 8 is defeated
S out8=2, the S that sub- output 9 exports9=0, the S that sub- output 10 exports10=0.Therefore, the S exported at this timex0For (0,3,0,9,
6,0,1,2,0,0).
Finally, by the Sxi(0≤i≤n) obtains the first summing value S by index summation operationx。
In embodiments of the present invention, according to same calculating process, first computing module 10 can calculate separately first
The output valve S of input terminal delay amplification branchx1, the output valve S of the second input terminal delay amplification branchx2..., the n-th input terminal prolongs
The output result S of Shi Fang great branchxn, in this way, can be obtained the first output sequence (Sx0,Sx1,...,Sxn).Described first
Computing module 10 is also by the first output sequence (Sx0,Sx1,...,Sxn) be added by exponential relationship, obtain the first summation
Value Sx, wherein the Sx0,Sx1,...,SxnAnd the first summing value SxIt is sequence, is added the summation fortune for meeting exponential relationship
It calculates.
S402, by the amplification factor (a of amplifiers at different levels0,a1,...,an) it is expressed as that there is the predetermined truth of a matter and index
Sub- amplification sequence, using second type amplification arithmetic unit to the output valve (S at the preceding m moment at current timey1,...,Sym) with
And the amplification factor of the amplifier at different levels amplifies operation, generates the second output sequence (Sy'1,...,Sy'm), and will be described
Second output sequence (Sy'1,...,Sy'm) it is added the second obtained summing value Sy；
Specifically:
Firstly, by the amplification factor a of each amplifieriIt is expressed as the n son amplification with the predetermined truth of a matter and exponential representation
Sequence (Ai-seg0,Ai-seg1,...,Ai-segt)；
Specifically, in embodiments of the present invention, in the input terminal of second computing module 20, output valve Sym, Sym- 1..Sy1It is located at corresponding delay amplification branch road.As the output valve S for acquiring current timey0When, output valve Sym-1It is logical
It crosses on the delayer 21 of m input terminal delay amplification branch as Sym, and with amplifier amAmplification factor amIt is input to together
In the second type amplification arithmetic unit 24 ..., Sy0It is delayed on the delayer 21 of amplification branch by first input end as Sy1, and
With amplifier a1Amplification factor a1It is input in second type amplification arithmetic unit 24 together.
In embodiments of the present invention, the second type amplification arithmetic unit 24 has third splitter, the third splitter
For by the amplification factor a of each amplifierj(0≤j≤m) is split as the t+1 son amplification sequence with the predetermined truth of a matter and index
Arrange (Ai-seg0, Ai-seg1..., Ai-segt), then by the output valve SyjEach subsignal one by one with the sub- amplification sequence
Arrange (Ai-seg0, Ai-seg1..., Ai-segt) by exponential relationship progress multiplying, generate Sy'j, due to the output valve SyiItself
For sequence, therefore, there is no need to be split.
Secondly, by the output valve S at the preceding m moment at current timeyjThe subsignal that (0≤j≤m) includes one by one with it is described
(Ai-seg0,Ai-seg1,...,Ai-segt) by exponential relationship progress multiplying, generate Sy'j。
Finally, by the Sy'jIt is added to obtain the second summing value S by exponential relationshipy。
S403, by the second summing value SyWith the first summing value SxIt is added, obtains third summing value Sy0, wherein
The third summing value Sy0For the output valve at current time；
In embodiments of the present invention, the first summing value SxIt is pushed to the summer 30, the second summing value Sy
Be pushed to the summer 30, the summer 30 according to exponential relationship (be added with index bit digital, and full system into
Position) to the second summing value SyWith the first summing value SxIt is added, generates the third summing value Sy0, wherein institute
State third summing value Sy0For the output valve at current time, and the third summing value Sy0It is pushed to second computing module
20 input terminal and the combiner 40.
S404 obtains the third summing value Sy0Integer part Y, using as current time system output.
In embodiments of the present invention, the combiner 40 is summed according to the output valve at the current time received, i.e. third
Value Sy0, by the third summing value Sy0Fractional part is removed by exponential relationship, is such as that the corresponding data of negative are gone by exponential part
Fall, calculating then is combined to the part that exponential part is positive number, obtains the third summing value Sy0Integer part, and it is defeated
Out.For example, it is assumed that the third summing value Sy0For (3,0,9,6,0,1,2), by analysis above it is found that rear three indexes
For negative, latter three are cast out, i.e., third summing value S at this timey0Integer part Y be 3096.
In conclusion integer calculation method provided in an embodiment of the present invention, by by the signal sampling value and amplifier
Amplification factor be split as the integer subsequence with the predetermined truth of a matter and index, then to the subsequence carry out multiplication amplification fortune
It calculates, obtains output valve Sy0.The output valve S is cast out by the combiner 40 againy0Fractional part (such as exponent bits be negative
Part), to obtain third summing value Sy0Integer part Y.Due to not being related to Floating-point Computation in entire calculating process,
Can thus enable does not support the CPU of floating type operation while guaranteeing filter accuracies, improves the calculating speed of CPU.
Above disclosed is only a preferred embodiment of the present invention, cannot limit the power of the present invention with this certainly
Sharp range, those skilled in the art can understand all or part of the processes for realizing the above embodiment, and weighs according to the present invention
Benefit requires made equivalent variations, still belongs to the scope covered by the invention.
Those of ordinary skill in the art will appreciate that realizing all or part of the process in above-described embodiment method, being can be with
Relevant hardware is instructed to complete by computer program, the program can be stored in a computer-readable storage medium
In, the program is when being executed, it may include such as the process of the embodiment of above-mentioned each method.Wherein, the storage medium can be magnetic
Dish, CD, read-only memory (Read-Only Memory, ROM) or random access memory (Random Access
Memory, RAM) etc..
Claims (10)
1. a kind of integer computing device, which is characterized in that including the first computing module, the second computing module, summer and combination
Device, wherein
First computing module, for by the signal sampling value (X at current time and the preceding n+1 moment at current time0,
X1,...,Xn) it is expressed as the subsignal sequence with the predetermined truth of a matter and index, at different levels in the first operational amplifier are put
Amplification factor (the b of big device0,b1,...,bn) it is expressed as the sub- amplification sequence with the predetermined truth of a matter and index, utilize first
Type amplifies arithmetic unit and amplifies operation to the subsignal sequence and sub- amplification sequence, generates the first output sequence (Sx0,
Sx1,...,Sxn), and by the first output sequence (Sx0,Sx1,...,Sxn) be added obtain the first summing value Sx, wherein it is described
Data in subsignal sequence and the sub- amplification sequence are integer data；
Second computing module, for by the amplification factor (a of the amplifiers at different levels in second operational amplifier0,a1,...,
an) it is expressed as the sub- amplification sequence with the predetermined truth of a matter and index, amplify arithmetic unit for current time using second type
Output valve (the S at preceding m momenty1,...,Sym) amplification factor with the amplifiers at different levels in the second operational amplifier respectively
Sub- amplification sequence amplify operation, generate the second output sequence (Sy'1,...,Sy'm), and by second output sequence
(Sy'1,...,Sy'm) it is added the second obtained summing value Sy；
The summer is used for the second summing value SyWith the first summing value SxIt is added, obtains third summing value Sy0,
Wherein, the third summing value Sy0For the output valve at current time；
The combiner, for obtaining the third summing value Sy0Integer part Y, using as current time system output.
2. the apparatus according to claim 1, which is characterized in that first computing module is specifically used for, by each signal
Sampled value Xi(0≤i≤n) is expressed as the subsignal sequence (X with the predetermined truth of a matter and indexi-seg0, Xi-seg1..., Xi-segk),
By the amplification factor b of each amplifieriIt is expressed as the sub- amplification sequence (B with the predetermined truth of a matter and exponential representationi-seg0,
Bi-seg1..., Bi-segt), (X described in orderi-seg0, Xi-seg1..., Xi-segk) each subsignal one by one with the sub- amplification
Sequence (Bi-seg0, Bi-seg1..., Bi-segl) by exponential relationship progress multiplying, generate Sxi；By the SxiIt sums by index
Operation obtains the first summing value Sx, wherein the SxiAnd the first summing value SxIt is sequence.
3. the apparatus according to claim 1, which is characterized in that second computing module is specifically used for, by each amplification
The amplification factor a of deviceiIt is expressed as that there is the predetermined truth of a matter and the t+1 of exponential representation sub- amplification sequence (Ai-seg0,Ai-seg1,...,
Ai-segt), by the output valve S at the preceding m moment at current timeyj(Sy1,...,Sym, 0≤j≤m) respectively with the sub- amplification sequence
Arrange (Ai-seg0,Ai-seg1,...,Ai-segt) by exponential relationship progress multiplying, generate Sy'j, by the Sy'jIt sums and transports by index
Calculation obtains the second summing value Sy, wherein the second summing value SyAnd Sy'jIt is sequence.
4. the apparatus according to claim 1, which is characterized in that the combiner is specifically used for, by the third summing value
Sy0In data corresponding with negative exponent cast out, to obtain the third summing value Sy0Integer part Y, and as current time
System output.
5. the apparatus according to claim 1, which is characterized in that the signal sampling value is integer data, the amplifier
Amplification factor be integer data or real-coded GA.
6. a kind of integer calculation method, which is characterized in that include at least following steps:
By the signal sampling value (X at current time and the preceding n+1 moment at current time0,X1,...,Xn) be expressed as having
There is the subsignal sequence of the predetermined truth of a matter and index, by the amplification factor (b of the amplifiers at different levels in the first operational amplifier0,
b1,...,bn) it is expressed as the sub- amplification sequence with the predetermined truth of a matter and index, using the first type amplification arithmetic unit to described
Subsignal sequence and sub- amplification sequence carry out operation, generate the first output sequence (Sx0,Sx1,...,Sxn), and it is defeated by described first
Sequence (S outx0,Sx1,...,Sxn) be added obtain the first summing value Sx, wherein the subsignal sequence and the sub- amplification sequence
In data be integer data；
By the amplification factor (a of the amplifiers at different levels in second operational amplifier0,a1,...,an) it is expressed as that there is predetermined bottom
Several and index sub- amplification sequence, using second type amplification arithmetic unit to the output valve at the preceding m moment at current time
(Sy1,...,Sym) with the amplification factors of the amplifiers at different levels in the second operational amplifier amplify operation, generate second
Output sequence (Sy'1,...,Sy'm), and by the second output sequence (Sy'1,...,Sy'm) it is added the second obtained summing value
Sy；
By the second summing value SyWith the first summing value SxIt is added, obtains third summing value Sy0, wherein the third is asked
With value Sy0For the output valve at current time；
Obtain the third summing value Sy0Integer part Y, using as current time system output.
7. according to the method described in claim 6, it is characterized in that, described by the preceding n+1 at current time and current time
Signal sampling value (the X at moment0,X1,...,Xn) it is expressed as the subsignal sequence with the predetermined truth of a matter and index, it will be at different levels
Amplification factor (the b of amplifier0,b1,...,bn) it is expressed as the sub- amplification sequence with the predetermined truth of a matter and index, utilize
One type amplifies arithmetic unit and carries out operation to the subsignal sequence and sub- amplification sequence, generates the first output sequence (Sx0,
Sx1,...,Sxn), and by the first output sequence (Sx0,Sx1,...,Sxn) be added obtain the first summing value Sx, comprising:
By signal sampling value Xi(0≤i≤n) is expressed as the subsignal sequence (X with the predetermined truth of a matter and indexi-seg0,
Xi-seg1..., Xi-segk) and by the amplification factor b of each amplifieriIt is expressed as that there is the son of the predetermined truth of a matter and exponential representation to put
Big sequence (Bi-seg0, Bi-seg1..., Bi-segt)；
(the X by described ini-seg0, Xi-seg1..., Xi-segk) each subsignal one by one with the (Bi-seg0, Bi-seg1...,
Bi-segt) by exponential relationship progress multiplying, generate Sxi；And
By the Sxi(0≤i≤n) obtains the first summing value S by index summation operationx。
8. according to the method described in claim 6, it is characterized in that, the amplification factor (a by amplifiers at different levels0,a1,...,
an) it is expressed as the sub- amplification sequence with the predetermined truth of a matter and index, using second type amplification arithmetic unit to current time
Output valve (the S at preceding m momenty1,...,Sym) with and the amplification factor of the amplifier at different levels amplify operation, generate the
Two output sequence (Sy'1,...,Sy'm), and by the second output sequence (Sy'1,...,Sy'm) it is added the second obtained summing value
Sy, comprising:
By the amplification factor a of each amplifieriIt is expressed as that there is the predetermined truth of a matter and the t+1 of exponential representation sub- amplification sequences
(Ai-seg0,Ai-seg1,...,Ai-segt)；
By the output valve S at the preceding m moment at current timeyj(Sy1,...,Sym, 0≤j≤m) include subsignal one by one with it is described
(Ai-seg0,Ai-seg1,...,Ai-segt) by exponential relationship progress multiplying, generate Sy'j；And
By the Sy'jIt is added to obtain the second summing value S by exponential relationshipy。
9. according to the method described in claim 6, it is characterized in that, the signal sampling value is integer data, the amplifier
Amplification factor be integer data or real-coded GA.
10. a kind of medical treatment detection device, which is characterized in that the medical treatment detection device includes such as any one of claim 1-5 institute
The integer computing device stated.
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