CN105070765A - Thin film transistor, array substrate, display device and manufacturing method - Google Patents
Thin film transistor, array substrate, display device and manufacturing method Download PDFInfo
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- CN105070765A CN105070765A CN201510570320.5A CN201510570320A CN105070765A CN 105070765 A CN105070765 A CN 105070765A CN 201510570320 A CN201510570320 A CN 201510570320A CN 105070765 A CN105070765 A CN 105070765A
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- 239000010409 thin film Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 title claims abstract description 15
- 239000000463 material Substances 0.000 claims abstract description 64
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 64
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 33
- 150000004706 metal oxides Chemical class 0.000 claims description 61
- 238000000034 method Methods 0.000 claims description 46
- 238000009413 insulation Methods 0.000 claims description 37
- 238000000059 patterning Methods 0.000 claims description 29
- 238000002161 passivation Methods 0.000 claims description 26
- 239000004020 conductor Substances 0.000 claims description 20
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 12
- 230000003139 buffering effect Effects 0.000 claims description 8
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 6
- JYMITAMFTJDTAE-UHFFFAOYSA-N aluminum zinc oxygen(2-) Chemical compound [O-2].[Al+3].[Zn+2] JYMITAMFTJDTAE-UHFFFAOYSA-N 0.000 claims description 6
- 229910052733 gallium Inorganic materials 0.000 claims description 6
- 229910052738 indium Inorganic materials 0.000 claims description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 6
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 6
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 claims description 6
- 239000011787 zinc oxide Substances 0.000 claims description 6
- 150000002739 metals Chemical class 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 44
- 239000007789 gas Substances 0.000 description 9
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 239000007769 metal material Substances 0.000 description 5
- 230000008054 signal transmission Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- Engineering & Computer Science (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses a thin film transistor, an array substrate, a display device and a manufacturing method and belongs to the display technical field. The thin film transistor includes a source electrode, a drain electrode, an active layer, a gate insulating layer and a gate electrode; the active layer and the drain electrode are located in the same layer; materials for forming the active layer contain metallic oxides; materials for forming the drain electrode contain conductive metallic oxides; the source electrode and the gate insulating layer are located at the same side of the active layer; the source electrode and the gate insulating layer contact with the same side surface of the active layer; the gate insulating layer is located between the source electrode and the drain electrode; the thickness of the gate insulating layer is larger than that of the source electrode; materials for forming the source electrode contain metal; and the gate electrode contacts with one surface of the gate insulating layer which is far away from the active layer. According to the thin film transistor of the invention, the materials for forming the drain electrode contain conductive metallic oxides; the materials for forming the source electrode contain metal; the source electrode and a data line are formed through patternizing a source electrode layer; metals for forming the data line and the source electrode both contain metal; and therefore, the problem of signal delay can be solved.
Description
Technical field
The present invention relates to Display Technique field, particularly a kind of thin-film transistor, array base palte, display unit and manufacture method.
Background technology
Liquid crystal display is gradually to large scale, high image quality and low energy consumption future development, its structure is included in the middle of the parallel substrate of two panels and places liquid crystal layer, infrabasal plate is array base palte, upper substrate is color membrane substrates, changed the rotation direction controlling liquid crystal molecule by the voltage on array base palte, thus reach the transmitance controlling each pixel incident light and the object reaching display.
Array base palte comprises underlay substrate, data wire, source electrode, drain electrode, pixel electrode, grid, grid line and gate insulation layer, each electrode and holding wire are formed on the underlay substrate of array base palte mainly through patterning processes, wherein data wire and source electrode are formed in a patterning processes simultaneously, and grid line and grid are formed in a patterning processes simultaneously.
Realizing in process of the present invention, inventor finds that prior art at least exists following problem:
The material of existing source electrode and data wire can select the metal oxide of conductor, and uses conductor metal oxide can produce more serious signal delay phenomenon as data wire, thus affects the display quality of liquid crystal display.
Summary of the invention
In order to solve the problem of prior art, embodiments provide a kind of thin-film transistor, array base palte, display unit and manufacture method.Described technical scheme is as follows:
A kind of thin-film transistor, described thin-film transistor comprises source electrode, drain electrode, active layer, gate insulation layer and grid;
Described active layer and described drain electrode are positioned at same layer, and the material of described active layer comprises metal oxide, and the material of described drain electrode comprises the metal oxide of conductor;
Described source electrode and described gate insulation layer are positioned at the same side of described active layer, and described source electrode and described gate insulation layer contact with the same side of described active layer, described gate insulation layer is between described source electrode and described drain electrode, the thickness of described gate insulation layer is greater than the thickness of described source electrode, and the material of described source electrode comprises metal;
Described grid contacts with the one side of described gate insulation layer away from described active layer.
A kind of array base palte, described array base palte comprises multiple pixel cells that the grid line be formed on underlay substrate, data wire and described grid line and described data wire and described data wire are divided into, and described pixel cell comprises pixel electrode and described thin-film transistor,
Active layer and the drain electrode of described pixel electrode, described thin-film transistor are positioned at same layer, and described drain electrode is connected with described pixel electrode, and the material of described pixel electrode comprises the metal oxide of conductor.
Alternatively, described array base palte also comprises passivation layer, and described passivation layer covers described source electrode, described grid, described drain electrode and described pixel electrode.
Alternatively, be also provided with buffering metal level below the source electrode of described thin-film transistor, described buffering metal level is between described source electrode and described active layer.
Alternatively, described array base palte also comprises public electrode, and described public electrode is positioned on described passivation layer.
A kind of display unit, comprise display floater, it is characterized in that, described display floater comprises described array base palte.
A manufacture method for array base palte, described method comprises:
Underlay substrate forms metal oxide layer, described metal oxide layer comprises Part I, Part II and Part III, described Part I is active layer, described Part II is between described Part I and Part III, described metal oxide layer deposits source layer, the material of described source layer comprises metal
By a patterning processes by described source layer patterning, form the figure comprising the source electrode of thin-film transistor;
Described source electrode, described active layer, described Part II and described Part III deposit gate insulation layer and grid layer;
By a patterning processes by described gate insulation layer and described grid layer patterning, formed and comprise the grid of described thin-film transistor and the figure of gate insulation layer, and described Part II is formed the figure comprising the drain electrode of described thin-film transistor, and described Part III is formed the figure comprising the pixel electrode of described thin-film transistor.
Alternatively, the described figure described Part II formation being comprised the drain electrode of described thin-film transistor, and the figure that described Part III formation comprises the pixel electrode of described thin-film transistor is comprised:
Adopt vacuum plasma gas to bombard described Part II and described metal oxide layer corresponding to described Part III, form the figure comprising described drain electrode at described Part II, form the figure comprising described pixel electrode at described Part III.
Alternatively, the manufacture method of described array base palte also comprises:
Deposit passivation layer on described source electrode, described grid, described drain electrode and described pixel electrode.
Alternatively, the manufacture method of described array base palte also comprises:
Described passivation layer deposits common electrode layer, by a patterning processes by described public electrode pattern layers, forms the figure of public electrode.
Alternatively, the material of described metal oxide layer comprises the single metal oxide of any one composition in aluminium zinc oxide, indium-zinc oxide, indium gallium zinc oxide, indium tin zinc oxide, or aluminium zinc oxide, indium-zinc oxide, indium gallium zinc oxide, the multiple layer metal oxide of any several composition in indium tin zinc oxide.
The beneficial effect that the technical scheme that the embodiment of the present invention provides is brought is:
Active layer and the drain electrode of thin-film transistor are positioned at same layer, the material of active layer comprises metal oxide, the material of drain electrode comprises the metal oxide of conductor, the material of source electrode comprises metal, source electrode be positioned at active layer and with a contacts side surfaces of active layer, source electrode and data wire are that source layer is formed, so the material of data wire is identical with source electrode by a patterning processes, comprise metal, solve the problem of signal delay.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of the thin-film transistor that the embodiment of the present invention one provides;
Fig. 2 is the structural representation of the array base palte that the embodiment of the present invention two provides;
Fig. 3 is the structural representation of the array base palte that the embodiment of the present invention two provides;
Fig. 4 is the structural representation of the array base palte that the embodiment of the present invention two provides;
Fig. 5 is the structural representation of the array base palte that the embodiment of the present invention two provides;
Fig. 6 is the structural representation of the array base palte that the embodiment of the present invention two provides;
Fig. 7-Figure 21 is the manufacture process schematic diagram of the array base palte that the embodiment of the present invention four provides.
Wherein,
1 source electrode, 2 drain electrodes, 3 active layers, 4 gate insulation layers,
5 grids, 6 underlay substrates, 7 pixel electrodes, 8 buffering metal levels,
9 passivation layers, 10 public electrodes, 11 metal oxide layers, 12 source layers,
13 photoresists, 14 grid layers,
A grid line, B data wire, C thin-film transistor,
D Part I, E Part II, F Part III,
The complete reserved area of G photoresist,
H photoresist half reserved area, H1 first photoresist half reserved area, H2 second photoresist half reserved area.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, embodiment of the present invention is described further in detail.
Embodiment one
As shown in Figure 1, embodiments provide a kind of thin-film transistor, this thin-film transistor comprises source electrode 1, drain electrode 2, active layer 3, gate insulation layer 4 and grid 5;
Active layer 3 and drain electrode 2 are positioned at same layer, and the material of active layer 3 comprises metal oxide, and the material of drain electrode 2 comprises the metal oxide of conductor;
Source electrode 1 and gate insulation layer 4 are positioned at the same side of active layer 3, and source electrode 1 and gate insulation layer 4 contact with the same side of active layer 3, gate insulation layer 4 is between source electrode 1 and drain electrode 2, and the thickness of gate insulation layer 4 is greater than the thickness of source electrode 1, and the material of source electrode 1 comprises metal;
Grid 5 contacts with the one side of gate insulation layer 4 away from active layer 3.
In an embodiment of the present invention, the active layer 3 of thin-film transistor is positioned at same layer with drain electrode 2, the material of active layer 3 comprises metal oxide, the material of drain electrode 2 comprises the metal oxide of conductor, the thickness of gate insulation layer 4 is greater than the thickness of source electrode 1, grid 5 is avoided to be short-circuited with the Contact of source electrode 1, the material of source electrode 1 comprises metal, source electrode 1 to be positioned on active layer 3 and with a contacts side surfaces of active layer 3, source electrode 1 and data wire are that source layer is formed by patterning processes, so the material of the material of data wire and source electrode 1 includes metal, metal material can better receive and signal transmission, solve the problem of signal delay.
Embodiment two
As shown in Figure 2, and see Fig. 3, embodiments provide a kind of array base palte, multiple pixel cells that this array base palte comprises the grid line A be formed on underlay substrate 6, data wire B and grid line A and data wire B is divided into, pixel cell comprises pixel electrode 7 and the thin-film transistor C as described in embodiment one
As shown in Figure 3, active layer 3 and the drain electrode 2 of pixel electrode 7, thin-film transistor C are positioned at same layer, and drain electrode 2 is connected with pixel electrode 7, and the material of pixel electrode 7 comprises the metal oxide of conductor.
As shown in Figure 3, in an embodiment of the present invention, the active layer 3 of array base palte, drain electrode 2 and pixel electrode 7 are positioned at same layer, the material of active layer 3 comprises metal oxide, and the material of drain electrode 2 and pixel electrode 7 includes the metal oxide of conductor, the thickness of gate insulation layer 4 is greater than the thickness of source electrode 1, grid 5 is avoided to be short-circuited with the Contact of source electrode 1, the material of source electrode 1 comprises metal, source electrode 1 to be positioned on active layer 3 and with a contacts side surfaces of active layer 3, source electrode 1 and data wire B are that source layer is formed by patterning processes, so the material of the material of data wire B and source electrode 1 includes metal, metal material can better receive and signal transmission, solve the problem of signal delay.
Alternatively, as shown in Figure 4, be also provided with buffering metal level 8 below the source electrode 1 of thin-film transistor, buffering metal level 8 is between source electrode 1 and active layer 3, and buffering metal level 8 can make source electrode 1 better be deposited on active layer 3.
Alternatively, as shown in Figure 5, array base palte also comprises passivation layer 9, and passivation layer 9 covers source electrode 1, grid 5, drain electrode 2 and pixel electrode 7.
Passivation layer 9 can protect source electrode 1, grid 5, drain electrode 2 and pixel electrode 7.
Alternatively, the material of passivation layer 9 comprises SiNx.
Adopt SiNx as the material of passivation layer 9, when depositing, the gas of use comprises ammonia, containing more hydrogen in ammonia, can make in deposition process the drain electrode 2 that formed by the metal oxide of conductor and pixel electrode 7 reduce resistance further, meanwhile, adopt SiNx to replace SiO
2as the material of passivation layer 9, when can also avoid deposit passivation layer 9, source electrode 1 is oxidized, because deposition SiO
2time, need N be used
2o gas, N
2the source electrode 1 that oxygen in O gas can make material comprise metal is oxidized.
Alternatively, as shown in Figure 6, array base palte also comprises public electrode 10, and public electrode 10 is positioned on passivation layer 9.
If the array base palte in the present embodiment is also for making the display floater of multi-dimensional electric field mode, then array base palte also needs to make public electrode, as shown in Figure 6, passivation layer 9 deposits common electrode layer, form public electrode 10 by patterning processes.
In an embodiment of the present invention, the active layer 3 of array base palte, drain electrode 2 and pixel electrode 7 are positioned at same layer, the material of active layer 3 comprises metal oxide, and the material of drain electrode 2 and pixel electrode 7 includes the metal oxide of conductor, the material of source electrode 1 comprises metal, source electrode 1 to be positioned on active layer 3 and with a contacts side surfaces of active layer 3, source electrode 1 and data wire B are that source layer 12 is formed by patterning processes, so the material of the material of data wire B and source electrode 1 includes metal, solve the problem of signal delay.
Embodiment three
Embodiments provide a kind of display unit, comprise display floater, display floater comprises the array base palte as described in embodiment two.
In an embodiment of the present invention, the active layer 3 of the array base palte that the display floater in display unit adopts, drain electrode 2 and pixel electrode 7 are positioned at same layer, the material of active layer 3 comprises metal oxide, and the material of drain electrode 2 and pixel electrode 7 includes the metal oxide of conductor, the material of source electrode 1 comprises metal, source electrode 1 to be positioned on active layer 3 and with a contacts side surfaces of active layer 3, source electrode 1 and data wire B are that source layer 12 is formed by patterning processes, so the material of the material of data wire B and source electrode 1 includes metal, metal material can better receive and signal transmission, solve the problem of signal delay.
Embodiment four
Embodiments provide a kind of manufacture method of array base palte, comprising:
Step 101: as shown in Figure 7, underlay substrate 6 is formed metal oxide layer 11, metal oxide layer 11 comprises Part I D, Part II E and Part III F, Part I D is active layer 3, Part II E is between Part I D and Part III F, metal oxide layer 11 deposits source layer 12, and the material of source layer 12 comprises metal
Particularly, as shown in Figure 7, first on underlay substrate 6, metal oxide layer 11 is formed;
Afterwards, as shown in Figure 7, metal oxide layer 11 deposits source layer 12.
Step 102: by a patterning processes by source layer 12 patterning, forms the figure comprising the source electrode 1 of thin-film transistor;
Particularly, as shown in Figure 8, first on source layer 12, one deck photoresist 13 is applied;
Afterwards, halftoning or gray tone mask plate is adopted to expose photoresist 13, develop, as shown in Figure 9, photoresist 13 is made to form the complete reserved area G of photoresist and photoresist half reserved area H, wherein, the complete reserved area G of photoresist at least corresponds to source electrode 1 location, and photoresist half reserved area H at least corresponds to part active layer 3, drain electrode 2 and pixel electrode 7 location;
Afterwards, as shown in Figure 10, and see Fig. 9, metal oxide layer 11 except the complete reserved area G of photoresist and photoresist half reserved area H and source layer 12 is etched away completely by etching technics;
Afterwards, as shown in figure 11, and see Figure 10, removed the photoresist 13 of photoresist half reserved area H by cineration technics, expose the source layer 12 in this region, as shown in figure 11, and see Figure 10, this cineration technics also can make the photoresist 13 of photoresist complete reserved area G thinning;
Afterwards, as shown in figure 12, and see Figure 10, source layer 12 corresponding to photoresist half reserved area H is etched away completely by an etching technics;
Afterwards, as shown in figure 11, peel off remaining photoresist G, as shown in figure 12, form the figure of source electrode 1.
Step 103: as shown in figure 13, the Part II E and Part III F of source electrode 1, active layer 3, metal oxide layer 11 deposit gate insulation layer 4 and grid layer 14;
Particularly, as shown in figure 13, first on the Part II E and Part III F of source electrode 1, active layer 3, metal oxide layer 11, gate insulation layer 4 is deposited;
Afterwards, as shown in figure 13, depositing layers 14 on gate insulation layer 4.
Step 104: by a patterning processes respectively by gate insulation layer 4 and grid layer 14 patterning, formed and comprise the grid 5 of thin-film transistor and the figure of gate insulation layer 4, and Part II E is formed the figure comprising the drain electrode 2 of thin-film transistor, and Part III F is formed the figure comprising the pixel electrode 7 of thin-film transistor.
Particularly, as shown in figure 14, first on grid layer 14, one deck photoresist 13 is applied;
Afterwards, halftoning or gray tone mask plate is adopted to expose photoresist 13, development, as shown in figure 15, photoresist 13 is made to form the complete reserved area G of photoresist and photoresist half reserved area H, wherein, photoresist half reserved area H is divided into the first photoresist half reserved area H1 and the second photoresist half reserved area H2, the complete reserved area G of photoresist at least corresponds to grid 5 location, corresponding part active layer 3 location, grid 5 location, first photoresist half reserved area H1 at least corresponds to source electrode 1 location, second photoresist half reserved area H2 at least corresponds to Part II E and the Part III F of metal oxide layer 11, namely drain 2 and pixel electrode 7 location,
As shown in figure 16, and see Figure 15, gate insulation layer 4 except the complete reserved area G of photoresist and photoresist half reserved area H and grid layer 14 is etched away completely by etching technics;
Afterwards, as shown in figure 17, and see Figure 16, the photoresist 13 of the first photoresist half reserved area H1 and the second photoresist half reserved area H2 is removed by cineration technics, expose the grid layer 14 of the first photoresist half reserved area H1 and the second photoresist half reserved area H2, as shown in figure 17, and see Figure 16, this cineration technics also can make the photoresist 13 of photoresist complete reserved area G thinning;
As shown in figure 18, and see Figure 16, etch away grid layer 14 corresponding to the first photoresist half reserved area H1 and gate insulation layer 4 completely by an etching technics, expose source electrode 1;
As shown in figure 19, and see Figure 16, etch away grid layer 14 corresponding to the second photoresist half reserved area H2 and gate insulation layer 4 completely by an etching technics, expose the metal oxide layer 11 of Part II E and Part III F;
Finally, as shown in figure 20, peel off remaining photoresist G, form the figure of grid 5, the Part II E of metal oxide layer 11 is formed the figure comprising the drain electrode 2 of thin-film transistor, and the Part III F of metal oxide layer 11 is formed the figure comprising the pixel electrode 7 of thin-film transistor.
In an embodiment of the present invention, the active layer 3 of array base palte, drain electrode 2 and pixel electrode 7 are positioned at same layer, the material of active layer 3 comprises metal oxide, and the material of drain electrode 2 and pixel electrode 7 includes the metal oxide of conductor, the material of source electrode 1 comprises metal, source electrode 1 to be positioned on active layer 3 and with a contacts side surfaces of active layer 3, source electrode 1 and data wire B are that source layer 12 is formed by patterning processes, so the material of the material of data wire B and source electrode 1 includes metal, metal material can better receive and signal transmission, solve the problem of signal delay.
Alternatively, Part II E is formed the figure comprising the drain electrode 2 of thin-film transistor, and Part III F is formed the figure comprising the pixel electrode 7 of thin-film transistor, comprising:
As shown in figure 19, and see Figure 20, adopt the metal oxide layer 11 that vacuum plasma gas bombardment Part II E and Part III F is corresponding, form the figure comprising drain electrode 2 at Part II E, form the figure comprising pixel electrode 7 at Part III F.
Wherein, as shown in figure 16, and see Figure 20, if what adopt when etching away grid layer 14 corresponding to the second photoresist half reserved area H2 and gate insulation layer 4 completely is dry carving technology, then in dry carving technology process, the metal oxide layer 11 that Part II E and Part III F is corresponding can present conductor trend, and form the figure of drain electrode 2 and the figure of pixel electrode 7 respectively, the gas that dry carving technology process is used comprises CF
4and O
2or He and O
2, wherein CF
4plasma gas, He plasma gas can play the effect making conductor metal oxide;
To make the conductor trend of the drain electrode 2 and pixel electrode 7 formed after overdrying is carved better, the surface using the bombardment drain electrode 2 of vacuum plasma gas and pixel electrode 7 can be continued, ammonia or hydrogen can be selected.
In an embodiment of the present invention, drain electrode 2 and the pixel electrode 7 of array base palte are positioned at same layer, and the material of drain electrode 2 and pixel electrode 7 comprises the metal oxide of conductor, not only save patterning processes, simultaneously due to drain 2 material comprise metal oxide, the aperture opening ratio of array base palte can be increased, can backlight power consumption be lowered, energy savings.
Alternatively, the manufacture method of array base palte also comprises:
Deposit passivation layer 9 on source electrode 1, grid 5, drain electrode 2 and pixel electrode 7.
As shown in figure 21, deposit passivation layer 9 on source electrode 1, grid 5, drain electrode 2 and pixel electrode 7, passivation layer 9 can protect source electrode 1, grid 5, drain electrode 2 and pixel electrode 7.
Alternatively, as shown in Figure 6, the manufacture method of array base palte also comprises:
Passivation layer 9 deposits common electrode layer, by a patterning processes by public electrode pattern layers, forms the figure of public electrode 10.
If the array base palte in the present embodiment also for making the display floater of multi-dimensional electric field mode, then can deposit common electrode layer on passivation layer 9, formed the figure of public electrode 10 by patterning processes.As shown in Figure 6, passivation layer 9 deposits common electrode layer, by the figure of a composition patterning processes formation public electrode 10.
Alternatively, the material of metal oxide layer 11 comprises the single metal oxide of any one composition in aluminium zinc oxide, indium-zinc oxide, indium gallium zinc oxide, indium tin zinc oxide, or aluminium zinc oxide, indium-zinc oxide, indium gallium zinc oxide, the multiple layer metal oxide of any several composition in indium tin zinc oxide.
In an embodiment of the present invention, the active layer 3 of array base palte, drain electrode 2 and pixel electrode 7 are positioned at same layer, the material of active layer 3 comprises metal oxide, and the material of drain electrode 2 and pixel electrode 7 includes the metal oxide of conductor, the material of source electrode 1 comprises metal, source electrode 1 to be positioned on active layer 3 and with a contacts side surfaces of active layer 3, source electrode 1 and data wire B are that source layer 12 is formed by patterning processes, so the material of the material of data wire B and source electrode 1 includes metal, metal material can better receive and signal transmission, solve the problem of signal delay.
The invention described above embodiment sequence number, just to describing, does not represent the quality of embodiment.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. a thin-film transistor, is characterized in that, described thin-film transistor comprises source electrode, drain electrode, active layer, gate insulation layer and grid;
Described active layer and described drain electrode are positioned at same layer, and the material of described active layer comprises metal oxide, and the material of described drain electrode comprises the metal oxide of conductor;
Described source electrode and described gate insulation layer are positioned at the same side of described active layer, and described source electrode and described gate insulation layer contact with the same side of described active layer, described gate insulation layer is between described source electrode and described drain electrode, the thickness of described gate insulation layer is greater than the thickness of described source electrode, and the material of described source electrode comprises metal;
Described grid contacts with the one side of described gate insulation layer away from described active layer.
2. an array base palte, it is characterized in that, described array base palte comprises multiple pixel cells that the grid line be formed on underlay substrate, data wire and described grid line and described data wire are divided into, and described pixel cell comprises pixel electrode and thin-film transistor according to claim 1
Active layer and the drain electrode of described pixel electrode, described thin-film transistor are positioned at same layer, and described drain electrode is connected with described pixel electrode, and the material of described pixel electrode comprises the metal oxide of conductor.
3. array base palte according to claim 2, is characterized in that, described array base palte also comprises passivation layer, and described passivation layer covers described source electrode, described grid, described drain electrode and described pixel electrode.
4. array base palte according to claim 2, is characterized in that, is also provided with buffering metal level below the source electrode of described thin-film transistor, and described buffering metal level is between described source electrode and described active layer.
5. array base palte according to claim 3, is characterized in that, described array base palte also comprises public electrode, and described public electrode is positioned on described passivation layer.
6. a display unit, is characterized in that, comprises the array base palte described in any one of claim 2-5 claim.
7. a manufacture method for array base palte, is characterized in that, described method comprises:
Underlay substrate forms metal oxide layer, described metal oxide layer comprises Part I, Part II and Part III, described Part I is active layer, described Part II is between described Part I and Part III, described metal oxide layer deposits source layer, the material of described source layer comprises metal
By a patterning processes by described source layer patterning, form the figure comprising the source electrode of thin-film transistor;
Described source electrode, described active layer, described Part II and described Part III deposit gate insulation layer and grid layer;
By a patterning processes by described gate insulation layer and described grid layer patterning, formed and comprise the grid of described thin-film transistor and the figure of gate insulation layer, and described Part II is formed the figure comprising the drain electrode of described thin-film transistor, and described Part III is formed the figure comprising the pixel electrode of described thin-film transistor.
8. method according to claim 7, is characterized in that, describedly described Part II is formed the figure comprising the drain electrode of described thin-film transistor, and described Part III is formed the figure comprising the pixel electrode of described thin-film transistor comprises:
Adopt vacuum plasma gas to bombard described Part II and described metal oxide layer corresponding to described Part III, form the figure comprising described drain electrode at described Part II, form the figure comprising described pixel electrode at described Part III.
9. method according to claim 7, it is characterized in that, the manufacture method of described array base palte also comprises:
Deposit passivation layer on described source electrode, described grid, described drain electrode and described pixel electrode.
10. method according to claim 9, it is characterized in that, the manufacture method of described array base palte also comprises:
Described passivation layer deposits common electrode layer, by a patterning processes by described public electrode pattern layers, forms the figure of public electrode.
11. according to any one of claim 7-10 method, it is characterized in that, the material of described metal oxide layer comprises the single metal oxide of any one composition in aluminium zinc oxide, indium-zinc oxide, indium gallium zinc oxide, indium tin zinc oxide, or aluminium zinc oxide, indium-zinc oxide, indium gallium zinc oxide, the multiple layer metal oxide of any several composition in indium tin zinc oxide.
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| CN106653767A (en) * | 2016-12-12 | 2017-05-10 | 深圳市华星光电技术有限公司 | Array substrate and fabrication method therefor |
| CN110391186A (en) * | 2019-07-09 | 2019-10-29 | 武汉华星光电半导体显示技术有限公司 | Array substrate and preparation method thereof |
| CN111584427A (en) * | 2020-05-25 | 2020-08-25 | 京东方科技集团股份有限公司 | Manufacturing method of array substrate, array substrate and display panel |
| CN113141780A (en) * | 2019-11-01 | 2021-07-20 | 京东方科技集团股份有限公司 | Thin film transistor, method of manufacturing the same, and display device |
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| CN105070765B (en) | 2018-11-16 |
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