CN105068292A - Manufacturing method for AHVA panel - Google Patents
Manufacturing method for AHVA panel Download PDFInfo
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- CN105068292A CN105068292A CN201510473786.3A CN201510473786A CN105068292A CN 105068292 A CN105068292 A CN 105068292A CN 201510473786 A CN201510473786 A CN 201510473786A CN 105068292 A CN105068292 A CN 105068292A
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- flatness
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133351—Manufacturing of individual cells out of a plurality of cells, e.g. by dicing
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133345—Insulating layers
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133354—Arrangements for aligning or assembling substrates
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/40—Arrangements for improving the aperture ratio
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Liquid Crystal (AREA)
Abstract
The invention provides a manufacturing method for an AHVA panel. The manufacturing method includes the steps that a first insulation layer is formed; the first insulation layer is coated with a flat layer; a first electric conduction layer is deposited on the flat layer and is flush with the flat layer; a second insulation layer is formed on the first electric conduction layer; a second electric conduction layer is formed on the second insulation layer. Compared with the prior art, the first electric conduction layer is flush with the flat layer, and therefore the retreating distance between the first electric conduction layer and a hole in the flat layer is omitted, a pixel design window is added, and the pixel aperture ratio and the liquid crystal efficiency of the AHVA panel are increased. In addition, due to the fact that the retreating distance does not need to be preset on the first electric conduction layer relative to the hole of the flat layer, the exactly-opposite area between the first electric conduction layer and the second electric conduction layer can be increased, and the capacitance of a capacitor is increased.
Description
Technical field
The present invention relates to a kind of lcd technology, particularly relating to a kind ofly increases pixel aperture ratio and promotes the manufacture method of the AHVA panel of liquid crystal efficiency.
Background technology
Liquid crystal indicator is current most popular a kind of panel display apparatus, can be various electronic equipment, as mobile phone, digital camera, computing machine and personal digital assistant (PersonalDigitalAssistant, PDA) etc. provide, there is high-resolution color/graphics.Wherein, with its viewing visual angle, wide and aperture opening ratio high is subject to liking of users to fringe field switching technology (FringeFieldSwitching, FFS) liquid crystal indicator.Such as, AHVA (AdvancedHyperViewingAngle, super large visual angle high definition) display.
In general, the AHVA display liquid crystal layer that mainly comprises colored filter substrate (ColorFilterSubstrate), thin-film transistor array base-plate (ThinFilmTransistorArraySubstrate) and be arranged between two substrates.Wherein, colored filter substrate comprises a glass substrate, a chromatic filter layer and multiple black matrix, and this chromatic filter layer is provided with Red lightscreening plate, green color filter and blue color filter successively.Black arranged in matrix is in the intersection of two optical filters of arbitrary neighborhood.Array base palte comprises a subtend substrate, a common electrode layer, an insulation course and a pixel electrode layer, and this common electrode layer (commonelectrodelayer) is positioned at the top of subtend substrate and is electrically coupled to a common electric voltage (commonvoltage).Pixel electrode layer (pixelelectrodelayer) is positioned at the top of insulation course, and it comprises multiple pixel electrodes spaced apart.As is well known, the drain electrode (drain) of thin film transistor (TFT) is electrically coupled to pixel electrode, and source electrode (source) is electrically coupled to data line, and grid (gate) is electrically coupled to sweep trace.When thin film transistor (TFT) is opened, pixel electrode receives the data-signal on data line by the drain electrode of thin film transistor (TFT), the source electrode of thin film transistor (TFT), the common electrode in common electrode layer receives common signal by common electrode wire.Liquid crystal molecule in liquid crystal layer deflects under the effect of data-signal and common signal, thus makes liquid crystal indicator show corresponding image content.
But in the prior art, traditional AHVA panel is by processing procedure ability restriction, and for guaranteeing the reliable electric coupling of the drain electrode of pixel electrode and thin film transistor (TFT), the size of flatness layer must be greater than the via size of insulation course.In addition, occur short circuit condition for the photoresistance landing avoiding common electrode corresponding causes between common electrode and pixel electrode, the size of common electrode must be greater than again the size of flatness layer.Thus, the via size that insulation course is offered must overlap minimally/back out distance, and this will certainly limit the increase of pixel aperture ratio and the raising of liquid crystal efficiency.Meanwhile, because minimum overlay/back out the existence of distance, also can affect the number of pixels (pixelsperinch, ppi) of Pixel Dimensions (pixelsize)/per inch.
In view of this, how to design a kind of manufacture method of AHVA panel, or existing making technology is improved, thus overcome above-mentioned defect of the prior art or deficiency, increase pixel aperture ratio, promoting liquid crystal efficiency, is the problem that person skilled is urgently to be resolved hurrily in the industry.
Summary of the invention
For AHVA panel of the prior art because process capability restriction must overlap minimally/back out apart from this defect, the invention provides a kind of manufacture method of AHVA panel, to increase the pixel aperture ratio of panel and to promote liquid crystal efficiency.
According to one aspect of the present invention, provide a kind of manufacture method of AHVA panel, comprise the following steps:
Form one first insulation course;
Be coated with a flatness layer in the top of described first insulation course;
Deposit one first conductive layer in the top of described flatness layer, wherein, described first conductive layer aligns with described flatness layer;
Form one second insulation course in the top of described first conductive layer; And
Form one second conductive layer in the top of described second insulation course.
An embodiment wherein, between the step and the step forming described second insulation course of described first conductive layer of above-mentioned deposition, this manufacture method also comprises: expose described flatness layer; And utilize developer solution to remove a part for described flatness layer corresponding to exposure area and a part for described first conductive layer, align with described flatness layer to realize described first conductive layer.
An embodiment wherein, the step of the described flatness layer of above-mentioned coating also comprises and exposing described flatness layer, wherein, between the step and the step forming described second insulation course of described first conductive layer of above-mentioned deposition, this manufacture method also comprises: utilize developer solution to remove a part for described flatness layer corresponding to exposure area and a part for described first conductive layer, align to realize described first conductive layer with described flatness layer.
An embodiment wherein, between the step and the step forming described second insulation course of described first conductive layer of above-mentioned deposition, this manufacture method also comprises: be coated with a photoresist layer in the top of described first conductive layer, and expose described photoresist layer and described flatness layer; Utilize a part for the described flatness layer of developer solution removal corresponding to exposure area, a part for described first conductive layer and a part for described photoresist layer; And the first conductive layer described in wet etching thus the described photoresist layer peeled off above it, back out distance with what control described first conductive layer.
An embodiment wherein, described flatness layer is an organic planarization layer.
An embodiment wherein, this manufacture method also comprises: form a first metal layer in the top of a substrate, by the grid of described the first metal layer definition thin film transistor (TFT); Form a gate insulator in the top of described the first metal layer; And form one second metal level in the top of described gate insulator, define source electrode and the drain electrode of described thin film transistor (TFT) by described second metal level, wherein, the drain electrode of described thin film transistor (TFT) is electrically coupled to described second conductive layer via a via hole.
An embodiment wherein, described first conductive layer and described second conductive layer are tin indium oxide material.
An embodiment wherein, described first conductive layer is a common electrode, and described second conductive layer is a pixel electrode.
Adopt the manufacture method of AHVA panel of the present invention, first one first insulation course is formed, then a flatness layer is coated with in the top of this first insulation course, then deposit one first conductive layer in the top of this flatness layer and the first conductive layer align with flatness layer, formation one second insulation course forms the second conductive layer in the top of the second insulation course in the top of the first conductive layer afterwards.Compared to prior art, first conductive layer and flatness layer are carried out self-aligned by the present invention, thus save and back out distance between the hole on this first conductive layer and flatness layer, and then add Pixel Design window, the pixel aperture ratio of AHVA panel and liquid crystal efficiency are promoted.In addition, because the first conductive layer backs out distance relative to the hole of flatness layer without the need to presetting, thus the right opposite that can increase between the first conductive layer and the second conductive layer amasss, and then increases the capacitance of electric capacity.
Accompanying drawing explanation
Reader, after having read the specific embodiment of the present invention with reference to accompanying drawing, will become apparent various aspects of the present invention.Wherein,
Figure 1A illustrates in a kind of AHVA panel of prior art, insulation course, the vertical view of a reserved determining deviation each other between protective seam and the first conductive layer;
Figure 1B illustrates the schematic cross-section of the AHVA panel of Figure 1A;
Fig. 2 illustrates according to one embodiment of the present invention, for the FB(flow block) of the manufacture method of AHVA panel;
Fig. 3 A illustrates that the AHVA panel of Fig. 2 adopts after protective seam aligns with the first conductive layer, the vertical view of insulation course, spacing state between protective seam and the first conductive layer;
Fig. 3 B illustrates the schematic cross-section of the AHVA panel of Fig. 3 A;
Fig. 4 A to Fig. 4 C illustrates the decomposing schematic representation of the first embodiment adopting the manufacture method of Fig. 2 to make protective seam and the first conductive layer carry out aliging;
Fig. 5 A to Fig. 5 C illustrates the decomposing schematic representation of the second embodiment adopting the manufacture method of Fig. 2 to make protective seam and the first conductive layer carry out aliging; And
Fig. 6 A to Fig. 6 E illustrates the decomposing schematic representation of the 3rd embodiment adopting the manufacture method of Fig. 2 to make protective seam and the first conductive layer carry out aliging.
Embodiment
The technology contents disclosed to make the application is more detailed and complete, and can refer to accompanying drawing and following various specific embodiment of the present invention, mark identical in accompanying drawing represents same or analogous assembly.But those of ordinary skill in the art should be appreciated that hereinafter provided embodiment is not used for limiting the scope that contains of the present invention.In addition, accompanying drawing, only for being schematically illustrated, is not drawn according to its life size.
With reference to the accompanying drawings, the embodiment of various aspects of the present invention is described in further detail.
Figure 1A illustrates in a kind of AHVA panel of prior art, insulation course, the vertical view of a reserved determining deviation each other between protective seam and the first conductive layer.Figure 1B illustrates the schematic cross-section of the AHVA panel of Figure 1A.
With reference to Figure 1A and Figure 1B, as as described in preceding sections, in existing AHVA panel, because it is by processing procedure ability restriction, in order to ensure the drain electrode reliable electric coupling of pixel electrode 106 with thin film transistor (TFT), the size of flatness layer 102 must be greater than the via size of insulation course 100.Meanwhile, cause between common electrode 104 and pixel electrode 106 for avoiding the photoresistance of common electrode 104 correspondence (photospacer) landing and occur short circuit condition, the size of common electrode 104 must be greater than again the size of flatness layer 102.
Such as, insulation course 100 is d1 with the size disparity of flatness layer 102, and common electrode 104 is d2 with the size disparity of flatness layer 102.As shown in Figure 1A, between flatness layer 102 and common electrode 104, there is an annular white space, so that the minimum overlay between both keeping/back out distance, but this pixel aperture ratio that will inevitably limit panel increases the raising with liquid crystal efficiency.
In order to overcome above-mentioned defect of the prior art or deficiency, this application provides a kind of novelty, the manufacture method of AHVA panel.Fig. 2 illustrates according to one embodiment of the present invention, for the FB(flow block) of the manufacture method of AHVA panel.Fig. 3 A illustrates that the AHVA panel of Fig. 2 adopts after protective seam aligns with the first conductive layer, the vertical view of insulation course, spacing state between protective seam and the first conductive layer.Fig. 3 B illustrates the schematic cross-section of the AHVA panel of Fig. 3 A.
With reference to Fig. 2, Fig. 3 A and Fig. 3 B, in this embodiment, first the manufacture method of AVHA panel of the present invention performs step S101, forms one first insulation course (firstinsulationlayer) 108.Then in step s 103, coating (coating) flatness layer (planarizationlayer, PL) 102 is in the top of the first insulation course 108, and such as, this flatness layer 102 is an organic planarization layer (organicPL).Then perform step S105, deposition (depositing) one first conductive layer (firstconductivelayer) 104 is in the top of flatness layer 102, and wherein, the first conductive layer 104 aligns with flatness layer 102.Then in step s 107, one second insulation course (secondinsulationlayer) 100 is formed in the top of the first conductive layer 104.Finally perform step S109, form one second conductive layer (secondconductivelayer) 106 in the top of the second insulation course 100.Fig. 3 A and Figure 1A is compared, after first conductive layer 104 of the present invention adopts self-aligned (self-align) with flatness layer 102, therebetween minimum distance is backed out without the need to retaining, only between insulation course 100 and flatness layer 102, retain certain spacing distance, as shown in figure notation d3.Thus, the present invention can save and back out distance between the hole on the first conductive layer 104 and flatness layer 102, and then increases Pixel Design window area, promotes pixel aperture ratio and the liquid crystal efficiency of panel.
At a specific embodiment, the first conductive layer 104 and the second conductive layer 106 are tin indium oxide material.Further, the first conductive layer 104 is a common electrode (commonelectrode), and the second conductive layer 106 is a pixel electrode (pixelelectrode).
At a specific embodiment, this manufacture method also can form a first metal layer 202 in the top of a substrate 200, defines the grid (gateelectrode) of thin film transistor (TFT) by the first metal layer 202.Then a gate insulator (gateinsulationlayer) 204 is formed in the top of the first metal layer 202.Then one second metal level is formed in the top of gate insulator 204, by source electrode and the drain electrode of the second metal level definition thin film transistor (TFT).Wherein, the drain electrode of thin film transistor (TFT) is electrically coupled to the second conductive layer 106 via a via hole, as shown in Figure 3 B.
Fig. 4 A to Fig. 4 C illustrates the decomposing schematic representation of the first embodiment adopting the manufacture method of Fig. 2 to make protective seam and the first conductive layer carry out aliging.
With reference to Fig. 4 A to Fig. 4 C, flatness layer 102 is formed at the top of the first insulation course 108, and then depositing first conductive layer 104 is in the top of flatness layer 102.In figure 4b, flatness layer 102 is exposed, then utilize developer solution to remove a part for flatness layer 102 corresponding to exposure area and a part for the first conductive layer 104, align with flatness layer 102, as Fig. 4 C to realize the first conductive layer 104.
Fig. 5 A to Fig. 5 C illustrates the decomposing schematic representation of the second embodiment adopting the manufacture method of Fig. 2 to make protective seam and the first conductive layer carry out aliging.
With reference to Fig. 5 A to Fig. 5 C, and itself and Fig. 4 A are compared to scheming C, its key distinction is, exposes just contrary with the process sequence of depositing first conductive layer 104 to flatness layer 102.Specifically, in fig. 5, just this flatness layer 102 is exposed when coating flat layer 102, and then depositing first conductive layer 104 is in the top of flatness layer 102, and utilize developer solution to remove a part for flatness layer 102 corresponding to exposure area and a part for the first conductive layer 104, align with flatness layer 102, as Fig. 5 C to realize the first conductive layer 104.
Fig. 6 A to Fig. 6 E illustrates the decomposing schematic representation of the 3rd embodiment adopting the manufacture method of Fig. 2 to make protective seam and the first conductive layer carry out aliging.Different from aforementioned two embodiments, in this embodiment, manufacture method of the present invention also utilizes photoresist layer to carry out wet etching to the first conductive layer, with control the first conductive layer to insulation course via hole back out distance.
Similarly, in Fig. 6 A and Fig. 6 B, be first coated with a flatness layer 102 in the top of the first insulation course 108, and then deposit one first conductive layer 104 in the top of flatness layer 102.Next, be coated with a photoresist layer 110 in the top of the first conductive layer 104, and photoresist layer 110 and flatness layer 102 are exposed (as Fig. 6 C).Then developer solution is utilized to remove a part (as Fig. 6 D) for a part for flatness layer 102, a part for the first conductive layer 104 and photoresist layer 110 corresponding to exposure area.Finally, then wet etching (wetetching) first conductive layer 104 thus the photoresist layer 110 peeled off above it, distance D is backed out with what control the first conductive layer 104, as illustrated in fig. 6e.
Adopt the manufacture method of AHVA panel of the present invention, first one first insulation course is formed, then a flatness layer is coated with in the top of this first insulation course, then deposit one first conductive layer in the top of this flatness layer and the first conductive layer align with flatness layer, formation one second insulation course forms the second conductive layer in the top of the second insulation course in the top of the first conductive layer afterwards.Compared to prior art, first conductive layer and flatness layer are carried out self-aligned by the present invention, thus save and back out distance between the hole on this first conductive layer and flatness layer, and then add Pixel Design window, the pixel aperture ratio of AHVA panel and liquid crystal efficiency are promoted.In addition, because the first conductive layer backs out distance relative to the hole of flatness layer without the need to presetting, thus the right opposite that can increase between the first conductive layer and the second conductive layer amasss, and then increases the capacitance of electric capacity.
Above, the specific embodiment of the present invention is described with reference to the accompanying drawings.But those skilled in the art can understand, when without departing from the spirit and scope of the present invention, various change and replacement can also be done to the specific embodiment of the present invention.These change and replace and all drop in claims of the present invention limited range.
Claims (8)
1. a manufacture method for super large visual angle high definition (AdvancedHyperViewingAngle, AHVA) panel, is characterized in that, this manufacture method comprises the following steps:
Form one first insulation course;
Be coated with a flatness layer in the top of described first insulation course;
Deposit one first conductive layer in the top of described flatness layer, wherein, described first conductive layer aligns (self-align) with described flatness layer;
Form one second insulation course in the top of described first conductive layer; And
Form one second conductive layer in the top of described second insulation course.
2. manufacture method according to claim 1, is characterized in that, between the step and the step forming described second insulation course of described first conductive layer of above-mentioned deposition, this manufacture method also comprises:
Described flatness layer is exposed; And
Utilize developer solution to remove a part for described flatness layer corresponding to exposure area and a part for described first conductive layer, align with described flatness layer to realize described first conductive layer.
3. manufacture method according to claim 1, it is characterized in that, the step of the described flatness layer of above-mentioned coating also comprises and exposing described flatness layer, wherein, between the step and the step forming described second insulation course of described first conductive layer of above-mentioned deposition, this manufacture method also comprises:
Utilize developer solution to remove a part for described flatness layer corresponding to exposure area and a part for described first conductive layer, align with described flatness layer to realize described first conductive layer.
4. manufacture method according to claim 1, is characterized in that, between the step and the step forming described second insulation course of described first conductive layer of above-mentioned deposition, this manufacture method also comprises:
Be coated with a photoresist layer in the top of described first conductive layer, and described photoresist layer and described flatness layer are exposed;
Utilize a part for the described flatness layer of developer solution removal corresponding to exposure area, a part for described first conductive layer and a part for described photoresist layer; And
First conductive layer described in wet etching thus the described photoresist layer peeled off above it, back out distance with what control described first conductive layer.
5. manufacture method according to claim 1, is characterized in that, described flatness layer is an organic planarization layer.
6. manufacture method according to claim 1, is characterized in that, this manufacture method also comprises:
Form a first metal layer in the top of a substrate, by the grid of described the first metal layer definition thin film transistor (TFT);
Form a gate insulator in the top of described the first metal layer; And
Form one second metal level in the top of described gate insulator, define source electrode and the drain electrode of described thin film transistor (TFT) by described second metal level, wherein, the drain electrode of described thin film transistor (TFT) is electrically coupled to described second conductive layer via a via hole.
7. manufacture method according to claim 1, is characterized in that, described first conductive layer and described second conductive layer are tin indium oxide material.
8. manufacture method according to claim 7, is characterized in that, described first conductive layer is a common electrode, and described second conductive layer is a pixel electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510473786.3A CN105068292A (en) | 2015-08-05 | 2015-08-05 | Manufacturing method for AHVA panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510473786.3A CN105068292A (en) | 2015-08-05 | 2015-08-05 | Manufacturing method for AHVA panel |
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| CN105068292A true CN105068292A (en) | 2015-11-18 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108183111A (en) * | 2017-12-08 | 2018-06-19 | 友达光电股份有限公司 | Pixel array substrate |
| WO2019072120A1 (en) * | 2017-10-11 | 2019-04-18 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor and display device |
-
2015
- 2015-08-05 CN CN201510473786.3A patent/CN105068292A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019072120A1 (en) * | 2017-10-11 | 2019-04-18 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor and display device |
| US11710747B2 (en) | 2017-10-11 | 2023-07-25 | Ordos Yuansheng Optoelectronics Co., Ltd. | Array substrate, manufacturing method thereof, and display device |
| CN108183111A (en) * | 2017-12-08 | 2018-06-19 | 友达光电股份有限公司 | Pixel array substrate |
| TWI645557B (en) * | 2017-12-08 | 2018-12-21 | 友達光電股份有限公司 | Pixel array substrate |
| US20190179207A1 (en) * | 2017-12-08 | 2019-06-13 | Au Optronics Corporation | Pixel array substrate |
| US10718985B2 (en) * | 2017-12-08 | 2020-07-21 | Au Optronics Corporation | Pixel array substrate |
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