CN105048994A

CN105048994A - Distributed algorithm applied to FIR filters

Info

Publication number: CN105048994A
Application number: CN201510370425.6A
Authority: CN
Inventors: 凌春丽; 顾文军; 陈长华; 徐佰新; 赵健
Original assignee: Wuxi China Resources Semico Co Ltd
Current assignee: Wuxi China Resources Semico Co Ltd
Priority date: 2015-06-30
Filing date: 2015-06-30
Publication date: 2015-11-11

Abstract

The present invention relates to digital filter field,More particularly to a kind of distributed algorithm applied to FIR filter,Comprising steps of analog input signal X [n] is converted to B position digital signal through analog-to-digital conversion module; It is handled using B position digital signal as shift register is entered data into,Processing result is sent to string and module; It goes here and there and input data is transferred to binary digit and weighs multiplier module by module,According to binary system power and position rearrange output to and go here and there module; And go here and there module by input data according to 20,21,..,2B-1,It is divided into B group bit flow data; B group bit flow data has respectively entered n group look-up table means while being tabled look-up and add operation,And according to two-dimensional DA algorithmic formula B group output data is calculated to get filtered output signal Y [n] out. Present invention saves memory resources and logic unit, have sufficiently used FPGA resource.

Description

A kind of distributed algorithm being applied to FIR filter

Technical field

The present invention relates to digital filter (i.e. FIR filter) field, be specifically related to a kind of distributed algorithm being applied to FIR filter.

Background technology

Existing FIR filter is mainly applied in touch control circuit, such as: just used FIR filter in the existing touch screen control circuit CS9603 product commercially sold.At present, what existing FIR filter adopted is that Direct-type accumulation structure directly uses multiplier and adder to realize convolution algorithm, thus reaches filtering object.

As shown in Figure 1, it is the block diagram that existing FIR filter is applied to periphery circuit, wherein filter configuration (fir_mcu_if) module receives the action that address that main control chip sends, data, filter coefficient and the information such as enable control filter, adopts standard time sequence.Data processing (Data_process) module is by the scanning of configuration requirement judgment frame, line scanning, whether uses the information such as upper lower limit value, carries out data processing.

Due to ADC(digital-to-analogue conversion) be 9 level production line ADC, 2 every grade, so be that 18 adc data are supplied to wired impulse response (fir) module altogether, time unifying (time_align) module inside fir module deposits 2 bit data of 8 grades above, Deng 2 bit data of the 9th grade out after, the data of the data of depositing above and the 9th grade are combined into 18 bit data through data correction (digital_correction) module, remove error, generate effective 10 adc data, later, each adc clock has effective adc data.

10 adc data, first through a comparison circuit, compare its bound, when exceeding in limited time, represent by higher limit, when being less than lower prescribing a time limit, representing, if when dropping in region, represent with original value by lower limit.Whether this circuit can be opened by software control, and default situations is closed.

10 adc data are multiplied by 11 sign filter coefficient, product is 21 signed numbers, these 21 signed numbers are just as median, if consideration register, that each point must have, 32 row are multiplied by 18 row, 576 21 must be had to have sign register, can waste area, final realization is write in fir_sram by 21 signed numbers, when descending secondary, reading out from fir_sram.

Each adc clock carrys out effective 10 bit data, from fir_sram read data, should write data again at the rising edge of adc clock, for single port fir_sram, has no idea to realize.Present implementation method is 2 frequencies that fir_sram is operated in adc clock, if adc is 2.5MHz, so fir_sram is operated in 5MHz clock zone, before adc clock, the half period reads accumulated value last time from fir_sram, the accumulated value read out and currency are multiplied by filter coefficient and are added, and write in fir_sram in the later half cycle of adc clock.

Existing FIR filter substantially all adopts Convolution-type, Direct-type structural design, and this structure needs to combine multiple adder, shift unit and multiplier to realize.Due to multiplier, to take resource too large, and these those skilled in the art propose again the multiplier that application shifter-adder unit comes in alternative Direct-type in succession, but the resource utilization of this kind of structure to field programmable gate array (FPGA) is too low.Take the too large and problem too low to FPGA resource utilance of resource have a class processing method based on distributed algorithm to solve multiplier, this two-dimentional algorithm have employed shift add method to reduce the use of memory, and add time delay module, avoid the confusion brought because of timing Design, ensure the correctness of Output rusults.Also be adding due to time delay module, employ too many shift unit, counteract the memory resource that shifter-adder module is saved, in fact do not save memory resource and logical block (LE).

Summary of the invention

Object of the present invention will solve Problems existing in background technology exactly, provide a kind of distributed algorithm being applied to FIR filter, this distributed algorithm is the further improvement to existing Two dimensional Distribution formula algorithm, method after improvement, for designing the new structure of FIR filter, can save more logical block and memory resource.

In order to solve the problems of the technologies described above, the technical solution adopted in the present invention is: a kind of distributed algorithm being applied to FIR filter, based on existing FIR filter circuit, comprise analog-to-digital conversion module, shift register, string is module also, and go here and there module and look-up table means, it is characterized in that, binary digit power multiplier module is also add in described distributed algorithm, this distributed algorithm comprises the following steps: (1) analog input signal X [n] is input in FIR filter, analog input signal X [n] is converted to B position digital signal through analog-to-digital conversion module, wherein B is positive integer, (2) described B position digital signal is entered shift register as input data, result is delivered to string and module by shift register, (3) described string module will input transfer of data to binary digit power multiplier module, and this module is carried out rearranging according to binary system power and position and exported to and go here and there module, it is (4) described and go here and there module and will input data according to 20,21 ..., 2B-1, is divided into B group bit flow data, (5) B group bit flow data enters into n group look-up table means respectively and carries out tabling look-up and add operation simultaneously, and according to the DA algorithmic formula of two dimension calculate B group and export data, namely draw filtered output signal Y [n], in formula, b represents b bit of input data, and B represents total bit of input data, and n represents the n-th data, and (N+1)/2=P*M, M is the input figure place of look-up table in addition, and P is the number of look-up table under each parallel-serial conversion.

The invention has the beneficial effects as follows: adopt binary digit to weigh the look-up table means of multiplier module in FIR filter in distributed algorithm disclosed by the invention and be combined, instead of the time delay module adopted in existing distributed algorithm, achieve making full use of the look-up table resource in FPGA, save logical block and memory resource, save this kind of module taken compared with multiple resource of multiplier, fully use FPGA resource efficiently, between area-speed, find an appropriate balance point.

Accompanying drawing explanation

Fig. 1, existing FIR filter is applied to the block diagram of periphery circuit;

Fig. 2, the FIR filter steps flow chart block diagram in the specific embodiment of the invention.

Embodiment

Below in conjunction with accompanying drawing, the specific embodiment of the present invention and operation principle are described.

As shown in Figure 2, it is steps flow chart block diagram distributed algorithm of the present invention being applied to existing FIR filter, binary digit power multiplier module is also applied in the realization of the method, this distributed algorithm comprises the following steps: (1) analog input signal X [n] is input in FIR filter, analog input signal X [n] is converted to B position digital signal through analog-to-digital conversion module, and wherein B is positive integer; (2) described B position digital signal is entered shift register as input data.Result is delivered to string and module by shift register; (3) described string module will input transfer of data to binary digit power multiplier module, and this module is carried out rearranging according to binary system power and position and exported to and go here and there module; (4) described and go here and there module and will input data according to 2 ⁰, 2 ¹..., 2 ^b-1, be divided into B group bit flow data; (5) B group bit flow data enters into n group look-up table means respectively and carries out tabling look-up and add operation simultaneously, and according to the DA algorithmic formula of two dimension

Calculate B group and export data, namely draw filtered output signal Y [n]; In formula, b represents b bit of input data, and B represents total bit of input data, and n represents the n-th data; (N+1)/2=P*M, M is the input figure place of look-up table in addition, and P is the number of look-up table under each parallel-serial conversion, l=0,1 ..., m-1, p=0,1 ..., p-1.

Embodiment: the present embodiment is for 31 rank FIR filter, analog input signal X [n] obtains 8 position digital signals through analog-to-digital conversion, shift register is entered as input data, result is delivered to string and module by shift register group, input data are carried out rearranging according to binary system power and position and exports to and go here and there module, and go here and there module input data are divided into 8 groups of bit flow datas, enter look-up table means respectively to carry out tabling look-up and add operation simultaneously, when entering binary digit power multiplier module, 8 data are ready, need process 8 data in one-period simultaneously, to avoid the data collision with next cycle.By Parameter N=31, N+1 is resolved into the product of P, M two positive integers, makes m=0,1 ..., M-1, p=0,1 ..., P-1; B=8 (figure place of digital signal), b=0,1 ..., 7; N represents the n-th data, and these parameters are substituted into formula , draw output signal Y [n].

Application binary position of the present invention power multiplication (* 2 ⁿ) module, just can ensure the correctness of Output rusults.Otherwise the realization of existing distributed algorithm just need increase time delay module to ensure the correctness of Output rusults.But adding of time delay module, employ too many shift unit, counteract the memory resource that shifter-adder module is saved.The present invention is the consumption for reducing memory resource and logical block, to the further optimization of time delay and shifter-adder module.

Claims

1. one kind is applied to the distributed algorithm of FIR filter, based on existing FIR filter circuit, comprise analog-to-digital conversion module, shift register, string module go here and there module and look-up table means, it is characterized in that, also apply binary digit power multiplier module in described distributed algorithm, this distributed algorithm comprises the following steps:

(1) analog input signal X [n] is input in FIR filter, and analog input signal X [n] is converted to B position digital signal through analog-to-digital conversion module, and wherein B is positive integer;

(2) described B position digital signal is entered shift register as input data, result is delivered to string and module by shift register;

(3) described string module will input transfer of data to binary digit power multiplier module, and this module is carried out rearranging according to binary system power and position and exported to and go here and there module;

(4) described and go here and there module and will input data according to 2 ⁰, 2 ¹..., 2 ^b-1, be divided into B group bit flow data;

(5) B group bit flow data enters into n group look-up table means respectively and carries out tabling look-up and add operation simultaneously, and according to the DA algorithmic formula of two dimension calculate B group and export data, namely draw filtered output signal Y [n]; In formula, b represents b bit of input data, and B represents total bit of input data, and n represents the n-th data; (N+1)/2=P*M, N is filter order in addition, and M is the input figure place of look-up table, and P is the number of look-up table under each parallel-serial conversion, l=0,1 ..., m-1, p=0,1 ..., p-1.