CN105023840B - 具有凹陷沟道的应变半导体装置以及形成该装置的方法 - Google Patents
具有凹陷沟道的应变半导体装置以及形成该装置的方法 Download PDFInfo
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- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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- H—ELECTRICITY
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Abstract
本发明提供一种具有应力沟道(strained channel)的半导体装置以及制造该装置的方法。此半导体装置具有形成在沟道凹陷上的栅极。以应力引发材料(stress‑inducing material)填入形成于栅极两侧的第一凹陷及第二凹陷,该应力引发材料扩展进入源极/漏极延伸(source/drain extension)与栅极边缘重叠的区域。在一实施例中,沟道凹陷及/或第一与第二凹陷的侧壁可为沿着{111}刻面。本发明相较于其他已知***可在沟道区显示较高且较均匀的应力。
Description
本申请是申请号为201010250734.7、申请日为2010年8月10日、发明名称为“具有凹陷沟道的应变半导体装置以及形成该半导体装置的方法”的发明专利申请的分案申请。
技术领域
本发明涉及一种半导体装置,特别涉及一种具有凹陷沟道的互补型金属氧化物半导体(CMOS)晶体管及其形成方法。
背景技术
过去数十年间,金属氧化物半导体场效应晶体管(MOSFETs)尺寸的缩减,包括栅极长度及栅极氧化层厚度的缩减,使得集成电路的速度、性能、密度及每单元功能成本能够持续进步。为了更进一步加强晶体管的表现,已利用在半导体基板的部分的应变沟道区制作金属氧化物半导体场效应晶体管装置。应变沟道区可增强载流子迁移率,从而增进在n-沟道(NMOSFET)或p-沟道(PMOSFET)时的表现。一般而言,可在NMOSFET晶体管的n沟道中,在源极到漏极的方向引发伸张应力以增加电子迁移率,而在PMOSFET晶体管的p沟道中,在源极到漏极的方向引发压缩应力以增加空穴迁移率。现有多个方法将应力引进晶体管沟道区。
方法之一是通过在源极/漏极区的基板中形成凹陷以引进沟道区的应力。例如,在源极/漏极区的凹陷区中,可通过外延生长一应力引发层,如硅锗,其相较于硅具有较大晶格结构,如此可在硅基板上形成在沟道区具有压缩应力的PMOS装置。相似的,在源极/漏极区的凹陷区中,可通过外延生长一应力引发层,如碳化硅,其相较于硅具有较小晶格结构,如此可在硅基板上形成沟道区具有伸张应力的NMOS装置。
在此方法中,应力引发层限于在源极/漏极区中较重掺杂的区域,因此源极/漏极延伸区或栅极与源极/漏极延伸区的重叠区对于沟道区的应力,具有极少或几乎不具贡献性。
发明内容
为克服现有技术的缺陷,在一实施例中,提供一半导体装置,该半导体装置包含基板、在基板上的栅极介电材料及在栅极介电材料上的栅极。栅极置放于基板的凹陷中,而在栅极两侧的源极/漏极区包括一应力引发材料,使得应力引发材料扩展进入源极/漏极的延伸与栅极边缘重叠的区域。该栅极下的凹陷可有侧壁具{111}表面方向且为U型或其类似形状。
在另一实施例中,提供具应力沟道区的半导体装置的形成方法,并提供具虚置栅极以及在虚置栅极两侧的第一凹陷及第二凹陷的基板,该第一及第二凹陷以应力引发材料填塞。移除虚置栅极而在第一凹陷与第二凹陷中间形成第三凹陷。在第三凹陷的底部形成栅极介电材料,并且在该栅极介电材料上形成栅极。第一凹陷及第二凹陷扩展至栅极下方,而进入源极/漏极的延伸与栅极边缘重叠的区域。
在另一实施例中,提供一种形成半导体装置的方法,包括:在一基板上形成一第一栅极;在该第一栅极两侧的该基板中形成一第一应力引发区及一第二应力引发区;在该第一栅极两侧的该基板中形成源极/漏极延伸;移除该第一栅极;在该基板中的该第一应力引发区及该第二应力引发区之间形成一沟道凹陷,该第一应力引发区及该第二应力引发区扩展进入源极/漏极延伸与该沟道凹陷重叠的一区域;以及在该沟道凹陷上形成一第二栅极,其中该沟道凹陷在{111}刻面具有一侧壁。
在另一实施例中,提供一种半导体装置,包括:一基板;一栅极介电材料,位于该基板上;一栅极,位于该栅极介电材料上,该栅极设于该基板中的一第一凹陷上,其中该第一凹陷在{111}刻面具有一侧壁;源极/漏极区,位于该栅极两侧的基板中,该源极/漏极区包括一应力引发材料位于该栅极两侧该基板的一第二凹陷及一第三凹陷中,该应力引发材料扩展至该栅极下且未与该栅极介电材料直接接触;以及凸起的源极/漏极延伸,形成在该栅极两侧的该基板中,且该凸起的源极/漏极延伸的上表面位于该第一凹陷的底表面上,其中该应力引发材料扩展进入该凸起的源极/漏极延伸与该栅极重叠的区域。
本发明相较于其他已知***可在沟道区显示较高且较均匀的应力。
为让本发明的上述及其他目的、特征、及优点能更明显易懂,下文特举出较佳实施例,并配合附图,作详细说明如下。
附图说明
图1~图4为一系列剖面图,说明一实施例形成半导体装置的中间阶段。
图5~图6为一系列剖面图,说明另一实施例形成半导体装置的中间阶段。
【主要附图标记说明】
100~基板 102~晶体管
104~虚置栅极 105~虚置栅极介电层
106~间隔物 108~应力区
110~硅化区 114~介电层
414~栅极介电层 416~栅极
518~沟道凹陷 620~栅极介电材料
622~栅极 312~沟道凹陷
112~源极/漏极延伸
具体实施方式
以下详细讨论实施例的制作与使用,然而,本发明公开所提供许多可应用的发明概念可实施于多种广泛的个别内容上。所讨论的特定的实施例仅为说明特定制作及使用实施例的方法,而非用以限制本发明公开的保护范围。
以下将详细解释在源极及漏极区中利用应力引发层的一实施例。应力引发层扩展进入源极/漏极延伸(source/drain extension, SDE)区,从而在沟道区发挥更大的应力。更进一步的,沟道区本身凹陷,造成凸起的源极/漏极的延伸区扩展到栅极介电层的底部表面之上。因此,部分实施例可在驱动电流Ion增加时改善短沟道效应。
图1至图4根据一实施例说明具有应力凹陷沟道区的半导体装置的制造方法。首先,图1显示根据一实施例的部分基板100,该基板100上形成晶体管102。该基板100可包含为掺杂或未掺杂的硅块材,或绝缘层上覆半导体(semiconductor-on-insulator,SOI)基板的有源层。一般而言,SOI包含于绝缘层上形成的一层半导体材料如硅。该绝缘层举例来说可为埋入氧化物(buried oxide,BOX)层或氧化硅层。该绝缘层在基板上,该基板通常为硅或玻璃基板。其他可使用的基板如多层或梯度基板。该基板也可为锗基板、锗硅基板、Ⅲ-Ⅴ族基板或其类似基板。
以下将详述在源极/漏极区的基板中形成的一个凹陷,且该凹陷的侧壁较佳为具有{111}表面方向。为得具该{111}表面方向凹陷的侧壁,基板100较佳具有{100}或{110}的表面方向,然而其他方向也可使用。
晶体管102包括虚置栅极104及形成于虚置栅极104旁边的间隔物106。虚置栅极可用任何适当材料形成,然而,形成虚置栅极104的材料,相较于制造间隔物106的材料,以具有高度蚀刻选择性的材料为佳,因为如下面详述,随后将在工艺步骤中移除虚置栅极104。在一实施例中,沉积及再结晶非晶硅以制造多晶硅。在一虚置栅极为多晶硅的实施例中,该虚置栅极104可通过低压化学气相沉积(LPCVD)来沉积掺杂或未掺杂的多晶硅,使其厚度约在200至1000埃范围间。以这种方式,虚置栅极可与真实栅极同时或分别形成于基板100的不同处,使单一晶片/裸片上的装置具有不同操作特性。应注意可如图1所示,将虚置栅极介电层105***基板100及虚置栅极104之间。在部分实施例中,在移除虚置栅极104时,相较于虚置栅极104及基板100,使用虚置栅极介电层105可使其有较佳的蚀刻选择性。虚置栅极介电层105可包含任何适当的介电层,包括与基板100有高度蚀刻选择性的材料如氧化硅、氮氧化硅、二氧化铪、氧化硅铪(HfSiO)、氮氧化硅铪(HfSiON)、氧化钽铪(HfTaO)、氧化钛铪(HfTiO)、氧化锆铪(HfZrO)、其他适合的高介电常数材料及/或上述的组合。
可通过将介电层沉积及图案化而形成间隔物106。在一实施例中,介电层可包含一个单层或多于两层,各包含氧化物、氮化硅、氮氧化硅及/或其他介电材料。该介电层的形成可通过任何适合的技术如等离子体化学气相沉积(PECVD)、低压化学气相沉积(LPCVD)、次压化学气相沉积(sub-atmospheric chemical vapor deposition,SACVD)及其类似方法。介电层而后进行图案化以形成间隔物106,其中可由湿蚀刻或干蚀刻择一进行图案化。移除介电层的水平部分,而剩余部分如图1所示形成间隔物106。应注意得是,虽然图中仅显示单一间隔物以说明,但也可形成多间隔物、衬层(liners)、及/或其类似物以在源极/漏极中得到所欲的掺杂轮廓。
图1也显示源极/漏极中的应力区108在虚置栅极104的两侧。根据一实施例,该应力区108由应力引发材料形成而造成应力沟道区。在源极/漏极区的凹陷区中,可通过外延生长一应力引发层,如硅锗,其相较于硅具有较大晶格结构,如此可在硅基板上形成在沟道区具有压缩应力的PMOS装置。相似的,在源极/漏极区的凹陷区中,可通过外延生长一应力引发层,如碳化硅,其相较于硅具有较小晶格结构,如此可在硅基板上形成沟道区具有伸张应力的NMOS装置。
可通过具晶格表面选择性的湿蚀刻工艺形成该凹陷,举例来说可在体积浓度1至10%及温度范围在15至50℃下使用羟化四甲铵(TMAH)溶液。在另一实施例中,也可使用其他对于(100)硅基板具晶格表面选择性的湿蚀刻溶液如氢氧化铵(NH4OH)、氢氧化钾或氨类蚀刻溶液。该具选择性湿蚀刻暴露出硅基板100的{111}表面,而凹陷的侧壁具{111}表面方向。应注意可依特定应用改变该凹陷及应力引发材料的位置。在一实施例中,应力区108扩展至虚置栅极104下。
应力区108的接触表面可进行硅化,从而形成硅化区110。如现有技术,硅化区110的形成可通过毯覆性沉积(blanket deposition)一薄层如镍、铂、钴及其组合。而后加热该基板100而造成硅与金属接触的地方反应。反应后,形成一层金属硅化物,而后通过会蚀刻金属但不会蚀刻硅化物的蚀刻剂选择性的移除未反应的金属。
图1还说明源极/漏极延伸112例如轻掺杂漏极(lightly-doped drains,LDDs)。在一实施例中,应力区108扩展入源极/漏极延伸112,从而在源极/漏极延伸(SDE)及沟道区提供额外的应力。如图1所示,源极/漏极延伸112及应力区108扩展至栅极下,使应力区108扩展至源极/漏极延伸112与虚置栅极104边缘重叠的区域。在一实施例中,应力区108扩展超过虚置栅极104约20埃至100埃的距离。
应注意源极/漏极区可包含任何适合的掺杂轮廓,而可通过任何适合的工艺包含任何适合的间隔物、衬层及/或牺牲衬层/间隔物。举例来说,源极/漏极延伸112及重掺杂区可利用间隔物106及/或不同间隔物及/或额外的间隔物于原位(in situ)形成,或在具应力的源极/漏极区形成之后形成。在另一个例子中,源极/漏极延伸112及重掺杂区皆形成于凹陷形成之后,该凹陷例如以注入、扩散或其类似方法形成。再者,也可使用其他掺杂区如阱、晕状/口袋注入(halo/pocket implants)及/或其类似方法。
在基板100上形成介电层114而暴露出虚置栅极104。介电层114可由任何适合的介电材料如那些介电常数约为或小于4.0的介电材料组成。可用来制作介电层114的材料包括氧化硅或二氧化硅、类钻碳(diamond-like carbon)、氟硅玻璃(fluorinated silicateglass or fluorinated silicon oxide glass,FSG)、掺碳氧化硅(SiOxCy)、旋涂玻璃(Spin-On-Glass)、旋涂聚合物(Spin-on-Polymer)、碳硅材料、其化合物、其复合物、其组合或其类似物。该介电层114可由多层组成,包括一层或多层蚀刻停止层。
该介电层114可由任何适当的方法形成。在一实施例中,介电层114含氧化物,其形成是通过化学气相沉积技术利用四乙基原硅酸盐(TEOS)及氧作为前趋物。在一实施例中,形成介电层114的厚度足以覆盖晶体管102及一平坦化工艺,如以化学机械研磨(chemicalmechanical polish,CMP)使表面平坦化且暴露出虚置栅极104。
请参见图2,移除虚置栅极104及虚置栅极介电层105(参考图1)。在虚置栅极104以多晶硅形成的一实施例中可使用蚀刻工艺,该蚀刻工艺利用如羟化四甲铵(TMAH)、氢氧化铵(NH4OH)或其类似物。该蚀刻工艺应选择可移除虚置栅极104,而源极/漏极延伸112及/或间隔物106不会受到严重的损害的工艺。若具有该虚置栅极介电层105时,则可通过如氢氟酸移除,以暴露出基板100的表面。在移除虚置栅极介电层105时可移除部分介电层114。另可选择在介电层114上形成保护层如氮化硅层,以在移除虚置栅极介电层105时保护介电层114。
图3为根据一实施例说明沟道凹陷312的形成。沟道凹陷312的形成可通过例如以氢氧化钾或羟化四甲铵溶液湿蚀刻,例如该氢氧化钾溶液为约45%体积的氢氧化钾溶于水中。如上述的蚀刻工艺相较于{111}刻面,对于(100)及(110)平面具有较高的蚀刻速率。因此,如图3所示沟道凹陷312的侧壁是延着{111}刻面。在一实施例中,沟道凹陷312的厚度约2至15纳米,例如约5纳米。如图3所示,沟道凹陷312使源极/漏极延伸112之上表面位于沟道凹陷312底表面上,从而创造凸起的源极/漏极延伸(SDEs)112。更进一步在一实施例中,应力引发材料的上表面扩展至沟道凹陷312底表面之上。
在一实施例中,沟道凹陷312并未扩展至应力区108以避免或减少因在后续工艺步骤中所形成的栅极介电层与应力区108的材料直接接触所造成的问题。在上述实施例中,以氢氧化钾或羟化四甲铵溶液蚀刻而暴露出{111}刻面,蚀刻位置的偏移造成一层基板100插在应力区108及沟道凹陷312间。在使用40原子%锗成分的P型金属氧化物半导体(PMOS)晶体管的TCAD(半导体工艺模拟及器件模拟工具)模拟中,该晶体管102的相对应力引发的驱动电流的增益,相较于传统晶体管约可增加10%。在另一电子模拟MEDICI中,当最小栅长度为24纳米时,空腔/晕状注入可大幅减少,并增加约9%的驱动电流Ion且获得15mV漏极引致势垒降低(drain induced barrier lowering,DIBL)。在上述条件下,可降低短沟道效应。
其后,如图4所示,形成栅极介电层414及栅极416。栅极介电层414可包含至少一种材料如氧化物、氮化物、氮氧化物及其他栅极介电材料。在实施例中,栅极介电层414可包括一介面层(interfacial layer)如氧化硅层,以及在介面层上的高介电常数介电层。在实施例中,高介电常数介电层可包括二氧化铪、氧化硅铪(HfSiO)、氮氧化硅铪(HfSiON)、氧化钽铪(HfTaO)、氧化钛铪(HfTiO)、氧化锆铪(HfZrO)、其他适合的高介电常数材料及/或上述的组合。该高介电常数材料还可由下择之:金属氧化物、金属氮化物、金属硅化物、过渡金属氧化物、过渡金属氮化物、过渡金属硅化物、金属氮氧化物、金属铝、锆、硅酸盐、铝酸锆、氧化硅、氮化硅、氮氧化硅、氧化锆、氧化钛、氧化铝、二氧化铪-氧化铝合金、其他适合的材料及/或上述的组合。栅极介电层414的厚度约为10至50埃。
栅极416可包括导电材料如金属(如钽、钛、钼、钨、铂、铝、铪或钌)、金属硅化物(如硅化钛、硅化钴、硅化镍或硅化钽)、金属氮化物(如氮化钛或氮化钽)、掺杂多晶硅(dopedpoly-crystalline silicon)、其他导电材料或上述的组合。
依照形成栅极介电层414及栅极416的工艺而定,可视需要执行平坦化工艺。更详细的说,部分沉积方法如化学气相沉积工艺会形成顺应层(conformal layer),因而可执行平坦化工艺如磨平(grinding)或化学机械研磨(CMP)工艺,以创造如图4所示的平坦表面。若使用其他方法如掩模(masking)及电镀,则可不需要CMP工艺。
也可执行其他适合特定应用的后段工艺(BEOL)技术。举例来说,可执行金属化/金属间介电层(inter-metal dielectric layer)工艺、内连线结构(interconnectstructure)工艺、封装(encapsulant)工艺、切割(singulation)工艺等。
图5及图6根据另一实施例说明半导体装置的形成方法。图5及图6描述的工艺是假设已执行图1及图2的前叙述的工艺。在此假设下,在图2之后,图5说明制作沟道凹陷518的工艺,该工艺是利用类等离子体(plasma-like)干蚀刻工艺,在变压耦合等离子体(transformer-coupling-plasma)以溴化氢在氦气及氧气中流速为5至50sccm,压力为1至20mtorr,偏压为30至100V的条件下进行。利用如上述的工艺,沟道凹陷518呈现U型轮廓,是因蚀刻工艺对于不同晶体方向的选择性并不如之前所述参考图3的蚀刻选择性佳。
而后如图6所示,可形成栅极介电材料620及栅极622。可通过参考图3上述用来形成栅极介电层414与栅极416的相似工艺及相似材料形成栅极介电材料620及栅极622。
之后也可执行其他适合特定应用的后段工艺(BEOL)技术。举例来说,可执行金属化/金属间介电层(inter-metal dielectric layer)工艺、内连线结构(interconnectstructure)工艺、封装(encapsulant)工艺、切割(singulation)工艺等。
上述实施例相较于其他已知***,在沟道区明显产生更多的应力。已知***如利用具尖端扩展至源极/漏极延伸(SDE)区下的应力区的***,或具有凸起尖端更靠近基板的上表面的应力区,但实质上并未扩展进入源极/漏极延伸(SDE)区与栅极重叠的区域。可发现上述实施例相较于其他已知***可在沟道区显示较高且较均匀的应力。
虽然本发明已以多个较佳实施例公开如上,然其并非用以限定本发明,任何本领域普通技术人员,在不脱离本发明的精神及范围内,当可作任意的更动与润饰,因此本发明的保护范围当视所附的权利要求所界定的范围为准。
Claims (9)
1.一种形成半导体装置的方法,包括:
在一基板上形成一第一栅极;
在该第一栅极两侧的该基板中形成一第一应力引发区及一第二应力引发区;
在该第一栅极两侧的该基板中形成源极/漏极延伸;
移除该第一栅极;
在该基板中的该第一应力引发区及该第二应力引发区之间形成一沟道凹陷,该第一应力引发区及该第二应力引发区扩展进入源极/漏极延伸与该沟道凹陷重叠的一区域;以及
在该沟道凹陷上形成一栅极介电材料及一第二栅极,该第一应力引发区及该第二应力引发区的材料未与该栅极介电材料直接接触,且该源极/漏极延伸与该栅极介电材料直接接触;
其中该沟道凹陷在{111}刻面具有一侧壁。
2.根据权利要求1所述的方法,其中形成该沟道凹陷至少部分是以氢氧化铵或羟化四甲铵溶液进行蚀刻。
3.根据权利要求1所述的方法,其中形成该沟道凹陷,从而创造凸起的源极/漏极延伸,该凸起的源极/漏极延伸的上表面位于该沟道凹陷的底表面上。
4.根据权利要求1所述的方法,其中该基板包括具有{100}或{110}表面方向的硅块材。
5.根据权利要求1所述的方法,其中该沟道凹陷的厚度介于2至15纳米。
6.根据权利要求1所述的方法,其中该第一应力引发区扩展超过该第一栅极20埃至100埃的距离。
7.一种半导体装置,包括:
一基板;
一栅极介电材料,位于该基板上;
一栅极,位于该栅极介电材料上,该栅极设于该基板中的一第一凹陷上,其中该第一凹陷在{111}刻面具有一侧壁;
源极/漏极区,位于该栅极两侧的基板中,该源极/漏极区包括一应力引发材料位于该栅极两侧该基板的一第二凹陷及一第三凹陷中,该应力引发材料扩展至该栅极下且未与该栅极介电材料直接接触;以及
凸起的源极/漏极延伸,形成在该栅极两侧的该基板中,该凸起的源极/漏极延伸的上表面位于该第一凹陷的底表面上,且该凸起的源极/漏极延伸与该栅极介电材料直接接触,
其中该应力引发材料扩展进入该凸起的源极/漏极延伸与该栅极重叠的区域。
8.根据权利要求7所述的半导体装置,其中该基板包括具有{100}或{110}表面方向的硅块材。
9.根据权利要求7所述的半导体装置,其中该应力引发材料扩展超过该栅极20埃至100埃的距离。
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