CN105021865A - A voltage measurement method allowing compensation - Google Patents
A voltage measurement method allowing compensation Download PDFInfo
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- CN105021865A CN105021865A CN201510304278.2A CN201510304278A CN105021865A CN 105021865 A CN105021865 A CN 105021865A CN 201510304278 A CN201510304278 A CN 201510304278A CN 105021865 A CN105021865 A CN 105021865A
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Abstract
The invention discloses a voltage measurement method allowing compensation. According to the method, through measuring of current values superposed on a ground wire for two times, measured voltages of two times can be obtained through measurement; test equipment can obtain values obtained through two times of voltage measurement, so that contact resistance of the ground wire can be obtained; then a voltage value output by the measured chip, i.e. the voltage value obtained after voltage compensation, can be calculated. The method eliminates adverse influences caused by different contact resistances due to contact failures, thereby enabling accurate voltage measurement and rise in the precision of the voltage measurement.
Description
Technical field
The invention belongs to the technical field of chip, particularly chip voltage detection method.
Background technology
Digital-analog mix-mode chip generally has internal reference voltage, in order to ensure absolute precision and the consistance of reference voltage, chip dispatch from the factory Shi Douhui volume production test in carry out reference voltage calibration.Although it is very high that the reference voltage of chip own can be calibrated to precision, measuring accuracy can be affected because chip contacts situation with tester table, so precision voltage reference calibration is the contact situation being limited to chip and tester table.Contact situation is embodied in contact resistance difference, thus affects voltage calibration precision.
Patented claim 201210312733.X discloses a kind of output voltage of internal power source of chip measuring system and method.This output voltage of internal power source of chip measuring system comprises: test machine and probe; Wherein said test machine is connected to chip to be measured by described probe; Wherein, described test machine comprises driving voltage applying unit and Power Management Unit; And wherein, described driving voltage applying unit be used for internally Power supply to guarantee the accuracy that power supply supplies; Described Power Management Unit is used for described to described chip applying drive current to be measured, to measure the internal electric source output voltage of described chip to be measured; And wherein, the first passage of described test machine and second channel are connected to an input port of described probe at the mutual short circuit of output terminal; And the described input port of described probe corresponds to a pin of described chip to be measured.。
Summary of the invention
For solving the problem, the object of the present invention is to provide a kind of compensable voltage measurement method, the method provides a kind of compensable voltage measurement method, the contact situation different with measuring equipment to chip under test can carry out voltage compensation to improve voltage measurement accuracy.
For achieving the above object, technical scheme of the present invention is as follows.
A kind of compensable voltage measurement method, it is characterized in that the method can be measured by the current value that twice measurement is superimposed upon ground wire and obtain twice measuring voltage, testing apparatus is obtainable twice voltage tester value also, obtain the contact resistance of ground wire thus, calculate the magnitude of voltage that chip under test exports afterwards, namely carry out the magnitude of voltage after voltage compensation, the process eliminate the harmful effect because loose contact causes contact resistance difference to cause, can measuring voltage exactly, improve the precision of voltage measurement.
Described method, the reference voltage of first time testing apparatus measurement chip under test is VBC, and the reference voltage of the actual output of chip under test is VEF, owing to there is contact resistance between the ground pin of testing apparatus and the ground pin CF ground wire of testing apparatus, can following formula be obtained:
VBC＝VEF+I1*(R0+R0X) ……(1)
When second time is tested, testing apparatus need supply the power pins A end power supply of chip under test in testing apparatus, the extra drive current increasing the common input and output pin I2 of chip under test simultaneously, then the electric current of the testing apparatus supply power pins of chip under test and the power pins AD of chip under test is I1+I2;
Simultaneously, testing apparatus need be held to be held by the common input and output pin I of the chip under test of chip under test at the pin H of the Geied current excitation of testing apparatus and be poured into electric current I 2 to chip under test, then the electric current of the ground pin of testing apparatus and the ground pin CF of testing apparatus is I1+I2, the reference voltage that testing apparatus measures chip under test is VBC2, and the reference voltage of the actual output of chip under test is VEF, can following formula be obtained:
VBC2＝VEF+(I1+I2)*(R0+R0X) ……(2)
By formula (1), (2) can obtain
(R0+R0X)＝(VBC2-VBC)/I2 ……(3)
VEF＝VBC-I1*(VBC2-VBC)/I2 ……(4)
By the result of twice test, then formula (4) just accurately can draw the reference voltage level that chip exports, and wherein I1* (VBC2-VBC)/I2 is that contact resistance compensates the magnitude of voltage of returning.
The present invention, by twice voltage measurement to chip under test, obtains twice voltage tester value, obtains the contact resistance of ground wire thus, carry out voltage compensation afterwards, calculates the magnitude of voltage that chip under test exports.The process eliminate because loose contact causes the harmful effect that causes of contact resistance difference, can measuring voltage exactly, improve the precision of voltage measurement.
Accompanying drawing explanation
Fig. 1 is the circuit diagram that the present invention implements.
Fig. 2 be the present invention another plant the circuit diagram of embodiment.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Be the power pins of chip under test with reference to figure 1 and Fig. 2, D, F is the ground pin of testing apparatus, and E is the reference voltage output pin of chip under test, and I is the common input and output pin of chip under test; A is the power pins of testing apparatus supply chip under test, and C is the ground pin of testing apparatus, and B is the pin of test thermometrically voltage, and H is the pin of the Geied current excitation of testing apparatus.
R0 be testing apparatus and chip under test ground contact good time resistance, R0X be testing apparatus and chip under test ground contact bad time increase resistance.
R1 be testing apparatus and chip under test internal reference voltage linear contact lay good time resistance, R1X be testing apparatus and the loose contact of chip under test reference voltage line time increase resistance.
R2 is the resistance of testing apparatus when contacting good with chip under test power lead, R2X be testing apparatus and the loose contact of chip under test power lead time increase resistance.
R3 is the resistance of testing apparatus when contacting good with chip under test I/O port, R3X be testing apparatus and the loose contact of chip under test I/O port time increase resistance.
Because the impedance at BE two ends is very large, so electric current can be ignored.
For (A) of Fig. 1, testing apparatus A port holds power supply to chip under test D, and I1 is the working current (can be obtained by testing apparatus measurement) of chip; To (A) of Fig. 2, the input of testing apparatus H end input high resistant, then HI does not walk electric current.
The reference voltage of first time testing apparatus measurement chip under test is VBC, and the reference voltage of the actual output of chip under test is VEF, owing to there is contact resistance between CF ground wire, can obtain following formula:
VBC＝VEF+I1*(R0+R0X) ……(1)
Second time is when testing, and concerning (B) of Fig. 1, testing apparatus need at the power supply of A end, the simultaneously extra drive current increasing I2, then the electric current of AD is I1+I2; Concerning (B) of Fig. 2, testing apparatus need to be held by the I of chip under test at H end and be poured into electric current I 2 to chip under test, then the electric current of CF is I1+I2, the reference voltage that testing apparatus measures chip under test is VBC2, and the reference voltage of the actual output of chip under test is VEF, can following formula be obtained:
VBC2＝VEF+(I1+I2)*(R0+R0X) ……(2)
By formula (1), (2) can obtain
(R0+R0X)＝(VBC2-VBC)/I2 ……(3)
VEF＝VBC-I1*(VBC2-VBC)/I2 ……(4)
By the result of twice test, then formula (4) just accurately can draw the reference voltage level that chip exports, and I1* (VBC2-VBC)/I2 is that contact resistance compensates the magnitude of voltage of returning.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (2)
1. a compensable voltage measurement method, it is characterized in that the method can be measured by the current value that twice measurement is superimposed upon ground wire and obtain twice measuring voltage, testing apparatus is obtainable twice voltage tester value also, obtain the contact resistance of ground wire thus, calculate the magnitude of voltage that chip under test exports afterwards.
2. compensable voltage measurement method as claimed in claim 1, it is characterized in that first time testing apparatus to measure the reference voltage of chip under test be VBC, and the reference voltage of the actual output of chip under test is VEF, owing to there is contact resistance between the ground pin of testing apparatus and the ground pin CF ground wire of testing apparatus, can following formula be obtained:
VBC＝VEF+I1*(R0+R0X) …… (1)
When second time is tested, testing apparatus need supply the power pins A end power supply of chip under test in testing apparatus, the extra drive current increasing the common input and output pin I2 of chip under test simultaneously, then the electric current of the testing apparatus supply power pins of chip under test and the power pins AD of chip under test is I1+I2;
Simultaneously, testing apparatus need be held to be held by the common input and output pin I of the chip under test of chip under test at the pin H of the Geied current excitation of testing apparatus and be poured into electric current I 2 to chip under test, then the electric current of the ground pin of testing apparatus and the ground pin CF of testing apparatus is I1+I2, the reference voltage that testing apparatus measures chip under test is VBC2, and the reference voltage of the actual output of chip under test is VEF, can following formula be obtained:
VBC2＝VEF+(I1+I2)*(R0+R0X) …… (2)
By formula (1), (2) can obtain
(R0+R0X)＝(VBC2-VBC)/I2 …… (3)
VEF＝VBC-I1*(VBC2-VBC)/I2 …… (4)
By the result of twice test, then formula (4) just accurately can draw the reference voltage level that chip exports, and wherein I1* (VBC2-VBC)/I2 is that contact resistance compensates the magnitude of voltage of returning.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108333411A (en) * | 2018-01-12 | 2018-07-27 | 上海华虹宏力半导体制造有限公司 | A kind of circuit and method for reducing analog voltage and measuring error |
| CN110265081A (en) * | 2019-06-26 | 2019-09-20 | 建荣半导体（深圳）有限公司 | Method, apparatus, cd-rom recorder and the storage medium of calibration chip voltage |
| CN113514758A (en) * | 2021-09-15 | 2021-10-19 | 绅克半导体科技(苏州)有限公司 | Chip testing method, tester and storage medium |
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| CN1291724A (en) * | 1999-10-07 | 2001-04-18 | 广州擎天实业有限公司电工分公司 | Automatic sampling correction method for voltage of battery |
| CN1609621A (en) * | 2004-11-19 | 2005-04-27 | 天津市纳百山科贸发展有限公司 | Double-parameter measuring instrument |
| CN101713794A (en) * | 2009-10-23 | 2010-05-26 | 广州蓝奇电子实业有限公司 | Method for detecting poor contact of battery voltage testing terminals |
| US20120139495A1 (en) * | 2010-12-06 | 2012-06-07 | Coda Automative, Inc. | Electrochemical cell balancing circuits and methods |
| CN104238619A (en) * | 2014-09-26 | 2014-12-24 | 深圳市芯海科技有限公司 | Temperature compensation circuit for reference voltage |
| CN104483537A (en) * | 2014-11-12 | 2015-04-01 | 深圳市芯海科技有限公司 | Low-voltage detection circuit with temperature compensation function |
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2015
- 2015-06-04 CN CN201510304278.2A patent/CN105021865B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1291724A (en) * | 1999-10-07 | 2001-04-18 | 广州擎天实业有限公司电工分公司 | Automatic sampling correction method for voltage of battery |
| CN1609621A (en) * | 2004-11-19 | 2005-04-27 | 天津市纳百山科贸发展有限公司 | Double-parameter measuring instrument |
| CN101713794A (en) * | 2009-10-23 | 2010-05-26 | 广州蓝奇电子实业有限公司 | Method for detecting poor contact of battery voltage testing terminals |
| US20120139495A1 (en) * | 2010-12-06 | 2012-06-07 | Coda Automative, Inc. | Electrochemical cell balancing circuits and methods |
| CN104238619A (en) * | 2014-09-26 | 2014-12-24 | 深圳市芯海科技有限公司 | Temperature compensation circuit for reference voltage |
| CN104483537A (en) * | 2014-11-12 | 2015-04-01 | 深圳市芯海科技有限公司 | Low-voltage detection circuit with temperature compensation function |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108333411A (en) * | 2018-01-12 | 2018-07-27 | 上海华虹宏力半导体制造有限公司 | A kind of circuit and method for reducing analog voltage and measuring error |
| CN110265081A (en) * | 2019-06-26 | 2019-09-20 | 建荣半导体（深圳）有限公司 | Method, apparatus, cd-rom recorder and the storage medium of calibration chip voltage |
| CN110265081B (en) * | 2019-06-26 | 2021-04-23 | 建荣半导体（深圳）有限公司 | Method and device for calibrating chip voltage, burner and storage medium |
| CN113514758A (en) * | 2021-09-15 | 2021-10-19 | 绅克半导体科技(苏州)有限公司 | Chip testing method, tester and storage medium |
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Address after: 518067 Nanshan District, Shenzhen, Nanhai Avenue, garden city, No. 1079, building A, block, floor 9 Patentee after: Chipsea Technology (Shenzhen) Co., Ltd. Address before: 518067 Nanshan District, Shenzhen, Nanhai Avenue, garden city, No. 1079, building A, block, floor 9 Patentee before: Xinhai Science and Technology Co., Ltd., Shenzhen City |
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