CN104992936A - Wafer level chip packaging structure - Google Patents
Wafer level chip packaging structure Download PDFInfo
- Publication number
- CN104992936A CN104992936A CN201510255996.5A CN201510255996A CN104992936A CN 104992936 A CN104992936 A CN 104992936A CN 201510255996 A CN201510255996 A CN 201510255996A CN 104992936 A CN104992936 A CN 104992936A
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- CN
- China
- Prior art keywords
- layer
- barrier layer
- plastic packaging
- wafer stage
- encapsulating structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a wafer level chip packaging structure. The wafer level chip packaging structure a metal protruding point. The metal protruding point is provided with a barrier layer. The barrier layer is provided with a welded ball. The periphery of a copper column is provided with a plastic packaging material. The barrier layer is arranged outside a plastic packaging layer. The barrier layer is arranged in a protruding manner relative to the upper surface of the plastic packaging layer. In the wafer level chip packaging structure, the barrier layer is additionally arranged, unfavorable influences of intermetallic compounds can be effectively prevented, and the electric performance and the mechanical property of the product are obviously improved.
Description
Technical field
The present invention relates to a kind of semiconductor packaging, be specifically related to a kind of wafer stage chip encapsulating structure.
Background technology
Current use electro-coppering post, grinds shaping after plastic packaging, and uses copper post to carry out planting ball as basalis.This structure has superiority in big current.But in the big current course of work, copper directly contacts with tin ball material, the copper Sn intermetallic compound of formation has adverse influence for follow-up reliability, electrical property and mechanical performance.
Summary of the invention
Provide hereinafter about brief overview of the present invention, to provide about the basic comprehension in some of the present invention.Should be appreciated that this general introduction is not summarize about exhaustive of the present invention.It is not that intention determines key of the present invention or pith, and nor is it intended to limit the scope of the present invention.Its object is only provide some concept in simplified form, in this, as the preorder in greater detail discussed after a while.
The object of the embodiment of the present invention is the defect for above-mentioned prior art, provides a kind of adverse effect that effectively can stop intermetallic compound, improves the wafer stage chip encapsulating structure of product electrical property and mechanical performance.
To achieve these goals, the technical scheme that the present invention takes is:
A kind of wafer stage chip encapsulating structure, comprise metal salient point, described metal salient point is provided with barrier layer, described barrier layer is provided with soldered ball, described the outer of copper post is arranged with plastic packaging material, described barrier layer is positioned at beyond described plastic packaging layer, and described barrier layer is arranged relative to the described upper surface projection stating plastic packaging layer.
Compared with prior art, the invention has the beneficial effects as follows:
The present invention, in wafer stage chip encapsulating structure (Wafer Level Chip Scale Packaging, WLCSP), increases one deck barrier layer, effectively can stop the adverse effect of intermetallic compound.The electrical property of product and mechanical performance are significantly improved.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The structural representation of the wafer stage chip encapsulating structure that Fig. 1 provides for the embodiment of the present invention.
Reference numeral:
1-metal salient point; 2-barrier layer; 3-soldered ball; 4-plastic packaging layer; 5-silicon bearing bed; 6-aluminium lamination; 7-passivation layer; 8-is wiring layer again.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.The element described in an accompanying drawing of the present invention or a kind of execution mode and feature can combine with the element shown in one or more other accompanying drawing or execution mode and feature.It should be noted that for purposes of clarity, accompanying drawing and eliminate expression and the description of unrelated to the invention, parts known to persons of ordinary skill in the art and process in illustrating.Based on the embodiment in the present invention, those of ordinary skill in the art, not paying the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
See Fig. 1, a kind of wafer stage chip encapsulating structure, comprises metal salient point 1, metal salient point 1 is provided with barrier layer 2, and barrier layer 2 is provided with soldered ball 3, and the outer of metal salient point 1 is arranged with plastic packaging layer 4, barrier layer 2 is positioned at beyond plastic packaging layer 4, and barrier layer 2 is arranged relative to the upper surface projection of plastic packaging layer 4.
The adverse effect of intermetallic compound effectively can be stoped by arranging barrier layer.
The present embodiment is on the basis of above-described embodiment, and metal salient point 1 is copper post, and soldered ball 3 is tin ball.Preferably, barrier layer is nickel or nickel alloy.
The existence on barrier layer, prevents generation and the growth of the intermetallic compound of copper and tin, is significantly improved for the electrical property of product and mechanical performance.
Preferably, the surrounding on barrier layer 2 is positioned at after stretching out and is formed on plastic packaging layer 4.
The present embodiment is on the basis of above-described embodiment, also comprise silicon bearing bed 5, silicon bearing bed 5 is provided with groove, aluminium lamination 6 is provided with in described groove, silicon bearing bed 5 is provided with passivation layer 7, passivation layer 7 is provided with opening on aluminium lamination 6, aluminium lamination 6 below passivation layer 7 and opening optionally forms wiring layer 8 again, wiring layer 8 is made to cover described opening again, wiring layer again 8 upper surface beyond described opening arranges metal salient point 1, and the periphery of metal salient point 1, again wiring layer 8 and passivation layer 7 arrange plastic packaging layer 4.
The upper surface of the plastic packaging layer that the present invention is arranged is concordant with the upper surface of metal salient point, and the barrier layer be arranged on metal salient point protrudes from the upper surface of described plastic packaging layer.Metal salient point selects copper post, and barrier layer is nickel or nickel alloy, and tin ball selected by soldered ball, due to the existence on barrier layer, prevents generation and the growth of the intermetallic compound of copper and tin, is significantly improved for the electrical property of product and mechanical performance.
Optionally, passivation layer 7 cover part aluminium lamination.
Optionally, the material of described passivation layer is dielectric material or their mixtures such as silica, silicon nitride, silicon oxynitride, polyimides.
Preferably, plastic packaging layer 4 is polyimide covercoat.The i.e. material selection polyimides of plastic packaging.
Last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to previous embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (8)
1. a wafer stage chip encapsulating structure, comprise metal salient point, it is characterized in that, described metal salient point is provided with barrier layer, described barrier layer is provided with soldered ball, the outer of described metal salient point is arranged with plastic packaging layer, and described barrier layer is positioned at beyond described plastic packaging layer, and described barrier layer is arranged relative to the described upper surface projection stating plastic packaging layer.
2. wafer stage chip encapsulating structure according to claim 1, is characterized in that, described metal salient point is copper post, and described soldered ball is tin ball.
3. wafer stage chip encapsulating structure according to claim 2, is characterized in that, described barrier layer is nickel or nickel alloy.
4. the wafer stage chip encapsulating structure according to any one of claim 1-3, is characterized in that, is positioned on described plastic packaging layer after the surrounding on described barrier layer stretches out.
5. wafer stage chip encapsulating structure according to claim 4, it is characterized in that, also comprise silicon bearing bed, described silicon bearing bed is provided with groove, aluminium lamination is provided with in described groove, described silicon bearing bed is provided with passivation layer, described passivation layer is provided with opening on aluminium lamination, aluminium lamination below described passivation layer and opening optionally forms wiring layer again, described in making, wiring layer covers described opening again, the upper surface of wiring layer again beyond described opening arranges metal salient point, in the periphery of described metal salient point, described wiring layer again and described passivation layer arrange plastic packaging layer.
6. wafer stage chip encapsulating structure according to claim 5, is characterized in that, described passivation layer cover part aluminium lamination.
7. wafer stage chip encapsulating structure according to claim 6, is characterized in that, the material of described passivation layer is silica, silicon nitride, silicon oxynitride, polyimides or their mixture.
8. wafer stage chip encapsulating structure according to claim 7, is characterized in that, described plastic packaging layer is polyimide covercoat.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510255996.5A CN104992936A (en) | 2015-05-19 | 2015-05-19 | Wafer level chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510255996.5A CN104992936A (en) | 2015-05-19 | 2015-05-19 | Wafer level chip packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104992936A true CN104992936A (en) | 2015-10-21 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510255996.5A Pending CN104992936A (en) | 2015-05-19 | 2015-05-19 | Wafer level chip packaging structure |
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| CN (1) | CN104992936A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010026954A1 (en) * | 2000-03-30 | 2001-10-04 | Yukihiro Takao | Semiconductor device and manufacturing method thereof |
| US20040021234A1 (en) * | 2002-07-15 | 2004-02-05 | Kazutaka Shibata | Semiconductor device and manufacturing method thereof |
| CN1697148A (en) * | 2004-05-12 | 2005-11-16 | 富士通株式会社 | Semiconductor device and method of manufacturing the semiconductor device |
| CN102194783A (en) * | 2010-03-17 | 2011-09-21 | 玛克西姆综合产品公司 | Enhanced WLP for superior temperature cycling, drop test and high current applications |
| CN102244061A (en) * | 2011-07-18 | 2011-11-16 | 江阴长电先进封装有限公司 | Low-k chip package structure |
| CN102496606A (en) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | High-reliability wafer level cylindrical bump packaging structure |
| CN202473905U (en) * | 2011-12-19 | 2012-10-03 | 南通富士通微电子股份有限公司 | Wafer level columnar bump packaging structure |
-
2015
- 2015-05-19 CN CN201510255996.5A patent/CN104992936A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010026954A1 (en) * | 2000-03-30 | 2001-10-04 | Yukihiro Takao | Semiconductor device and manufacturing method thereof |
| US20040021234A1 (en) * | 2002-07-15 | 2004-02-05 | Kazutaka Shibata | Semiconductor device and manufacturing method thereof |
| CN1697148A (en) * | 2004-05-12 | 2005-11-16 | 富士通株式会社 | Semiconductor device and method of manufacturing the semiconductor device |
| CN102194783A (en) * | 2010-03-17 | 2011-09-21 | 玛克西姆综合产品公司 | Enhanced WLP for superior temperature cycling, drop test and high current applications |
| CN102244061A (en) * | 2011-07-18 | 2011-11-16 | 江阴长电先进封装有限公司 | Low-k chip package structure |
| CN102496606A (en) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | High-reliability wafer level cylindrical bump packaging structure |
| CN202473905U (en) * | 2011-12-19 | 2012-10-03 | 南通富士通微电子股份有限公司 | Wafer level columnar bump packaging structure |
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| C06 | Publication | ||
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| CB02 | Change of applicant information |
Address after: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant before: Fujitsu Microelectronics Co., Ltd., Nantong |
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| COR | Change of bibliographic data | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20151021 |
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| RJ01 | Rejection of invention patent application after publication |