CN104980139A

CN104980139A - Circuit structure for ensuring normal switching among working states of submodules in multi-module system

Info

Publication number: CN104980139A
Application number: CN201510398317.XA
Authority: CN
Inventors: 陆网妹
Original assignee: Individual
Current assignee: Individual
Priority date: 2015-06-30
Filing date: 2015-06-30
Publication date: 2015-10-14

Abstract

The invention provides a circuit structure for ensuring the normal switching among the working states of submodules in a multi-module system. By adopting the circuit structure, the normal switching among the working states of submodules can be ensured. According to the technical scheme of the invention, the circuit structure comprises a power supply module, a power supply management module and a group of the submodules. The power supply module is used for supplying a working power supply to each loop. The power supply management module matches with the power supply module, and each submodule is composed of a field-effect tube switching circuit and a load. A residual voltage consumption circuit is additionally arranged inside a circuit structure of an arbitrary submodule. A control end of the power supply management module is connected with a controlled end of the residual voltage consumption circuit, and an output end of the field-effect tube switching circuit is connected with the residual voltage consumption circuit to be grounded. By adopting the circuit structure, the normal electrification of the submodules is ensured through accessing the matched residual voltage consumption circuit to the output end of the field-effect tube switching circuit and reducing the voltage at the input ends of the submodules to be within a permitted range.

Description

The circuit structure that submodule operating state normally switches is ensured in multi-module system

Technical field

The application relates to a kind of circuit structure that submodule operating state normally switches that ensures in multi-module system, belongs to electronic technology field, particularly a kind of by residual voltage consumption circuit, realizes the circuit structure that submodule normally powers on.

Background technology

Along with the fast development of electronic technology, electronic equipment is towards the future development of Highgrade integration, function modoularization, and along with the introducing of environmental protection, energy-saving and cost-reducing demand, and the demand of fault diagnosis functions etc., system often needs the working power of closing a module or several module in certain occasion, to reach the object of energy-saving and cost-reducing and failure diagnosis, restart the power supply of necessary submodule in due course to realize the function needed for user.As shown in Figure 1, in prior art, power module gives other each module for power supply, and power management module is also responsible for the power management of each submodule except completing specific function.When the power supply of submodule is closed, we expect that the voltage of P point is 0V, but due to module each in multi-CPU system except working power also have a lot of signal circuit be connected, the isolation that all will realize these signals needs to increase a large amount of devices, not only increase the complexity of system, and too increase cost.Therefore in actual design, these signal circuits cannot realize isolating one by one, the submodule of non-powered-down pours into weak current by these holding wires, P point voltage is caused to be greater than 0.7V, therefore when the submodule of closing re-powers, its working power is not power on from desirable 0V, cannot normally work after causing submodule to power on.For this problem, prior art does not well solve, and brings inconvenience to the work of this area.

Summary of the invention

The application will solve the technical problem ensureing that submodule operating state normally switches, devise and ensure the circuit structure that submodule operating state normally switches in multi-module system, access supporting residual voltage by the output of scene effect pipe switching circuit and consume circuit, the input terminal voltage of submodule is down to allowed band, ensures that submodule normally powers on.

The application is the technical scheme realizing goal of the invention employing, the circuit structure that submodule operating state normally switches is ensured in multi-module system, above circuit structure comprises for each loop provides the power module of working power, supporting power management module, and one group of submodule be made up of FET switch circuit and load, have additional residual voltage in the circuit structure of above-mentioned norator module and consume circuit, the control end of power management module connects the controlled end that residual voltage consumes circuit, the output of FET switch circuit connects residual voltage consumption circuit and enters ground.

The beneficial effect of the application is: access supporting residual voltage by the output of scene effect pipe switching circuit and consume circuit, the input terminal voltage of submodule is down to allowed band, ensures that submodule normally powers on.

Below in conjunction with accompanying drawing, the application is described in detail.

Accompanying drawing explanation

Fig. 1 is the structure principle chart of multi-module system in prior art.

Fig. 2 is the structure principle chart of the application.

Fig. 3 is a specific embodiment of the application.

Embodiment

Referring to Fig. 2, the circuit structure that submodule operating state normally switches is ensured in multi-module system, above circuit structure comprises for each loop provides the power module 1 of working power, supporting power management module 2, and one group of submodule 3 be made up of FET switch circuit 3-1 and load 3-2, have additional residual voltage in the circuit structure of above-mentioned norator module 3 and consume circuit 3-3, the control end of power management module 2 connects the controlled end that residual voltage consumes circuit 3-3, the output of FET switch circuit 3-1 connects residual voltage consumption circuit 3-3 and enters ground.

Above-mentioned residual voltage consumes circuit 3-3 and is made up of current limliting chip U1, the controlled end of current limliting chip U1 connects the control end of power management module 2, the input of current limliting chip U1 connects the output of FET switch circuit 3-1, the ground pin ground connection of current limliting chip U1.

Above-mentioned current limliting chip U1 inside is provided with logic sum gate circuit, the B input pin ground connection of logic sum gate circuit, A input pin connects the control end of power management module 2 as the controlled end of current limliting chip U1, and Y pin is connected the output of FET switch circuit 3-1 with the logic output terminal of logic gates as the input of current limliting chip U1.

The model of above-mentioned current limliting chip U1 is NC7SZ32P5X.

A specific embodiment of the application, referring to Fig. 3, the current limliting chip U1 that residual voltage consumption circuit 3-3 is provided with logic sum gate circuit by inside forms, pin A, B of current limliting chip U1 are two inputs of logic sum gate circuit, wherein input B ground connection, another input A is as the control end of the controlled end connection power management module 2 of current limliting chip U1, and the input of current limliting chip U1 connects the output of FET switch circuit 3-1.Power management module 2 controls FET switch circuit 3-1 simultaneously and residual voltage consumes circuit 3-3, under normal operating conditions, power management module 2 exports high level, fet switch conducting, the pin A of current limliting chip U1 is high level, logic sum gate circuit exports as high level, and submodule 3 normally works; During power management module 2 output low level, fet switch is closed, and supply voltage starts to decline, and logic sum gate circuit exports as low level and starts Absorption Current (being usually no more than 90mA), final supply voltage drops to close to 0V, ensure that the normal closedown of submodule 3; When power management module 2 exports high level again, fet switch is opened, supply voltage rises from 0V, logic sum gate circuit exports as high level and pours into electric current (being usually no more than 90mA) to load 3-2 simultaneously, final supply voltage rises to normal working voltage, and submodule 3 completes normal startup; So far complete the lower electricity of submodule 3 and re-power process, submodule is able to start smoothly and normal work.

Claims

1. in multi-module system, ensure the circuit structure that submodule operating state normally switches, above circuit structure comprises for each loop provides the power module (1) of working power, supporting power management module (2), and one group of submodule (3) be made up of FET switch circuit (3-1) and load (3-2), it is characterized in that: have additional residual voltage in the circuit structure of described norator module (3) and consume circuit (3-3), the control end of power management module (2) connects the controlled end that residual voltage consumes circuit (3-3), the output of FET switch circuit (3-1) connects residual voltage consumption circuit (3-3) and enters ground.

2. according to claim 1ly in multi-module system, ensure the circuit structure that submodule operating state normally switches, it is characterized in that: described residual voltage consumes circuit (3-3) and is made up of current limliting chip (U1), the controlled end of current limliting chip (U1) connects the control end of power management module (2), and the input of current limliting chip (U1) connects the output of FET switch circuit (3-1).

3. according to claim 2ly in multi-module system, ensure the circuit structure that submodule operating state normally switches, it is characterized in that: described current limliting chip (U1) inside is provided with logic sum gate circuit, the B input pin ground connection of logic sum gate circuit, A input pin is connected to the control end of power management module (2), and Y pin is connected to the output of FET switch circuit (3-1).