CN104979345B - High-voltage CMOS integrated morphology and its manufacture method - Google Patents

High-voltage CMOS integrated morphology and its manufacture method Download PDF

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CN104979345B
CN104979345B CN201410141299.2A CN201410141299A CN104979345B CN 104979345 B CN104979345 B CN 104979345B CN 201410141299 A CN201410141299 A CN 201410141299A CN 104979345 B CN104979345 B CN 104979345B
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high pressure
traps
pressure nmos
doped regions
isolated
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CN104979345A (en
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潘光燃
文燕
王焜
石金成
高振杰
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Shenzhen Founder Microelectronics Co Ltd
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Peking University Founder Group Co Ltd
Shenzhen Founder Microelectronics Co Ltd
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Abstract

The present invention provides a kind of high-voltage CMOS integrated morphology and its manufacture method.The high-voltage CMOS integrated morphology includes：P type substrate, high voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area；The high voltage PMOS, the non-isolation type high pressure NMOS, the isolated form high pressure NMOS and the isolated area are separately positioned in the P type substrate；The isolated area is arranged between the non-isolation type high pressure NMOS and the isolated form high pressure NMOS.The present invention is by the way that high voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area are set directly in P type substrate, it is not necessary to epitaxial layer and buried layer, reduces making and process costs.

Description

High-voltage CMOS integrated morphology and its manufacture method
Technical field
The present invention relates to semiconductor technology, more particularly to a kind of high pressure complementary metal oxide semiconductor （Complementary Metal Oxide Semiconductor, abbreviation CMOS）Integrated morphology and its manufacture method.
Background technology
Fig. 1 is the structural representation of high-voltage CMOS integrated morphology in the prior art.As shown in figure 1, the high-voltage CMOS integrates The components such as high voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS, the integrated knot of the high-voltage CMOS are integrated with structure The making of structure mainly using N-type buried layer is made in P type substrate, then makes epitaxial layer, then in substrate and epitaxial layer The components such as high voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS are made among superposition Rotating fields, it is implemented Mode is：First high pressure NMOS is non-isolation type high pressure NMOS, the second high pressure NMOS is isolated form high pressure NMOS.Wherein, it is non-every The p-well of release high pressure NMOS is directly produced among the superposition Rotating fields of P type substrate and epitaxial layer, the P of isolated form high pressure NMOS It must be kept apart between trap and P type substrate using N-type buried layer, high voltage PMOS bears high electricity using the 3rd p-well as drain terminal The buffering area of work is pressed, as shown in figure 1, the effect of N-type buried layer is the 3rd p-well and P type substrate high voltage PMOS drain terminal Keep apart, short circuit, and the second p-well and P type substrate isolated form high pressure NMOS otherwise occur between drain terminal and P type substrate Keep apart.
But due to the integrated and isolated area of high pressure NMOS and high voltage PMOS all being made in the epitaxial layer, and extension The problem of making of layer needs expensive semi-conducting material, therefore the cost of manufacture that result in high-voltage CMOS integrated morphology is high.
The content of the invention
The present invention provides a kind of high-voltage CMOS integrated morphology and its manufacture method, by the way that high voltage PMOS, non-isolation type is high Pressure NMOS, isolated form high pressure NMOS and isolated area are set directly in P type substrate, it is not necessary to epitaxial layer and buried layer, are reduced Making and process costs.
First aspect present invention provides a kind of high-voltage CMOS integrated morphology, including：P type substrate, high voltage PMOS, non-isolation type High pressure NMOS, isolated form high pressure NMOS and isolated area；
The high voltage PMOS, the non-isolation type high pressure NMOS, the isolated form high pressure NMOS and the isolated area are distinguished It is arranged in the P type substrate；
The isolated area is arranged between the non-isolation type high pressure NMOS and the isolated form high pressure NMOS.
Second aspect of the present invention provides a kind of manufacture method of high-voltage CMOS integrated morphology, including：
Make P type substrate；
High voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area are formed in the substrate P；
Wherein, the isolated area is arranged between the non-isolation type high pressure NMOS and the isolated form high pressure NMOS.
High-voltage CMOS integrated morphology and its manufacture method of the present invention, by by high voltage PMOS, non-isolation type high pressure NMOS, every Release high pressure NMOS and isolated area are set directly in P type substrate, compared to high voltage PMOS in the prior art, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area are arranged on epitaxial layer, and the present invention is due to need not be high by high voltage PMOS, non-isolation type Pressure NMOS, isolated form high pressure NMOS and isolated area are arranged in epitaxial layer and buried layer, therefore reduce making and process costs.
Brief description of the drawings
Fig. 1 is the structural representation of high-voltage CMOS integrated morphology in the prior art；
Fig. 2 is the structural representation of high-voltage CMOS integrated morphology embodiment one of the present invention；
Fig. 3 is the structural representation of high-voltage CMOS integrated morphology embodiment two of the present invention；
Fig. 4 is the flow chart of the preparation method embodiment one of high-voltage CMOS integrated morphology of the present invention；
Fig. 5 a to Fig. 5 c are respectively the flow chart of the preparation method embodiment two of high-voltage CMOS integrated morphology of the present invention.
Embodiment
Fig. 2 is the structural representation of high-voltage CMOS integrated morphology embodiment one of the present invention, as shown in Fig. 2 the high-voltage CMOS Integrated morphology includes：P type substrate, high voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area.The height Pressure PMOS, the non-isolation type high pressure NMOS, the isolated form high pressure NMOS are separately positioned on the p-type with the isolated area and served as a contrast In bottom, and isolated area is arranged between the non-isolation type high pressure NMOS and isolated form high pressure NMOS.
In the present embodiment, the CMOS is n channel metal oxide semiconductor field effect transistor（Metal Oxide Semiconductor Field Effect Transistor, abbreviation MOS）With P-channel MOS（Abbreviation PMOS）According to certain side The combining structure that formula is electrically connected with.High-voltage CMOS integrated morphology, typically at least include the high-pressure MOS component of three kinds of structures：It is non-every Release high pressure NMOS, isolated form high pressure NMOS, high voltage PMOS.The N being lightly doped generally is respectively adopted in high pressure NMOS and high voltage PMOS Type doped region and the p-type doped region being lightly doped bear the buffering area of high voltage operation as its drain terminal, in the integrated electricity of high-voltage CMOS In the chip of road, also all integration section low voltage CMOS circuit（The circuit that low pressure NMOS and low pressure PMOS is formed）.
The high-voltage CMOS integrated morphology that the present embodiment provides, by by high voltage PMOS, non-isolation type high pressure NMOS, isolated form High pressure NMOS and isolated area are set directly in P type substrate, compared to high voltage PMOS in the prior art, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area are arranged on epitaxial layer, and the present invention is due to need not be high by high voltage PMOS, non-isolation type Pressure NMOS, isolated form high pressure NMOS and isolated area are arranged in epitaxial layer and buried layer, therefore reduce making and process costs.
Fig. 3 is the structural representation of high-voltage CMOS integrated morphology embodiment two of the present invention, on the basis of embodiment illustrated in fig. 2 On, as shown in figure 3, the high-voltage CMOS integrated morphology of the present embodiment also includes：
The high voltage PMOS includes：Source P+ doped regions, P drift area, drain terminal P+ doped regions and the first N traps, source P+ mix Miscellaneous area, P drift area and drain terminal P+ doped regions are arranged in the first N traps, and P drift area is located at source P+ doped regions and drain terminal Between P+ doped regions.Preferably, the depth of the first N traps is 2~10 times of depth of P drift area.
In the present embodiment, P drift area is the buffering area that high voltage PMOS drain terminal bears high voltage operation.
The isolated form high pressure NMOS includes the 2nd N traps, the second p-well, the 3rd N traps, source N+ doped regions and drain terminal N+ doping Area.Wherein, the 2nd N traps and the second p-well are arranged in the 3rd N traps, and source N+ doped regions are arranged in the second p-well, and drain terminal N+ mixes Miscellaneous area is arranged in the 2nd N traps.
Preferably, the depth of the 3rd N traps is 1.5~3 times of depth of the second p-well.
In the present embodiment, the 2nd N traps bear the buffering area of high voltage operation for the drain terminal of isolated form high pressure NMOS.
In addition, non-isolation type high pressure NMOS and identical in the prior art, including the 4th p-well and the 4th N traps, source N+ doping Area and drain terminal N+ doped regions, the 4th N traps bear the buffering area of high voltage operation for the drain terminal of non-isolation type high pressure NMOS.
The high-voltage CMOS integrated morphology that the present embodiment provides, high voltage PMOS is by source P+ doped regions, P drift area, drain terminal P + doped region and the first N traps composition, source P+ doped regions, P drift area and drain terminal P+ doped regions are arranged in the first N traps, and institute P drift area is stated between the source P+ doped regions and drain terminal P+ doped regions, isolated form high pressure NMOS is by the 2nd N traps, Two p-wells, the 3rd N traps, source N+ doped regions and drain terminal N+ doped regions composition, the 2nd N traps and the second p-well are arranged on the 3rd N In trap, the first N traps and the 3rd N traps are provided entirely in P type substrate, it is not necessary to epitaxial layer and buried layer, relative to existing skill Expensive epitaxial layer in art, reduce making and process costs.
Fig. 4 is the flow chart of the preparation method embodiment one of high-voltage CMOS integrated morphology of the present invention, as shown in figure 4, the system Include as method：
S401：Make P type substrate.
S402：High voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area are formed in substrate P.
In the present embodiment, the high-voltage CMOS integrated morphology can be to be integrated corresponding to above-mentioned Fig. 2 to embodiment illustrated in fig. 3 Structure.
In addition, isolated area is arranged between non-isolation type high pressure NMOS and isolated form high pressure NMOS, the isolated area can be by P Trap, and the P field doped region composition higher than the p-well doping concentration is set on the p-well top layer.For high voltage PMOS, non-isolation type The quantity of high pressure NMOS, isolated form high pressure NMOS and isolated area, it can set as requested, the present invention is not limited.
The preparation method for the high-voltage CMOS integrated morphology that the present embodiment provides, by by high voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area are set directly in P type substrate, it is not necessary to epitaxial layer and buried layer, reduce system Work and process costs.
Fig. 5 a to Fig. 5 c are respectively the flow chart of the preparation method embodiment two of high-voltage CMOS integrated morphology of the present invention, are being schemed On the basis of 4 illustrated embodiments, as shown in Figure 5 a, high voltage PMOS is formed in S402 in substrate P, specifically included：
S501, the first N traps are formed in substrate P.
S502, source P+ doped regions, P drift area and drain terminal P+ doped regions are formed in the first N traps；Wherein, p-type is floated Area is moved to be located between source P+ doped regions and drain terminal P+ doped regions.By way of forming P fields doped region, the high voltage PMOS is formed P drift area.
Preferably, as shown in Figure 5 b, isolated form high pressure NMOS is formed in S402 in substrate P, is specifically included：
S503, the 3rd N traps are made in P type substrate.
S504, the 2nd N traps and the second p-well are made in the 3rd N traps.
S505, drain terminal N+ doped regions are formed in the 2nd N traps, source N+ doped regions are formed in the second p-well.
Preferably, as shown in Figure 5 c, non-isolation type high pressure NMOS is formed in S402 in substrate P, is specifically included：
S506, the 4th p-well and the 4th N traps are made in P type substrate.
S507, drain terminal N+ doped regions are formed in the 4th N traps, source N+ doped regions are formed in the 4th p-well.
In the present embodiment, it is preferred that the depth in P drift area is 0.25~1.8 micron, and the depth of the first N traps is 2- 15 microns, the depth of the 3rd N traps is 4-15 microns, and the depth of the 2nd N traps and the second p-well is 2-8 microns.
Preferably, P type substrate is the p-type single crystalline substrate that resistivity is 5~300 ohm * centimetres.
Further, in the preparation method embodiment three of high-voltage CMOS integrated morphology, shown in above-mentioned Fig. 4, Fig. 5 a-5c Embodiment on the basis of, form field oxide in the subregion on the P type substrate surface, and do not covered by field oxide The P type substrate surface region of lid forms gate oxide, and polysilicon is formed in the subregion on gate oxide and field oxide surface Grid, finally it is fabricated to high-voltage CMOS integrated morphology.
The preparation method for the high-voltage CMOS integrated morphology that the present embodiment provides, it is to be served as a contrast in P that high voltage PMOS is formed in substrate P The first N traps are formed in bottom, source P+ doped regions, P drift area and drain terminal P+ doped regions, p-type drift are formed in the first N traps Move area to be located between source P+ doped regions and drain terminal P+ doped regions, it is in P type substrate to form isolated form high pressure NMOS in substrate P The 3rd N traps of middle making, make the 2nd N traps and the second p-well in the 3rd N traps, and drain terminal N+ doped regions are formed in the 2nd N traps, Source N+ doped regions are formed in second p-well.First N traps and the 3rd N traps are provided entirely in P type substrate, it is not necessary to epitaxial layer And buried layer, relative to epitaxial layer expensive in the prior art, reduce making and process costs.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than its limitations；To the greatest extent The present invention is described in detail with reference to foregoing embodiments for pipe, it will be understood by those within the art that：Its according to The technical scheme described in foregoing embodiments can so be modified, either which part or all technical characteristic are entered Row equivalent substitution；And these modifications or replacement, the essence of appropriate technical solution is departed from various embodiments of the present invention technology The scope of scheme.

Claims (6)

  1. A kind of 1. high-voltage CMOS integrated morphology, it is characterised in that including：P type substrate, high voltage PMOS, non-isolation type high pressure NMOS, Isolated form high pressure NMOS and isolated area；
    The high voltage PMOS, the non-isolation type high pressure NMOS, the isolated form high pressure NMOS are set respectively with the isolated area In the P type substrate；
    The isolated area is arranged between the non-isolation type high pressure NMOS and the isolated form high pressure NMOS；
    The P type substrate is the P type substrate not comprising epitaxial layer；
    Wherein, the high voltage PMOS includes source P+ doped regions, P drift area, drain terminal P+ doped regions and the first N traps；
    The source P+ doped regions, the P drift area and the drain terminal P+ doped regions are arranged in the first N traps, and institute P drift area is stated between the source P+ doped regions and the drain terminal P+ doped regions；
    The isolated form high pressure NMOS includes the 2nd N traps, the second p-well, the 3rd N traps, source N+ doped regions and drain terminal N+ doped regions；
    The 2nd N traps are arranged in the 3rd N traps with second p-well；
    The source N+ doped regions are arranged in second p-well, and the drain terminal N+ doped regions are arranged in the 2nd N traps.
  2. 2. high-voltage CMOS integrated morphology according to claim 1, it is characterised in that the depth of the first N traps is the P 2~10 times of the depth of type drift region.
  3. 3. high-voltage CMOS integrated morphology according to claim 1 or 2, it is characterised in that the depth of the 3rd N traps is institute State the depth of the second p-well 1.5~3 times.
  4. A kind of 4. manufacture method of high-voltage CMOS integrated morphology, it is characterised in that including：
    Make P type substrate；
    The P type substrate is the P type substrate not comprising epitaxial layer；
    High voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area are formed in the substrate P；
    Wherein, the isolated area is arranged between the non-isolation type high pressure NMOS and the isolated form high pressure NMOS；
    Wherein, the high voltage PMOS is formed in the substrate P, including：
    The first N traps are formed in the substrate P；
    Source P+ doped regions, P drift area and drain terminal P+ doped regions are formed in the first N traps；Wherein, the P drift Area is between the source P+ doped regions and the drain terminal P+ doped regions；
    Isolated form high pressure NMOS is formed in the substrate P, including：
    The 3rd N traps are made in the P type substrate；
    The 2nd N traps and the second p-well are made in the 3rd N traps；
    Drain terminal N+ doped regions are formed in the 2nd N traps, source N+ doped regions are formed in second p-well.
  5. 5. preparation method according to claim 4, it is characterised in that the depth of the first N traps is 2-15 microns；It is described The depth of 3rd N traps is 4-15 microns；The depth of the 2nd N traps and second p-well is 2-8 microns.
  6. 6. the preparation method according to claim 4 or 5, it is characterised in that the resistivity of the P type substrate is 5~300 Europe * centimetres of nurse.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102446955A (en) * 2010-10-06 2012-05-09 旺宏电子股份有限公司 High voltage MOS device and method for making the same
CN103280460A (en) * 2013-05-22 2013-09-04 矽力杰半导体技术(杭州)有限公司 High-voltage PMOS (p-channel metal oxide semiconductor) transistor with injection molded superimposed drift region and manufacturing method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060220179A1 (en) * 2005-04-01 2006-10-05 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming an improved isolation junction in high voltage LDMOS structures

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102446955A (en) * 2010-10-06 2012-05-09 旺宏电子股份有限公司 High voltage MOS device and method for making the same
CN103280460A (en) * 2013-05-22 2013-09-04 矽力杰半导体技术(杭州)有限公司 High-voltage PMOS (p-channel metal oxide semiconductor) transistor with injection molded superimposed drift region and manufacturing method thereof

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Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province

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