CN104979281A - Contact hole forming method - Google Patents
Contact hole forming method Download PDFInfo
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- CN104979281A CN104979281A CN201510271722.5A CN201510271722A CN104979281A CN 104979281 A CN104979281 A CN 104979281A CN 201510271722 A CN201510271722 A CN 201510271722A CN 104979281 A CN104979281 A CN 104979281A
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- contact hole
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- 238000000034 method Methods 0.000 title claims abstract description 80
- 239000010410 layer Substances 0.000 claims abstract description 112
- 239000011229 interlayer Substances 0.000 claims abstract description 35
- 230000004888 barrier function Effects 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims description 109
- 229920002120 photoresistant polymer Polymers 0.000 claims description 73
- 239000000758 substrate Substances 0.000 claims description 35
- 239000004065 semiconductor Substances 0.000 claims description 29
- 229910052799 carbon Inorganic materials 0.000 claims description 28
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 26
- 238000000059 patterning Methods 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 19
- 238000007493 shaping process Methods 0.000 claims description 19
- 239000006117 anti-reflective coating Substances 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 230000007547 defect Effects 0.000 claims description 10
- 239000003153 chemical reaction reagent Substances 0.000 claims description 9
- 229910052914 metal silicate Inorganic materials 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 6
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 6
- 238000007689 inspection Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 5
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 3
- JMANVNJQNLATNU-UHFFFAOYSA-N oxalonitrile Chemical compound N#CC#N JMANVNJQNLATNU-UHFFFAOYSA-N 0.000 claims description 3
- 229920000642 polymer Polymers 0.000 abstract description 25
- 239000002184 metal Substances 0.000 abstract description 19
- 229910052751 metal Inorganic materials 0.000 abstract description 18
- 230000000694 effects Effects 0.000 abstract description 4
- 230000010148 water-pollination Effects 0.000 abstract description 4
- 230000000087 stabilizing effect Effects 0.000 abstract 1
- 238000005406 washing Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 9
- 229910021332 silicide Inorganic materials 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 3
- 229910001092 metal group alloy Inorganic materials 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- -1 silicon nitrides Chemical class 0.000 description 3
- 229910005883 NiSi Inorganic materials 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910052693 Europium Inorganic materials 0.000 description 1
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910016285 MxNy Inorganic materials 0.000 description 1
- 229910052779 Neodymium Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 229910020177 SiOF Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- DZPJVKXUWVWEAD-UHFFFAOYSA-N [C].[N].[Si] Chemical compound [C].[N].[Si] DZPJVKXUWVWEAD-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000006701 autoxidation reaction Methods 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a contact hole forming method. An initial contact hole in an interlayer medium layer is used as a window; after an etched barrier layer at the bottom of the window is removed to form the contact hole and before the contact hole is washed by a wet process, a second degumming treatment process is additionally increased to change the surface hydrophily; when subsequent wet-process washing is carried out, high-molecular polymers remained in the contact hole can be completely removed, so that the high-molecular polymers are basically not remained in the contact hole, the subsequent contact hole metal filling effect is greatly improved, and the aim of improving and stabilizing the yield of products is achieved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of contact hole shaping method.
Background technology
Because the manufacture of integrated circuit develops to very lagre scale integrated circuit (VLSIC), the current densities of its inside is increasing, along with the continuous increase of number of elements contained in chip, in fact just decreases the free space of surperficial line.This way to solve the problem adopts multiple layer metal traverse design, and the multilayer utilizing multilayer dielectric layer and conductive layer mutually to superpose is connected, and this wherein just needs to make a large amount of contact holes.Such as, in existing MOS transistor technique, need to form contact hole in active area (source electrode and drain electrode) and grid (comprising polysilicon gate, metal gates etc.).
Technology node before 90nm, after the contact hole etching (Contact Etch) of CMOS product, capital proceeds to the board that removes photoresist (Asher) and carries out remove photoresist (Ash), then enters after wet-cleaned board removes photoresist and cleans (Wet Clean).The step of contact hole etching is also relatively simple, after sending there being the substrate on Si N barrier layer and interlayer dielectric layer on the surface into etching machine, generally only comprise photoresist spin coating (mainly bottom antireflective coating/dielectric anti-reflective coating coating, BARC/DARC step), main etching (Main Etchstep) and over etching (Over Etch step) these steps.
And constantly reducing along with critical size (CD), in order to the various parameters (such as shape, sidewall, top/bottom CD etc.) after ensureing contact hole etching, the structure in contact hole etching also constantly becomes complicated; After entering 65nm technology node, simple photoresist can not, as etching mask layer, need under photoresist, increase the hard mask of one deck (being generally APF or other carbon-containing hard mask materials); The metal silicide of contact hole and substrate contact also becomes metallic nickel (Ni) from metallic cobalt, and nickel-silicon compound (Ni-Silicide) is easily oxidized.In order to meet the demand that properties of product improve constantly, and in order to avoid Ni-Silicide oxidized in follow-up degumming process, in CIS product, remove photoresist (Ash Step) to be incorporated in contact hole etching processing procedure (usually, degumming process step completed before silicon nitride etch (SiN Remove), this technology completing degumming process in main etching cavity is called the contact hole technology that original position is removed photoresist (In-situ Ash), specific as follows:
In the etch chamber of etching apparatus, carry out contact hole etching, comprise Darc/Barc step, APF Hard MaskEtch Step, Main Etch Step, Over Etch step;
In the etch chamber of etching apparatus, carry out original position remove photoresist (In-situ Ash Step);
The silicon nitride (SiN Remove) bottom contact hole is removed in the etch chamber of etching apparatus;
Wet method (Wet) is cleaned, and in Wet board, remove particulate and other residuals of product surface;
Defect inspection (Defect Scan).
Therefore, in the contact hole etching technique of In-situ Ash, after contact hole etching terminates, directly can enter wet clean step.But, during defect inspection (Defect Scan) after wet cleaning, often can be tested with polymer residue (residue) (as shown in FIG. 1A and 1B) of random distribution.The quantity of polymer residue generally arrives hundreds of tens, serious meeting even 2000 more than 1000.Constituent analysis discovery is carried out to residue, residue composition mainly C, F, O, supposition should be the high molecular polymer (polymer) remained in contact hole etching process in contact hole through hole, these polymer can not remove very well and be attached on wafer (wafer) surface in follow-up wet clean process, form described random distribution polymer residue (residue).Find through done site by site defect scan tracing, residue after contact hole etching still can see vestige (please refer to Fig. 1 C) after contact metal deposition (CTG-DEP), chemical-mechanical planarization surface after metal filled occurs that metal plug is filled abnormal (please refer to Fig. 1 D), finally causes component failure.
Obviously, the existence of polymer residue can cause the yield (Yield) of final products to decline.Analysis large-tonnage product finds, remain at about 2000 particle/polymers and deposit in case, yield can decline about 10%.Therefore specify once the residue detecting discovery product exists quantity more than 700 at present, just judge that product has exception, process engineer is needed to make investigation, generally etching machine bench (chamber) to be taken time out to, check that residue has the front and back of defective product to criticize, if situation is serious, then need the cleaning maintenance work (maintains) at once carrying out board/cavity, confirm that residue could continue to produce after out of question.
Therefore, needing a kind of contact hole shaping method, there is quantity in that can reduce the polymer residue after degumming process, to improve the yield of product.
Summary of the invention
The object of the present invention is to provide a kind of contact hole shaping method, there is quantity in that can reduce the polymer residue after degumming process, to improve the yield of product.
For solving the problem, the present invention proposes a kind of contact hole shaping method, comprising:
The Semiconductor substrate of one contact hole etching waiting is sent into the etch chamber of etching apparatus, the surface of described Semiconductor substrate is formed with successively the photoresist of etching barrier layer, interlayer dielectric layer, carbon-containing hard mask layer and patterning;
In the etch chamber of described etching apparatus, with the photoresist of patterning for mask, successively contact hole etching is carried out to described carbon-containing hard mask layer and interlayer dielectric layer, to form initial contact hole in described interlayer dielectric layer;
In the etch chamber of described etching apparatus, first time is carried out to the device surface behind formation initial contact hole and removes photoresist, to remove photoresist and the carbon-containing hard mask layer of described patterning;
In the etch chamber of described etching apparatus, with remaining interlayer dielectric layer for mask, remove the etching barrier layer bottom described contact hole, form contact hole;
In the etch chamber of described etching apparatus, second time is carried out to the inner surface of contact hole and removes photoresist;
Device surface after removing photoresist to second time in wet-cleaned board carries out wet-cleaned.
Further, described Semiconductor substrate is front-end devices, comprises substrate, is arranged in described suprabasil grid and sidewall structure and is formed at the source/drain region of substrate of described grid both sides; Described etching barrier layer covers described grid and described source/drain region.
Further, described grid and/or described source/drain region are formed with self-aligned metal silicate, described contact hole is formed in described self-aligned metal silicate and self-aligned metal silicate surface described in bottom-exposed.
Further, the material of described carbon-containing hard mask layer is different from described photoresist, comprises at least one in carbon containing organic dielectric layer, amorphous carbon layer, APF, carbon nitride and carborundum; And/or the material of described etching barrier layer is NDC or silicon nitride or silicon oxynitride.
Further, described interlayer dielectric layer is silica or low-K dielectric.
Further, cover layer, dielectric anti-reflective coating and bottom antireflective coating is also formed with successively between described carbon-containing hard mask layer and the photoresist of described patterning;
Further, the photoresist layer of described patterning was formed before the etch chamber of described Semiconductor substrate feeding etching apparatus, or was formed after described Semiconductor substrate sends into the etch chamber of etching apparatus.
Further, the device surface after removing photoresist to second time in wet-cleaned board carries out wet-cleaned.
Further, described first time removes photoresist as the removing of photoresist by plasma or the removing of photoresist by oxidation, and degumming process parameter comprises: process reagents is O
2or CO
2or CO, flow is 50sccm ~ 500sccm; Technological temperature is 0 DEG C ~ 50 DEG C, and the process time is 30s ~ 300s, and power is 200w ~ 2000w, and pressure is 30mT ~ 200mT.
Further, described second time is removed photoresist as removing of photoresist by plasma skill or the removing of photoresist by oxidation, and degumming process parameter comprises: process reagents is O
2or N
2or H
2, flow is 50sccm ~ 2000sccm; Technological temperature is 0 DEG C ~ 50 DEG C, and the process time is 5s ~ 30s, and power is 200w ~ 1500w, and pressure is 30mT ~ 200mT.
Further, the technological parameter of described wet-cleaned comprises: process reagents is sulfuric acid and hydrogen peroxide; Technological temperature is 0 DEG C ~ 200 DEG C; Process time is 30s ~ 600s.
Compared with prior art, contact hole shaping method provided by the invention, with the initial contact hole in interlayer dielectric layer for window, remove the etching barrier layer of bottom of window with after forming contact hole, and before wet-cleaned contact hole, adds additional second time and remove photoresist treatment process to change the hydrophily of contact hole inner surface, residual high molecular polymer in the contact hole can be removed completely when subsequent wet cleans, improve the effect that subsequent touch mesoporous metal is filled, reach the object of raising and stable prod yield.
Accompanying drawing explanation
Figure 1A to 1D is the polymer residue defect inspection figure in a kind of CIS device manufacturing processes of prior art;
Fig. 2 is the contact hole shaping method flow chart of the specific embodiment of the invention;
Fig. 3 A to 3D is the device profile structural representation in flow chart shown in Fig. 2;
Fig. 4 is the polymer residue defect inspection comparison diagram adopting conventional art and the technology of the present invention to form same batch of crystal column surface of contact hole respectively.
Embodiment
For making object of the present invention, feature becomes apparent, and be further described, but the present invention can realize by different forms, should just not be confined to described embodiment below in conjunction with accompanying drawing to the specific embodiment of the present invention.
Please refer to Fig. 2, the invention provides a kind of contact hole shaping method, comprising:
S1, sends into the etch chamber of etching apparatus, the surface of described Semiconductor substrate is formed with successively the photoresist of etching barrier layer, interlayer dielectric layer, carbon-containing hard mask layer and patterning by the Semiconductor substrate of a contact hole etching waiting;
S2, in the etch chamber of described etching apparatus, with the photoresist of patterning for mask, carries out contact hole etching to described carbon-containing hard mask layer and interlayer dielectric layer, successively to form initial contact hole in described interlayer dielectric layer;
S3, in the etch chamber of described etching apparatus, carries out first time to the device surface behind formation initial contact hole and removes photoresist, to remove photoresist and the carbon-containing hard mask layer of described patterning;
S4, in the etch chamber of described etching apparatus, with remaining interlayer dielectric layer for mask, removes the etching barrier layer bottom described contact hole, forms contact hole;
S5, in the etch chamber of described etching apparatus, carries out second time to the inner surface of contact hole and removes photoresist;
S6, the device surface after removing photoresist to second time in wet-cleaned board carries out wet-cleaned.
Please refer to Fig. 3 A, in step sl, the Semiconductor substrate 300 provided can comprise any semi-conducting material, and this semi-conducting material can include but not limited to: Si, SiC, SiGe, SiGeC, Ge alloy, GeAs, InAs, InP, and other III-V or group Ⅱ-Ⅵ compound semiconductor.Semiconductor substrate 300 can also comprise organic semiconductor or the layered semiconductor as SiGe (SGOI) on Si/SiGe, silicon-on-insulator (SOI) or insulator.In the present embodiment, Semiconductor substrate 300 is front-end devices, comprises substrate, is arranged in described suprabasil grid and sidewall structure and is formed at the source/drain region of substrate of described grid both sides.Wherein, various doping configuration and trap (well) structure can be comprised in described substrate, and be divided into nmos area and PMOS district by shallow isolating trough (STI) structure wherein, in order to simplify, be omitted in diagram.Grid are formed with stacking on described substrate, the detailed process forming grid stacking is as follows: first, substrate forms gate dielectric layer, gate dielectric layer for silica or silicon nitride and can be combined to form, also can be high K dielectric, such as, the one in HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, HfLaO, HfLaSiO, Al2O3, La2O3, ZrO2, LaAlO or its combination, or comprise the combination of high K dielectric and silica or silicon nitride; Then, described gate dielectric layer forms grid, grid can be polysilicon, metal gates or self-aligned metal silicate, metal gates can by plated metal nitride or, metal or metal alloy formed, metal nitride comprises MxNy, MxSiyNz, MxAlyNz, MaAlxSiyNz and combination thereof, and wherein M is Ta, Ti, Hf, Zr, Mo, W and combination thereof; Metal or metal alloy comprises Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La and combination thereof.Metal silicide is NiSi, CoSi, TiSi etc.
It will be appreciated by those skilled in the art that; except above-mentioned each parts; front-end devices can also comprise the metal silicide (as NiSi), embedding germanium silicon layer etc. of grid curb wall, source/drain region usually; the preparation process of these structures is technology well known to those skilled in the art, does not repeat them here.Grid curb wall structure can be a kind of in silica, silicon nitride, silicon oxynitride or they combine formation
Then, Semiconductor substrate 300 is formed uniformly etching barrier layer 301, etching barrier layer 301 can the surface, source/drain region of cover gate, side wall and substrate completely.The material of etching barrier layer 301 is silicon nitrides in the present embodiment.Also silica, silicon oxynitride, tetraethoxysilane, NDC (nitrogen carbon-silicon compound), carborundum and combination thereof can be selected in other embodiments, and/or other suitable materials.Then, described etching barrier layer 301 is formed the interlayer dielectric layer 302 of one deck through planarization, and etching barrier layer 301 covers by described interlayer dielectric layer 302 completely, and the material of interlayer dielectric layer 302 is SiO in the present embodiment
2or low-K dielectric.Can be the material being different from arbitrarily etching barrier layer 301 in other embodiments, as SiOF, SiCOH, SiO, SiCO, SiCON, SiON, fluorocarbon CF, carbonitride of silicium SiCN, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG.Interlayer dielectric layer 302 is different from the material of etching barrier layer 301, is conducive to etching ratio when improving contact hole etching.Then, described interlayer dielectric layer 302 is formed carbon-containing hard mask layer 303a, and one deck photoresist (photoresistance) is applied on carbon-containing hard mask layer 303a, then carry out graphically to photoresistance, for exposing the carbon-containing hard mask layer 303a intending the position forming contact hole, form the photoresist (PR) 303 of patterning, the photoresist (PR) 303 of patterning defines the width of contact hole, length and position etc., thereby is achieved the Semiconductor substrate of contact hole waiting etching.Then Semiconductor substrate contact hole waiting etched sends into the etch chamber of etching apparatus, etches with contact hole waiting.Wherein, the material of described carbon-containing hard mask layer 303a can be different from the material of photoresist 303, comprise carbon containing organic dielectric layer, amorphous carbon layer, APF (advanced figure film, Advanced Patterning Film), at least one in carbon nitride and carborundum, also can be the hard mask layer of other carbon containing materials; The material of described etching barrier layer 301 is NDC or silicon nitride or silicon oxynitride.
Preferably, between described carbon-containing hard mask layer 303a and the photoresist 303 of described patterning, cover layer, dielectric anti-reflective coating, bottom antireflective coating is also formed with successively; Cover layer is used for reducing the critical size that contact hole checks (AEI) after etching, the processing procedure of physical vapour deposition (PVD), ald, rotary coating (spin-on) deposition or other proper method can be adopted to be formed, silicon, carbon, nitrogen, hydrogen, metal or metallic compound may be comprised, be such as silicon nitride (NDC) or the silicon nitride of carbon containing, cover layer can form the gap-fill that pyramidal structure contributes to metal after etching.Form the photoresist 309 of dielectric anti-reflective coating (DARC), bottom antireflective coating (BARC), patterning on the cover layer successively.Wherein, the material of dielectric anti-reflective coating (DARC) is inorganic material, preferred nitrogen silica, the material of dielectric anti-reflective coating (DARC) is not used in the material of bottom antireflective coating (BARC), and the material of bottom antireflective coating is organic material.
Please refer to Fig. 3 B, in the etch chamber of described etching apparatus, using the photoresist 303 of patterned patterning as mask layer, carbon-containing hard mask layer 303a and interlayer dielectric layer 302 are carried out to the etching of vertical direction, to form initial contact hole 304.The anisotropic dry etching that the etching in initial contact hole can select other suitable or wet-etching technology, or other suitable gas mixing ratio.Stop when being etched to and exposing etching barrier layer 301 surface.The etching in the present embodiment initial contact hole 304 divides main etching and over etching two step to complete.Wherein, main etching does not generally need the etching selection ratio considering interlayer dielectric layer 302 (being generally oxide) and the etching barrier layer 301 (being generally nitride) below it, and uses the etching condition that can carry out two-forty etching to interlayer dielectric layer 302 (oxide).The upper part in the initial contact hole 304 that main etching can etch, does not now likely run through interlayer dielectric layer 302 bottom initial contact hole 304; Continue to carry out over etching process to described interlayer dielectric layer 302, form the lower part in initial contact hole 304, now run through interlayer dielectric layer 302 bottom initial contact hole 304, and likely etched away certain thickness etching barrier layer 301.
It should be noted that, the photoresist layer 303 of described patterning was normally formed before described Semiconductor substrate 300 sends into the etch chamber of etching apparatus, in other embodiments of the invention, the photoresist layer 303 of described patterning is formed after described Semiconductor substrate 300 sends into the etch chamber of etching apparatus.
Please refer to Fig. 3 C, step S3 is that original position is removed photoresist step, namely in the etch chamber of described etching apparatus, adopt removing of photoresist by plasma technique or the removing of photoresist by oxidation technique photoresist of patterning is become volatile material and discharges etching apparatus, the technological parameter that described first time removes photoresist comprises: process reagents is O
2or CO
2or CO, flow is 50sccm ~ 500sccm; Technological temperature is 0 DEG C ~ 50 DEG C, and the process time is 30s ~ 300s, and power is 200w ~ 2000w, and pressure is 30mT ~ 200mT.。This process of removing photoresist can remove the patterned photo glue on interlayer dielectric layer 302, cannot remove contact hole inner surface and form polymer residue.
Please refer to Fig. 3 D, in step s 4 which, in the etch chamber of described etching apparatus, remaining interlayer dielectric layer 302 is the interlayer dielectric layer beyond initial contact hole site, with remaining interlayer dielectric layer 302 for mask, remove the etching barrier layer 301 bottom described contact hole, form contact hole, described contact hole is by the opening portion formed after the etching barrier layer 301 removed in the initial contact hole in interlayer dielectric layer 302 and etching barrier layer 301 bottom initial contact hole.Wherein, described etching barrier layer 301 is etched, can not need to consider etching barrier layer 301 with its below the etching selection ratio of contact zone (comprising grid and source/drain region and self-aligned metal silicate) of Semiconductor substrate 300, the general two-forty etching that adopts carries out two-forty etching to etching barrier layer 301.
Please refer to Fig. 3 D, in step s 5, in the etch chamber of described etching apparatus, adopt removing of photoresist by plasma technique or removing of photoresist by oxidation technique to carry out second time to the inner surface of contact hole to remove photoresist, the polymer residue produced in the etching process (such as, step S2 etches the process that interlayer dielectric layer 302 forms the etching barrier layer bottom initial contact hole 304 and etching initial contact hole 304) of contact hole was formed before removing.Before the step of the embodiment of the present invention " wet-cleaned " in the prior art, increase the step of this second time degumming process, object is to carry out modification to contact hole inner surface, change the hydrophily of contact hole inner surface, the polymer produced in etching process before making more easily is dissolved in cleaning fluid, remove more thorough, the effect that follow-up wet clean process removes polymer can be improved thus.The technological parameter that the second time of the present embodiment is removed photoresist comprises: process reagents is O
2or N
2or H
2, flow is 50sccm ~ 2000sccm; Technological temperature is 0 DEG C ~ 50 DEG C, and the process time is 5s ~ 30s, and power is 200w ~ 1500w, and pressure is 30mT ~ 200mT.
Please continue to refer to Fig. 3 D, in step s 6, the device after second time being removed photoresist is transferred in wet-cleaned board from etching apparatus, and the device surface after removing photoresist to second time carries out wet-cleaned (wet clean).Wherein, the order of wet-cleaned of the present invention mainly remove before contact hole etching process (such as, step S2 etches interlayer dielectric layer 302 and forms the process of etching barrier layer bottom initial contact hole 304 and etching initial contact hole 304) in the polymer (mainly containing the polymer of C, F, O) that produces, and grid in the process forming contact hole bottom contact hole or source/drain region surface autoxidation and the oxide skin(coating) that formed.When grid or surface, source/drain region are formed with metal silicide (such as nickle silicide), the easier process forming contact hole in etching, forms oxide skin(coating) on its surface.Common, this oxide skin(coating) causes the follow-up conductivity being formed at conductive plunger in contact hole and active area poor compared with missionary society due to self-conductive.The technological parameter of the wet-cleaned of the present embodiment comprises: process reagents is sulfuric acid and hydrogen peroxide; Technological temperature is 0 DEG C ~ 200 DEG C, and the process time is 30s ~ 600s.
Please refer to Fig. 4, for two wafer of same batch, on the left of Fig. 4, wafer adopts conventional method to form contact hole, on the right side of Fig. 4, wafer adopts method of the present invention to form contact hole, and namely the manufacturing process difference of two wafer is only that whether before wet-cleaned, carrying out second time to contact hole inner surface removes photoresist.Carry out defect inspection (Defect Scan) to two wafer, the crystal column surface that the present invention obtains does not have polymer residue substantially, and the crystal column surface that conventional method is obtained has number of polymers to remain.
In sum, contact hole shaping method provided by the invention, with the initial contact hole in interlayer dielectric layer for window, remove the etching barrier layer of bottom of window with after forming contact hole, and before wet-cleaned contact hole, adds additional the hydrophily that the treatment process that removes photoresist for the second time changes contact hole inner surface, remove residual high molecular polymer in the contact hole, make in contact hole, substantially do not have high molecular polymer to remain, substantially improve the effect that subsequent touch mesoporous metal is filled, reach the object of raising and stable prod yield.
Obviously, those skilled in the art can carry out various change and modification to invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. a contact hole shaping method, is characterized in that, comprising:
The Semiconductor substrate of one contact hole etching waiting is sent into the etch chamber of etching apparatus, the surface of described Semiconductor substrate is formed with successively the photoresist of etching barrier layer, interlayer dielectric layer, carbon-containing hard mask layer and patterning;
In the etch chamber of described etching apparatus, with the photoresist of patterning for mask, successively contact hole etching is carried out to described carbon-containing hard mask layer and interlayer dielectric layer, to form initial contact hole in described interlayer dielectric layer;
In the etch chamber of described etching apparatus, first time is carried out to the device surface behind formation initial contact hole and removes photoresist, to remove photoresist and the carbon-containing hard mask layer of described patterning;
In the etch chamber of described etching apparatus, with remaining interlayer dielectric layer for mask, remove the etching barrier layer bottom described contact hole, form contact hole;
In the etch chamber of described etching apparatus, second time is carried out to the inner surface of contact hole and removes photoresist;
Device surface after removing photoresist to second time in wet-cleaned board carries out wet-cleaned.
2. contact hole shaping method as claimed in claim 1, it is characterized in that, described Semiconductor substrate is front-end devices, comprises substrate, is arranged in described suprabasil grid and sidewall structure and is formed at the source/drain region of substrate of described grid both sides; Described etching barrier layer covers described grid and described source/drain region.
3. contact hole shaping method as claimed in claim 2, it is characterized in that, described grid and/or described source/drain region are formed with self-aligned metal silicate, and described contact hole is formed in described self-aligned metal silicate and self-aligned metal silicate surface described in bottom-exposed.
4. contact hole shaping method as claimed in claim 1, it is characterized in that, the material of described carbon-containing hard mask layer is different from described photoresist, comprises at least one in carbon containing organic dielectric layer, amorphous carbon layer, APF, carbon nitride and carborundum; And/or the material of described etching barrier layer is NDC or silicon nitride or silicon oxynitride.
5. contact hole shaping method as claimed in claim 1, is characterized in that, be also formed with cover layer, dielectric anti-reflective coating, bottom antireflective coating successively between described carbon-containing hard mask layer and the photoresist of described patterning.
6. contact hole shaping method as claimed in claim 1, it is characterized in that, the photoresist layer of described patterning was formed before the etch chamber of described Semiconductor substrate feeding etching apparatus, or was formed after described Semiconductor substrate sends into the etch chamber of etching apparatus.
7. contact hole shaping method as claimed in claim 1, it is characterized in that, described first time removes photoresist as the removing of photoresist by plasma or the removing of photoresist by oxidation, and degumming process parameter comprises: process reagents is O
2or CO
2or CO, flow is 50sccm ~ 500sccm; Technological temperature is 0 DEG C ~ 50 DEG C, and the process time is 30s ~ 300s, and power is 200w ~ 2000w, and pressure is 30mT ~ 200mT.
8. contact hole shaping method as claimed in claim 7, it is characterized in that, described second time is removed photoresist as removing of photoresist by plasma skill or the removing of photoresist by oxidation, and degumming process parameter comprises: process reagents is O
2or N
2or H
2, flow is 50sccm ~ 2000sccm; Technological temperature is 0 DEG C ~ 50 DEG C, and the process time is 5s ~ 30s, and power is 200w ~ 1500w, and pressure is 30mT ~ 200mT.
9. contact hole shaping method as claimed in claim 8, it is characterized in that, the technological parameter of described wet-cleaned comprises: process reagents is sulfuric acid and hydrogen peroxide; Technological temperature is 0 DEG C ~ 200 DEG C, and the process time is 30s ~ 600s.
10. contact hole shaping method as claimed in claim 1, it is characterized in that, defect inspection is carried out to the device surface after wet-cleaned, adjusts the technological parameter that the described second time in the contact hole formation process of all the other Semiconductor substrate at described Semiconductor substrate place batch is removed photoresist according to check result.
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