CN104979216A - Fully enclosed gate fin-shaped semiconductor device production method - Google Patents
Fully enclosed gate fin-shaped semiconductor device production method Download PDFInfo
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- CN104979216A CN104979216A CN201510435443.8A CN201510435443A CN104979216A CN 104979216 A CN104979216 A CN 104979216A CN 201510435443 A CN201510435443 A CN 201510435443A CN 104979216 A CN104979216 A CN 104979216A
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- Prior art keywords
- fin
- semiconductor device
- channel structure
- around
- gate pole
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 10
- 239000007769 metal material Substances 0.000 claims abstract description 7
- 239000000126 substance Substances 0.000 claims abstract description 4
- 238000002360 preparation method Methods 0.000 claims description 26
- 239000011248 coating agent Substances 0.000 claims description 21
- 238000000576 coating method Methods 0.000 claims description 21
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 238000004062 sedimentation Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 238000005498 polishing Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 6
- 230000005669 field effect Effects 0.000 description 4
- 238000010276 construction Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Abstract
The invention provides a fully enclosed gate fin-shaped semiconductor device production method. The method comprises the steps of (1) providing a substrate, forming a fin structure silicon substrate on the substrate, wherein the fin structure silicon substrate comprises a source electrode structure, a drain electrode structure and a fin-shaped channel structure between the source electrode structure and the drain electrode structure, (2) forming an oxide layer to cover a semiconductor substrate and carrying out chemical mechanical polishing on the oxide layer to expose a fin-shaped channel structure, (3) carrying out doping epitaxial on the exposed fin-shaped channel structure to form an epitaxial layer on the fin-shaped channel structure, (4) using the epitaxial layer to partially remove oxide layer to thin the oxide layer, (5) partially etching the fin-shaped channel structure which is exposed due to the thinning of the oxide layer such that the epitaxial layer becomes a channel structure suspended above the substrate, and (6) sequentially depositing a high dielectric constant material layer and a metal material layer at the outer periphery of the epitaxial layer of the channel structure.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of all-around-gate pole fin-shaped semiconductor device preparation method.
Background technology
Along with the development of integrated circuit, device size is more and more less, and integrated level is more and more higher.Along with feature sizes of semiconductor devices constantly reduces because device size is more and more less, traditional planar semiconductor manufacturing technology cannot use, and the semiconductor device of on-plane surface technology arises at the historic moment, such as silicon-on-insulator, double grid, the application of the new technologies such as multiple-grid.
Current fin field effect pipe is used by wide sending out in small size field, and the semiconductor device with all-around-gate pole (gate-all-around) structure is due in device performance and the property that effectively can suppress short-channel effect (short channel effect), semiconductor industry is pursued just.Because device channel is by gate wraps, so the impact that device leaks field is also eliminated, effectively inhibit electric leakage and the punchthrough issues of device.Because all-around-gate pole is suspended on base substrate, therefore the manufacturing process of all-around-gate pole device is comparatively complicated.
Summary of the invention
Technical problem to be solved by this invention is for there is above-mentioned defect in prior art, a kind of all-around-gate pole fin-shaped semiconductor device preparation method is provided, the full metal gate structure surrounded can be formed, short-channel effect is restrained effectively in fin field effect tubular construction, leak the problem such as field and break-through, improve device performance.
In order to realize above-mentioned technical purpose, according to the present invention, providing a kind of all-around-gate pole fin-shaped semiconductor device preparation method, comprising:
First step, provides substrate, and formed over the substrate and have fin structure silicon substrate, this fin structure silicon substrate comprises source configuration, drain electrode structure and the fin-shaped channel structure between described source configuration and drain electrode structure;
Second step, forms oxide skin(coating) to cover semiconductor substrate, is polished by oxide skin(coating) chemical machinery and expose fin-shaped channel structure;
Third step, carries out doped epitaxial to form epitaxial loayer in fin-shaped channel structure to the fin-shaped channel structure exposed;
4th step, removes oxide skin(coating) with utilizing epitaxial layer portion, with thinning oxide skin(coating);
5th step, partly etches away the fin-shaped channel structure exposed due to the thinning of oxide skin(coating), epitaxial loayer is become be suspended on the channel structure of types of flexure.
Preferably, described all-around-gate pole fin-shaped semiconductor device preparation method also comprises the 6th step, deposit high dielectric constant material layer and metal material layer successively in the periphery of the epitaxial loayer as channel structure.
Preferably, described all-around-gate pole fin-shaped semiconductor device preparation method also comprises the 6th step, heavy oxide layer and deposit spathic silicon successively in the periphery of the epitaxial loayer as channel structure.
Preferably, described fin structure silicon substrate is made up of monocrystalline silicon.
Preferably, described fin structure silicon substrate is made up of germanium silicon or carbon silicon.
Preferably, in the 6th step, by ald high dielectric constant material layer.
Preferably, in the 6th step, by sputtering sedimentation metal material layer.
Preferably, the material of described oxide skin(coating) is oxide silicon.
Preferably, in the second step, described oxide skin(coating) is formed by chemical vapour deposition (CVD).
Preferably, the doping type of epitaxial loayer is Ge-doped or carbon doping.
The invention provides a kind of unsettled grid fin-shaped semiconductor device preparation method that can realize all-around-gate pole.And the present invention restrained effectively short-channel effect, leaks the problem such as field and break-through in fin field effect tubular construction, improves device performance.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily there is more complete understanding to the present invention and more easily understand its adjoint advantage and feature, wherein:
Fig. 1 and Fig. 2 schematically shows the first step of all-around-gate pole fin-shaped semiconductor device preparation method according to the preferred embodiment of the invention.
Fig. 3 schematically shows the second step of all-around-gate pole fin-shaped semiconductor device preparation method according to the preferred embodiment of the invention.
Fig. 4 schematically shows the third step of all-around-gate pole fin-shaped semiconductor device preparation method according to the preferred embodiment of the invention.
Fig. 5 schematically shows the 4th step of all-around-gate pole fin-shaped semiconductor device preparation method according to the preferred embodiment of the invention.
Fig. 6 schematically shows the 5th step of all-around-gate pole fin-shaped semiconductor device preparation method according to the preferred embodiment of the invention.
Fig. 7 and Fig. 8 schematically shows the 6th step of all-around-gate pole fin-shaped semiconductor device preparation method according to the preferred embodiment of the invention.
It should be noted that, accompanying drawing is for illustration of the present invention, and unrestricted the present invention.Note, represent that the accompanying drawing of structure may not be draw in proportion.Further, in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention clearly with understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
Fig. 1 to Fig. 8 schematically shows each step of all-around-gate pole fin-shaped semiconductor device preparation method according to the preferred embodiment of the invention.
As shown in Figures 1 to 8, all-around-gate pole fin-shaped semiconductor device preparation method comprises according to the preferred embodiment of the invention:
As the stereogram of Fig. 1 and Fig. 2 along the dotted line planar interception shown in Fig. 1 sectional view shown in, first step, substrate 100 is wherein provided, described substrate 100 is formed and has fin structure silicon substrate, this fin structure silicon substrate comprises source configuration 10, drain electrode structure 20 and the fin-shaped channel structure 30 between described source configuration and drain electrode structure;
As shown in Figure 3, second step, wherein forms oxide skin(coating) 40 to cover semiconductor substrate, is polished by oxide skin(coating) chemical machinery and expose fin-shaped channel structure 30;
As shown in Figure 4, third step, wherein carries out doped epitaxial to form epitaxial loayer 50 in fin-shaped channel structure 30 to the fin-shaped channel structure 30 exposed;
As shown in Figure 5, the 4th step, wherein utilizes epitaxial loayer 50 partly to remove oxide skin(coating), with thinning oxide skin(coating) 40;
As shown in Figure 6, the 5th step, wherein partly etches away the fin-shaped channel structure 30 exposed due to the thinning of oxide skin(coating) 40, makes epitaxial loayer 50 become the channel structure being suspended on types of flexure;
As shown in the sectional view of Fig. 7 and the stereogram of Fig. 8, the 6th step, wherein at the periphery of the epitaxial loayer 50 as channel structure successively deposit high dielectric constant material layer 60 and metal material layer 70.
Preferably, described fin structure silicon substrate is made up of monocrystalline silicon, but also can be germanium silicon, carbon silicon etc.
In the 6th step, ald high dielectric constant material layer 60 can be passed through.
In the 6th step, sputtering sedimentation metal material layer 70 can be passed through.
Preferably, the material of described oxide skin(coating) 40 is oxide silicon.
Preferably, in the second step, described oxide skin(coating) 40 is formed by chemical vapour deposition (CVD).
Preferably, the doping type of epitaxial loayer 50 is Ge-doped also can be carbon doping.
Preferably, wherein wet etching fin-shaped channel structure 30 is passed through in the 5th step.
And the present invention not must adopt metal gates, also can adopt the technique such as oxidation technology or original position moisture-generation process (ISSG) outside raceway groove, form oxide layer, deposit spathic silicon is as grid.
The invention provides a kind of unsettled grid fin-shaped semiconductor device preparation method that can realize all-around-gate pole.And the present invention restrained effectively short-channel effect, leaks the problem such as field and break-through in fin field effect tubular construction, improves device performance.
In addition, it should be noted that, unless stated otherwise or point out, otherwise the term " first " in specification, " second ", " the 3rd " etc. describe only for distinguishing each assembly, element, step etc. in specification, instead of for representing logical relation between each assembly, element, step or ordinal relation etc.
Be understandable that, although the present invention with preferred embodiment disclose as above, but above-described embodiment and be not used to limit the present invention.For any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the technology contents of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1. an all-around-gate pole fin-shaped semiconductor device preparation method, is characterized in that comprising:
First step, provides substrate, and formed over the substrate and have fin structure silicon substrate, this fin structure silicon substrate comprises source configuration, drain electrode structure and the fin-shaped channel structure between described source configuration and drain electrode structure;
Second step, forms oxide skin(coating) to cover semiconductor substrate, is polished by oxide skin(coating) chemical machinery and expose fin-shaped channel structure;
Third step, carries out doped epitaxial to form epitaxial loayer in fin-shaped channel structure to the fin-shaped channel structure exposed;
4th step, removes oxide skin(coating) with utilizing epitaxial layer portion, with thinning oxide skin(coating);
5th step, partly etches away the fin-shaped channel structure exposed due to the thinning of oxide skin(coating), epitaxial loayer is become be suspended on the channel structure of types of flexure.
2. all-around-gate pole fin-shaped semiconductor device preparation method according to claim 1, characterized by further comprising:
6th step, deposit high dielectric constant material layer and metal material layer successively in the periphery of the epitaxial loayer as channel structure.
3. all-around-gate pole fin-shaped semiconductor device preparation method according to claim 1 and 2, characterized by further comprising:
6th step, heavy oxide layer and deposit spathic silicon successively in the periphery of the epitaxial loayer as channel structure.
4. all-around-gate pole fin-shaped semiconductor device preparation method according to claim 1 and 2, it is characterized in that, described fin structure silicon substrate is made up of monocrystalline silicon.
5. all-around-gate pole fin-shaped semiconductor device preparation method according to claim 1 and 2, it is characterized in that, described fin structure silicon substrate is made up of germanium silicon or carbon silicon.
6. all-around-gate pole fin-shaped semiconductor device preparation method according to claim 1 and 2, is characterized in that, in the 6th step, by ald high dielectric constant material layer.
7. all-around-gate pole fin-shaped semiconductor device preparation method according to claim 1 and 2, is characterized in that, in the 6th step, by sputtering sedimentation metal material layer.
8. all-around-gate pole fin-shaped semiconductor device preparation method according to claim 1 and 2, is characterized in that, the material of described oxide skin(coating) is oxide silicon.
9. all-around-gate pole fin-shaped semiconductor device preparation method according to claim 1 and 2, is characterized in that, in the second step, form described oxide skin(coating) by chemical vapour deposition (CVD).
10. all-around-gate pole fin-shaped semiconductor device preparation method according to claim 1 and 2, it is characterized in that, the doping type of epitaxial loayer is Ge-doped or carbon doping.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510435443.8A CN104979216A (en) | 2015-07-22 | 2015-07-22 | Fully enclosed gate fin-shaped semiconductor device production method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510435443.8A CN104979216A (en) | 2015-07-22 | 2015-07-22 | Fully enclosed gate fin-shaped semiconductor device production method |
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| Publication Number | Publication Date |
|---|---|
| CN104979216A true CN104979216A (en) | 2015-10-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201510435443.8A Pending CN104979216A (en) | 2015-07-22 | 2015-07-22 | Fully enclosed gate fin-shaped semiconductor device production method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783615A (en) * | 2016-11-22 | 2017-05-31 | 上海华力微电子有限公司 | A kind of preparation method of all-around-gate pole fin-shaped semiconductor devices |
| CN107068764A (en) * | 2017-05-08 | 2017-08-18 | 上海华力微电子有限公司 | Semiconductor devices preparation method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080237575A1 (en) * | 2007-03-29 | 2008-10-02 | Been-Yih Jin | Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications |
| US20140175379A1 (en) * | 2012-12-20 | 2014-06-26 | Benjamin Chu-Kung | Epitaxial film on nanoscale structure |
| CN104701376A (en) * | 2013-12-10 | 2015-06-10 | 台湾积体电路制造股份有限公司 | Replacement gate nanowire device |
| US9379182B1 (en) * | 2015-02-03 | 2016-06-28 | United Microelectronics Corp. | Method for forming nanowire and semiconductor device formed with the nanowire |
-
2015
- 2015-07-22 CN CN201510435443.8A patent/CN104979216A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080237575A1 (en) * | 2007-03-29 | 2008-10-02 | Been-Yih Jin | Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications |
| US20140175379A1 (en) * | 2012-12-20 | 2014-06-26 | Benjamin Chu-Kung | Epitaxial film on nanoscale structure |
| CN104701376A (en) * | 2013-12-10 | 2015-06-10 | 台湾积体电路制造股份有限公司 | Replacement gate nanowire device |
| US9379182B1 (en) * | 2015-02-03 | 2016-06-28 | United Microelectronics Corp. | Method for forming nanowire and semiconductor device formed with the nanowire |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783615A (en) * | 2016-11-22 | 2017-05-31 | 上海华力微电子有限公司 | A kind of preparation method of all-around-gate pole fin-shaped semiconductor devices |
| CN107068764A (en) * | 2017-05-08 | 2017-08-18 | 上海华力微电子有限公司 | Semiconductor devices preparation method |
| CN107068764B (en) * | 2017-05-08 | 2020-02-18 | 上海华力微电子有限公司 | Semiconductor device manufacturing method |
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Application publication date: 20151014 |