CN104967464B - The digital BPSK modulation impulse radio ultra-wideband emitters of CMOS - Google Patents
The digital BPSK modulation impulse radio ultra-wideband emitters of CMOS Download PDFInfo
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- CN104967464B CN104967464B CN201510385425.3A CN201510385425A CN104967464B CN 104967464 B CN104967464 B CN 104967464B CN 201510385425 A CN201510385425 A CN 201510385425A CN 104967464 B CN104967464 B CN 104967464B
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Abstract
The present invention discloses a kind of digital BPSK modulation impulse radio ultra-wideband emitters of CMOS, is made up of BPSK modulation modules, time delay generation module, pulse train generation module and antenna；BPSK modulation modules are processed supplied with digital signal DATA and clock signal clk, and generation meets the data signal that BPSK modulation is required；The characteristics of every grade of time delay generative circuit of time delay generation module utilizes phase inverter time delay, the modulated signal that BPSK modulation modules are exported is postponed, different delay outputs are obtained, for controlling corresponding pulse train to produce circuit, makes the pulse unit of the time widths such as its generation；Every grade of pulse train of pulse train generation module produces circuit to produce a single pulse signal, all pulse signals to be combined into a pulse train and sent via antenna as output signal output.The wireless transmission signal that the present invention is produced meets the requirement of the frequency spectrum and working frequency range of UWB.
Description
Technical field
The present invention relates to technical field of ultra wide band, and in particular to a kind of digital BPSK modulation impulse radio ultra-wide of CMOS
Band emitter.
Background technology
Since 2002 FCC (Federal Communications Commission, FCC) issue
The spectrum criterion of cloth ultra wide band (Ultra-Wideband, UWB), and by 3.1GHz~10.6GHz frequency ranges are used as civilian ultra wide band
Since the unlicensed band of equipment, Ultra-wideband Communication Technology with its system architecture it is simple, transmission rate is high, it is low in energy consumption the features such as receive
The application study and concern in the fields such as Wireless Personal Network, wireless sensor network, biomedicine are arrived.
Current ultra-wideband communication system can be divided three classes：Direct sequence spread spectrum (DS-SS), multi-band orthogonal frequency division multiplexing (MB-
OFDM), impulse radio (IR).Wherein IR-UWB (impulse radio ultra-wideband) technology mainly uses a series of ultra-narrow pulses
Carrier as information carries out data transmission, and without any carrier signal, and narrow pulse signal can be directly or through buffering
Launched by antenna after device, therefore for other two ways, its system and circuit structure are simpler, power consumption and
Cost is lower.Currently existing many documents are studied IR-UWB emitters, and these IR-UWB emitters are mainly using following
Scheme is realized：Scheme one is first to obtain a burst pulse using digital delay circuit, burst pulse by after shaping network, frequency spectrum quilt
Required frequency range is moved, this scheme needs to use substantial amounts of electric capacity, inductance and resistance device therefore chip area and cost
It is larger；Second scheme is to produce several burst pulses first with the delay of digital circuit, then these burst pulses are synthesized one
Frequency spectrum meets desired impulse waveform, and requirement of this scheme to Waveform composition part is very strict, and the time of pulse combination is slightly
The waveform for having deviation then to obtain will distortion completely；It is using the step recovery characteristics of avalanche diode in addition with a kind of scheme
Obtain required narrow pulse signal, this scheme because technique and the standard of its avalanche diode device for using CMOS technology not
Compatibility, so being not suitable for very much carrying out CMOS chip integrated.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of digital BPSK modulation impulse radio ultra-widebands of CMOS
Emitter, its generation for being used to solve wireless transmission signal in IR-UWB communication systems meets the spectrum requirement of UWB, and pulse
Signal is operated in 3-5GHz frequency ranges.
To solve the above problems, the present invention is achieved by the following technical solutions：
CMOS digital BPSK modulation impulse radio ultra-wideband emitters, by BPSK modulation modules, time delay generation module,
Pulse train generation module and antenna are constituted；Time delay generation module includes more than 2 grades of time delay generative circuit, and pulse train is produced
Module includes that more than 2 grades of pulse train produces circuit, and every grade of time delay generative circuit correspondence one-level pulse train produces circuit；
BPSK modulation modules are processed supplied with digital signal DATA and clock signal clk, and generation meets BPSK modulation
It is required that data signal；
The characteristics of every grade of time delay generative circuit of time delay generation module utilizes phase inverter time delay, by the output of BPSK modulation modules
Modulated signal postponed, obtain different delays outputs, for controlling corresponding pulse train to produce circuit, generate it
Deng the pulse unit of time width；
Every grade of pulse train of pulse train generation module produces circuit to produce a single pulse signal, all pulse signals
A pulse train is combined into be sent via antenna as output signal output.
In such scheme, time delay generation module includes 3 grades of time delay generative circuits, and pulse train generation module includes 3 grades of arteries and veins
Rush Sequence Generation circuit.
In such scheme, the BPSK modulation modules are by 3 nmos pass transistors NM0, NM1, NM2,3 PMOS transistors
PM0, PM1, PM2 and 2 phase inverter INV0, INV1 circuit compositions；The grid of nmos pass transistor NM0, the grid of PMOS transistor PM1
After pole is connected with the input of phase inverter INV0, the data signal DATA inputs of BPSK modulation modules are formed；Nmos pass transistor
The drain electrode of NM0, the source electrode of PMOS transistor PM0 form clock signal clk input after being connected with the input of phase inverter INV1；
The output end of phase inverter INV0, the grid of PMOS transistor PM0, the grid of nmos pass transistor NM1, the grid of PMOS transistor PM2
Pole is connected with the grid of nmos pass transistor NM2；The output end of phase inverter INV1, the drain electrode of nmos pass transistor NM1 and PMOS crystal
The source electrode of pipe PM1 is connected；The source electrode of nmos pass transistor NM2 connects low level；The source electrode of PMOS transistor PM2 connects high level；NMOS
After the source electrode of transistor NM0, the drain electrode of PMOS transistor PM0 are connected with the drain electrode of nmos pass transistor NM2, BPSK modulation moulds are formed
The output end of the output signal Q of block；The source electrode of nmos pass transistor NM1, the drain electrode of PMOS transistor PM1 and PMOS transistor PM2
Drain electrode be connected after, formed BPSK modulation modules output signal QN output end.
In such scheme, every grade of time delay generative circuit is made up of 4 phase inverters INV2, INV3, INV4, INV5；Phase inverter
INV2 and phase inverter INV3 are serially connected in the output end of output signal Q of BPSK modulation modules；The input of phase inverter INV2 is made
It is this grade of Q sides input of time delay generative circuit, while forming this grade of output end of the time delayed signal A of time delay generative circuit；Instead
The output end of phase device INV2 is connected with the input of phase inverter INV3, forms the defeated of this grade of time delayed signal B of time delay generative circuit
Go out end；The output end of phase inverter INV3 is used as this grade of Q sides output end of time delay generative circuit, while forming this grade of time delay generation electricity
The output end of the time delayed signal C on road；The Q sides input of first order time delay generative circuit and the output signal Q of BPSK modulation modules
Output end be connected, the Q sides input of second level time delay generative circuit and the Q sides output end phase of first order time delay generative circuit
Even, the Q sides input of third level time delay generative circuit is connected with the Q sides output end of second level time delay generative circuit；Phase inverter
INV4 and phase inverter IN5 are serially connected in the output end of output signal QN；The input of phase inverter INV4 is generated as this grade of time delay
The QN sides input of circuit, while forming this grade of output end of the time delayed signal a of time delay generative circuit；The output of phase inverter INV4
End is connected with the input of phase inverter INV5, forms this grade of output end of the time delayed signal b of time delay generative circuit；Phase inverter INV5
Output end as this grade of QN sides output end of time delay generative circuit, while forming this grade of time delayed signal c of time delay generative circuit
Output end；The output end phase of the QN sides input of first order time delay generative circuit and the output signal QN of BPSK modulation modules
Even, the QN sides input of second level time delay generative circuit is connected with the QN sides output end of first order time delay generative circuit, the third level
The QN sides input of time delay generative circuit is connected with the QN sides output end of second level time delay generative circuit.
In such scheme, every grade of pulse train produces circuit by PMOS transistor PM3, PM4, PM5, PM6 and NMOS crystal
Pipe NM3, NM4 and NM5, NM6 compositions；The time delayed signal A's of the corresponding time delay generative circuit of grid connection of PMOS transistor PM4
Output end；The drain electrode of the source electrode connection PMOS transistor PM3 of PMOS transistor PM4；The source electrode of PMOS transistor PM3 connects electricity high
It is flat；The output end of the time delayed signal a of the corresponding time delay generative circuit of grid connection of nmos pass transistor NM3；Nmos pass transistor NM3
Source electrode connection nmos pass transistor NM4 drain electrode；The source electrode of nmos pass transistor NM4 connects low level；The grid of PMOS transistor PM3
With the output end of the time delayed signal B of the corresponding time delay generative circuit of grid connection of nmos pass transistor NM5；PMOS transistor PM6
The corresponding time delay generative circuit of the grid connection of grid and nmos pass transistor NM4 time delayed signal b output end；PMOS crystal
The drain electrode of the source electrode connection PMOS transistor PM5 of pipe PM6；The source electrode of PMOS transistor PM5 connects high level；PMOS transistor PM5
The corresponding time delay generative circuit of grid connection time delayed signal c output end；The source electrode connection NMOS of nmos pass transistor NM5 is brilliant
The drain electrode of body pipe NM6；The source electrode of nmos pass transistor NM6 connects low level；The corresponding time delay life of grid connection of nmos pass transistor NM6
Into the output end of the time delayed signal C of circuit；The drain electrode of PMOS transistor PM4, the drain electrode of nmos pass transistor NM3, PMOS transistor
After the drain electrode of PM6 is connected with the drain electrode of nmos pass transistor NM5, the output signal PG_OUT that this grade of pulse train produces circuit is formed
Output end.
In such scheme, a buffer circuit is serially connected between the pulse train generation module and antenna.
Compared with prior art, the present invention is mainly produced by BPSK modulation modules, time delay generation module and pulse train
The part of module three is constituted.Data signal, by the treatment of BPSK modulation modules, produces the BPSK numbers for meeting needs with clock signal
Word modulated signal.The digital modulation signals that BPSK modulation modules are produced are directly sent to needed for the time delay generation module of rear class is produced
Time delayed signal, produces circuit to produce the pulse train of required pulse width for driving pulse.UWB pulse transmitters of the present invention
The pulse train frequency bandwidth of generation is 3-5GHz, pulse generation circuit control signal is few, it is to avoid easily produced in traditional circuit
The disorderly problem of raw sequential, and circuit power consumption is low, simple structure, chip area are small, is conducive to integrated chip, reduces cost, and
Be conducive to improving IR-UWB transmitter performances.
Brief description of the drawings
Fig. 1 is the system construction drawing that the digital BPSK of CMOS of the present invention modulate IR-UWB emitters.
Fig. 2 is BPSK modulation module structure charts in the present invention.
Fig. 3 (a) is each time delayed signal point of BPSK modulation modules in the output end side of output signal Q in the present invention
Oscillogram.
Fig. 3 (b) is each time delayed signal point of BPSK modulation modules in the output end side of output signal QN in the present invention
Oscillogram.
Fig. 4 (a) is workflow diagram of the pulse Sequence Generation circuit under DATA=1 states in the present invention.
Fig. 4 (b) is workflow diagram of the pulse Sequence Generation circuit under DATA=0 states in the present invention.
Fig. 5 is inverter structure figure in the present invention.
Specific embodiment
The present invention is described further below in conjunction with the accompanying drawings：
A kind of digital BPSK modulation impulse radio ultra-wideband emitters of CMOS, as shown in figure 1, main modulated by BPSK
Module, time delay generation module, pulse train generation module, phase inverter and antenna are constituted.
BPSK modulation modules, as shown in Fig. 2 by 3 nmos pass transistor NM0, NM1, NM2,3 PMOS transistor PM0,
PM1, PM2 and 2 phase inverter INV0, INV1 circuit compositions.The grid of nmos pass transistor NM0, the grid of PMOS transistor PM1 and
After the input of phase inverter INV0 is connected, the data signal DATA inputs of BPSK modulation modules are formed.Nmos pass transistor NM0's
Drain electrode, the source electrode of PMOS transistor PM0 form clock signal clk input after being connected with the input of phase inverter INV1.It is anti-phase
The output end of device INV0, the grid of PMOS transistor PM0, the grid of nmos pass transistor NM1, the grid of PMOS transistor PM2 and
The grid of nmos pass transistor NM2 is connected.The output end of phase inverter INV1, the drain electrode of nmos pass transistor NM1 and PMOS transistor PM1
Source electrode be connected.The source electrode of nmos pass transistor NM2 connects low level.The source electrode of PMOS transistor PM2 connects high level.Nmos pass transistor
After the source electrode of NM0, the drain electrode of PMOS transistor PM0 are connected with the drain electrode of nmos pass transistor NM2, the defeated of BPSK modulation modules is formed
Go out the output end of signal Q.The source electrode of nmos pass transistor NM1, the drain electrode of PMOS transistor PM1 and the drain electrode of PMOS transistor PM2
After being connected, the output end of the output signal QN of BPSK modulation modules is formed.
The major function of BPSK modulation modules is to be processed supplied with digital signal DATA and clock signal clk, is produced
Meet the data signal that BPSK modulation is required.I.e. when data signal DATA is high level " 1 ", output signal Q is clock signal
CLK, control late-class circuit produces the pulse train of positive；When data signal DATA is low level " 0 ", output signal QN is negative
Clock signal "-CLK ", control late-class circuit produces the pulse train of negative.Fig. 3 (a) is that BPSK modulation modules exist in the present invention
The oscillogram of each time delayed signal point of the output end side of output signal Q.Fig. 3 (b) is that BPSK modulation modules exist in the present invention
The oscillogram of each time delayed signal point of the output end side of output signal QN.
The course of work of BPSK modulation modules is：
When DATA is high level " 1 ", nmos pass transistor NM0 and PMOS transistor PM0, PM2 are in the conduction state, and
Nmos pass transistor NM1, NM2 and PMOS transistor PM1 are in not on-state, then clock signal clk can by NM0 and
The circuit network that PM0 is composed in parallel, output signal Q is equal to CLK signal.And output signal QN draws high into electricity high by DC voltage
It is flat " 1 ".
When DATA is low level " 0 ", nmos pass transistor NM0 and PMOS transistor PM0, PM2 are in not on-state, and
Nmos pass transistor NM1, NM2 and PMOS transistor PM1 are in the conduction state, then output signal QN be equal to negative clock signal "-
CLK ", and output signal Q is communicated to earth signal " 0 ".
It can be seen that, when data digital signal is " 1 ", there is non-inverting clock signal output, when data digital signal is " 0 ", have
Negative clock signal is exported, and meets BPSK modulating mode requirements.
Time delay generation module, as shown in figure 1, being composed in series by three-level time delay generative circuit.Every grade of time delay generative circuit bag
Include 4 phase inverters INV2, INV3, INV4, INV5.Phase inverter INV2 and phase inverter INV3 are serially connected in the output of BPSK modulation modules
In the output end of signal Q.The input of phase inverter INV2 is used as this grade of Q sides input of time delay generative circuit, while forming this
The output end of the time delayed signal A of level time delay generative circuit.The output end of phase inverter INV2 is connected with the input of phase inverter INV3,
Form this grade of output end of the time delayed signal B of time delay generative circuit.The output end of phase inverter INV3 is used as this grade of time delay generation electricity
The Q sides output end on road, while forming this grade of output end of the time delayed signal C of time delay generative circuit.First order time delay generative circuit
Q sides input be connected with the output end of the output signal Q of BPSK modulation modules, the input of the Q sides of second level time delay generative circuit
End is connected with the Q sides output end of first order time delay generative circuit, and the Q sides input of third level time delay generative circuit prolongs with the second level
When generative circuit Q sides output end be connected.Phase inverter INV4 and phase inverter IN5 are serially connected in the output end of output signal QN.Instead
The input of phase device INV4 is used as this grade of QN sides input of time delay generative circuit, while forming prolonging for this grade of time delay generative circuit
When signal a output end.The output end of phase inverter INV4 is connected with the input of phase inverter INV5, forms this grade of time delay generation electricity
The output end of the time delayed signal b on road.The output end of phase inverter INV5 as this grade of QN sides output end of time delay generative circuit, while
Form this grade of output end of the time delayed signal c of time delay generative circuit.The QN sides input and BPSK of first order time delay generative circuit
The output end of the output signal QN of modulation module is connected, and QN sides input and the first order time delay of second level time delay generative circuit are given birth to
QN sides output end into circuit is connected, the QN sides input of third level time delay generative circuit and the QN of second level time delay generative circuit
Side output end is connected.
The characteristics of major function of time delay generation module is using phase inverter time delay, the modulation that BPSK modulation modules are exported
Signal is postponed, and obtains different delay outputs, for controlling corresponding pulse train to produce circuit, makes the times such as its generation
The pulse unit of width.The breadth length ratio for adjusting the inside CMOS transistor of phase inverter adjusts the anti-phase delay time of phase inverter.
The structure of phase inverter is identical, as shown in figure 5, each phase inverter is constituted by PMOS transistor PM7 and nmos pass transistor NM7.Its
After the grid of middle PMOS transistor PM7 is connected with the grid of nmos pass transistor NM7, the input of phase inverter is formed.PMOS crystal
The source electrode of pipe PM7 connects high level, and the source electrode of nmos pass transistor NM7 connects low level.The drain electrode of PMOS transistor PM7 and NMOS crystal
After the drain electrode of pipe NM7 is connected, the output end of phase inverter is formed.By adjusting transistor PM7 and NM7 in all time delay generative circuits
Breadth length ratio adjust the anti-phase delay time of phase inverter.
Pulse train generation module, as shown in figure 1, being composed in series by three-level pulse Sequence Generation circuit (PG-cell).Often
One-level pulse train produces circuit correspondence one-level time delay generative circuit.Each pulse train produces circuit, such as Fig. 3 (a) and 3 (b)
It is shown, constituted by PMOS transistor PM3, PM4, PM5, PM6 and nmos pass transistor NM3, NM4 and NM5, NM6.PMOS transistor
The output end of the time delayed signal A of the corresponding time delay generative circuit of grid connection of PM4.The source electrode connection of PMOS transistor PM4
The drain electrode of PMOS transistor PM3.The source electrode of PMOS transistor PM3 connects high level.The grid connection of nmos pass transistor NM3 is corresponding
The output end of the time delayed signal a of time delay generative circuit.The drain electrode of the source electrode connection nmos pass transistor NM4 of nmos pass transistor NM3.
The source electrode of nmos pass transistor NM4 connects low level.The grid of PMOS transistor PM3 and the grid connection institute of nmos pass transistor NM5 are right
Answer the output end of the time delayed signal B of time delay generative circuit.The grid of PMOS transistor PM6 and the grid of nmos pass transistor NM4 connect
Connect the output end of the time delayed signal b of corresponding time delay generative circuit.The source electrode connection PMOS transistor PM5 of PMOS transistor PM6
Drain electrode.The source electrode of PMOS transistor PM5 connects high level.The corresponding time delay generative circuit of grid connection of PMOS transistor PM5
Time delayed signal c output end.The drain electrode of the source electrode connection nmos pass transistor NM6 of nmos pass transistor NM5.Nmos pass transistor NM6
Source electrode connect low level.The output end of the time delayed signal C of the corresponding time delay generative circuit of grid connection of nmos pass transistor NM6.
The drain electrode of PMOS transistor PM4, the drain electrode of nmos pass transistor NM3, the drain electrode of PMOS transistor PM6 and nmos pass transistor NM5's
After drain electrode is connected, the output end that this grade of pulse train produces the output signal PG_OUT of circuit is formed.
Every one-level pulse train of pulse train generation module produces circuit correspondence one-level time delay generative circuit.Produced per one-level
A raw single pulse signal, three-level pulse signal group synthesizes a pulse train and is sent via antenna as output signal.Pass through
The breadth length ratio of transistor in every grade of pulse train generation circuit is adjusted to adjust the amplitude of formed single pulse signal, three-level simple venation
Rush signal and be combined into one kind with preferable spectral characteristic puppet Gaussian pulse signal.
The course of work of pulse train generation module is：
When DATA is high level " 1 ", output signal Q is CLK signal, is obtained in the phase inverter group of time delay generative circuit
Different delays, and output signal QN is high level " 1 ", a=" 1 ", b=" 0 ", c=" 1 ".If original state is A=" 1 ", B
=" 0 ", C=" 1 ".Nmos pass transistor NM3, NM6 and PMOS transistor PM6, PM6 conducting, nmos pass transistor NM4, NM5 and PMOS
Transistor PM4, PM5 cut-off, output signal PG_OUT is constant voltage values.As shown in 4 (a), t1 moment, A point signals are electric from height
Flat " 1 " becomes low level " 0 ", and because the reason for anti-phase time delay, now B points signal is still low level " 0 ", in A=B=
In the case of " 0 ", PMOS transistor PM3 and PM4 are turned on, and nmos pass transistor NM5 is still in cut-off state, so output
Signal PG_OUT is communicated to high-level DC voltage signal, and magnitude of voltage is driven high.T2 moment, time delay crosses end, B points letter
Number become " 1 " from " 0 ", PMOS transistor PM3 cut-offs, output signal voltage stops being driven high.When B point signals become high level
When " 1 " because phase inverter time delay reason, C points voltage still when high level " 1 ", so nmos pass transistor NM5, NM6 are turned on.
Output signal PG_OUT is communicated to signal ground (low level " 0 "), and magnitude of voltage is pulled low.T3 moment, inverter delay time knot
Shu Hou, C point signal become low level " 0 ".Nmos pass transistor NM6 ends, and output signal voltage stops being pulled low.T1-t3 this
In one change of time cycle, a small positive single pulse signal is formd in output signal.And within the continuous time,
Three PG-cell will generate the zero crossing positive single pulse signal wide of the time such as three groups.Fig. 4 (a) is pulse sequence in the present invention
Row produce workflow diagram of the circuit under DATA=1 states.
When DATA is high level " 0 ", output signal Q is low level " 0 ", A=" 0 ", B=" 1 ", C=" 0 ".And QN is
Inverting clock signal "-CLK ".If original state is a=" 0 ", b=" 1 ", c=" 0 ".Nmos pass transistor NM4, NM5 and PMOS are brilliant
Body pipe PM4, PM5 conducting, nmos pass transistor NM3, NM6 and PMOS transistor PM3, PM6 cut-off, output signal PG_OUT is constant
Magnitude of voltage.As shown in 4 (b), the t1 moment, a point signals from low level " 0 " become high level " 1 " when, and because the original of anti-phase time delay
Cause, now b points signal is still low level " 1 ", and in the case of a=b=" 1 ", nmos pass transistor NM3 and NM4 are turned on, and
PMOS transistor PM6 is still in cut-off state, so output signal PG_OUT is communicated to signal ground (low level " 0 "), electricity
Pressure value is pulled low.T2 moment, time delay terminates, and b point signals become " 0 " from " 1 ", nmos pass transistor NM4 cut-offs, output signal
Voltage stops being pulled low.When b point signals become low level " 0 " because phase inverter time delay reason, c points voltage still when electricity high
Flat " 0 ", so PMOS transistor PM5, PM6 is all turned on.Output signal PG_OUT is communicated to DC high voltage signal " 1 ", electricity
Pressure value is driven high.T3 moment, the inverter delay time terminates, and c point signals become low level " 1 ".PMOS transistor PM5 ends,
Output signal voltage stops being driven high.Formd in the change of this time cycle of t1-t3, in output signal one it is small
Negative single pulse signal.And within the continuous time, three PG-cell will generate the time negative pulses wide such as three groups to be believed
Number.Fig. 4 (b) is workflow diagram of the pulse Sequence Generation circuit under DATA=0 states in the present invention.
During output signal PG_OUT magnitudes of voltage are pulled low or draw high, the amplitude of voltage change receives the property of transistor
Can determine.When a certain link is turned on, while when changing the breadth length ratio of all transistors of the active link, output letter can be adjusted
The amplitude of the pulse formed on number.For example, when transistor PM3 and PM4 are turned on, output signal PG_OUT is communicated to electricity high
Straight flow voltage signal, magnitude of voltage is driven high.And the breadth length ratio for debugging PM3 and PM4 can adjust output signal PG_OUT and be drawn
Amplitude high.This pulse generation network forms circuit by three pulses, and all continues in time, three simple venations
Punching combination forms a complete pulse train, and whole pulse train is similar to a high-order Gaussian pulse.This high-order Gauss arteries and veins
Punching has good spectral characteristic, is conducive to the transmission of signal of communication.
A buffer circuit is serially connected between the pulse train generation module and antenna.
Claims (5)
- The digital BPSK modulation impulse radio ultra-wideband emitters of 1.CMOS, it is characterised in that：By BPSK modulation modules, time delay Generation module, pulse train generation module and antenna are constituted；Time delay generation module includes more than 2 grades of time delay generative circuit, arteries and veins Rush sequence generation module and produce circuit, and every grade of time delay generative circuit correspondence one-level pulse sequence including more than 2 grades of pulse train Row produce circuit；BPSK modulation modules are processed supplied with digital signal DATA and clock signal clk, and generation meets BPSK modulation and requires Data signal；The characteristics of every grade of time delay generative circuit of time delay generation module utilizes phase inverter time delay, the tune that BPSK modulation modules are exported Signal processed is postponed, and different delay outputs is obtained, for controlling corresponding pulse train to produce circuit, when making its generation etc. Between width pulse unit；Every grade of pulse train of pulse train generation module produces circuit to produce a single pulse signal, all pulse signal combinations Sent via antenna as output signal output into a pulse train；Above-mentioned BPSK modulation modules by 3 nmos pass transistor NM0, NM1, NM2,3 PMOS transistors PM0, PM1, PM2 and 2 Phase inverter INV0, INV1 circuit are constituted；The grid of nmos pass transistor NM0, the grid of PMOS transistor PM1 and phase inverter INV0's After input is connected, the data signal DATA inputs of BPSK modulation modules are formed；The drain electrode of nmos pass transistor NM0, PMOS are brilliant The source electrode of body pipe PM0 forms clock signal clk input after being connected with the input of phase inverter INV1；The output of phase inverter INV0 End, the grid of PMOS transistor PM0, the grid of nmos pass transistor NM1, the grid of PMOS transistor PM2 and nmos pass transistor NM2 Grid be connected；The output end of phase inverter INV1, the drain electrode of nmos pass transistor NM1 are connected with the source electrode of PMOS transistor PM1； The source electrode of nmos pass transistor NM2 connects low level；The source electrode of PMOS transistor PM2 connects high level；The source electrode of nmos pass transistor NM0, After the drain electrode of PMOS transistor PM0 is connected with the drain electrode of nmos pass transistor NM2, form the output signal Q's of BPSK modulation modules Output end；After the source electrode of nmos pass transistor NM1, the drain electrode of PMOS transistor PM1 are connected with the drain electrode of PMOS transistor PM2, shape Into the output end of the output signal QN of BPSK modulation modules.
- 2. the digital BPSK of CMOS according to claim 1 modulate impulse radio ultra-wideband emitter, it is characterised in that： Time delay generation module includes 3 grades of time delay generative circuits, and pulse train generation module includes that 3 grades of pulse trains produce circuit.
- 3. the digital BPSK of CMOS according to claim 1 and 2 modulate impulse radio ultra-wideband emitter, and its feature exists In：Every grade of time delay generative circuit is made up of 4 phase inverters INV2, INV3, INV4, INV5；Phase inverter INV2 and phase inverter INV3 It is serially connected in the output end of output signal Q of BPSK modulation modules；The input of phase inverter INV2 is used as this grade of time delay generation electricity The Q sides input on road, while forming this grade of output end of the time delayed signal A of time delay generative circuit；The output end of phase inverter INV2 Input with phase inverter INV3 is connected, and forms this grade of output end of the time delayed signal B of time delay generative circuit；Phase inverter INV3's Output end is used as this grade of Q sides output end of time delay generative circuit, while forming the defeated of this grade of time delayed signal C of time delay generative circuit Go out end；The Q sides input of first order time delay generative circuit is connected with the output end of the output signal Q of BPSK modulation modules, and second The level Q sides input of time delay generative circuit is connected with the Q sides output end of first order time delay generative circuit, third level time delay generation electricity The Q sides input on road is connected with the Q sides output end of second level time delay generative circuit；Phase inverter INV4 and phase inverter IN5 are serially connected in In the output end of output signal QN；The input of phase inverter INV4 as this grade of QN sides input of time delay generative circuit, while Form this grade of output end of the time delayed signal a of time delay generative circuit；The output end of phase inverter INV4 and the input of phase inverter INV5 End is connected, and forms this grade of output end of the time delayed signal b of time delay generative circuit；The output end of phase inverter INV5 is used as this grade of time delay The QN sides output end of generative circuit, while forming this grade of output end of the time delayed signal c of time delay generative circuit；First order time delay is given birth to QN sides input into circuit is connected with the output end of the output signal QN of BPSK modulation modules, second level time delay generative circuit QN sides input is connected with the QN sides output end of first order time delay generative circuit, the QN sides input of third level time delay generative circuit It is connected with the QN sides output end of second level time delay generative circuit.
- 4. the digital BPSK of CMOS according to claim 1 and 2 modulate impulse radio ultra-wideband emitter, and its feature exists In：Every grade of pulse train produce circuit by PMOS transistor PM3, PM4, PM5, PM6 and nmos pass transistor NM3, NM4 and NM5, NM6 is constituted；The output end of the time delayed signal A of the corresponding time delay generative circuit of grid connection of PMOS transistor PM4；PMOS crystal The drain electrode of the source electrode connection PMOS transistor PM3 of pipe PM4；The source electrode of PMOS transistor PM3 connects high level；Nmos pass transistor NM3 The corresponding time delay generative circuit of grid connection time delayed signal a output end；The source electrode connection NMOS of nmos pass transistor NM3 is brilliant The drain electrode of body pipe NM4；The source electrode of nmos pass transistor NM4 connects low level；The grid and nmos pass transistor NM5 of PMOS transistor PM3 The corresponding time delay generative circuit of grid connection time delayed signal B output end；The grid and NMOS crystal of PMOS transistor PM6 The output end of the time delayed signal b of the corresponding time delay generative circuit of grid connection of pipe NM4；The source electrode connection of PMOS transistor PM6 The drain electrode of PMOS transistor PM5；The source electrode of PMOS transistor PM5 connects high level；The grid connection of PMOS transistor PM5 is corresponding The output end of the time delayed signal c of time delay generative circuit；The drain electrode of the source electrode connection nmos pass transistor NM6 of nmos pass transistor NM5； The source electrode of nmos pass transistor NM6 connects low level；The time delay letter of the corresponding time delay generative circuit of grid connection of nmos pass transistor NM6 The output end of number C；The drain electrode of PMOS transistor PM4, the drain electrode of nmos pass transistor NM3, the drain electrode of PMOS transistor PM6 and NMOS After the drain electrode of transistor NM5 is connected, the output end that this grade of pulse train produces the output signal PG_OUT of circuit is formed.
- 5. the digital BPSK of CMOS according to claim 1 modulate impulse radio ultra-wideband emitter, it is characterised in that： A buffer circuit is serially connected between the pulse train generation module and antenna.
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Application publication date: 20151007 Assignee: Nanning Taisu Semiconductor Co.,Ltd. Assignor: GUILIN University OF ELECTRONIC TECHNOLOGY Contract record no.: X2022450000523 Denomination of invention: CMOS all digital BPSK modulated pulse radio ultra wideband transmitter Granted publication date: 20170620 License type: Common License Record date: 20221229 |
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