CN104967450B - Control logic circuit with low fan-in - Google Patents

Control logic circuit with low fan-in Download PDF

Info

Publication number
CN104967450B
CN104967450B CN201510451112.3A CN201510451112A CN104967450B CN 104967450 B CN104967450 B CN 104967450B CN 201510451112 A CN201510451112 A CN 201510451112A CN 104967450 B CN104967450 B CN 104967450B
Authority
CN
China
Prior art keywords
dynamic logic
input
logic cells
cells
dynamic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201510451112.3A
Other languages
Chinese (zh)
Other versions
CN104967450A (en
Inventor
王玉涛
姚娇娇
朱樟明
梁宇华
杨银堂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xidian University
Original Assignee
Xidian University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xidian University filed Critical Xidian University
Priority to CN201510451112.3A priority Critical patent/CN104967450B/en
Publication of CN104967450A publication Critical patent/CN104967450A/en
Application granted granted Critical
Publication of CN104967450B publication Critical patent/CN104967450B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Logic Circuits (AREA)

Abstract

The invention discloses a kind of control logic circuit with low fan-in, it is characterised in that including：Main control logic triggers circuit, main control logic circuit and sub- control logic circuit, the main control logic triggers circuit are used to produce the trigger signal for making main control logic circuit work；The main control logic circuit is used for the input for producing sub- control logic circuit, and it includes 1 and door and 4 identical dynamic logic units, and the dynamic logic unit is latched successively for 4 groups by 16 comparative results of comparator point；The sub- control logic circuit includes 4 nor gates and 16 identical dynamic logic units, and the dynamic logic unit is used to 16 latch results of main control logic circuit latching output respectively.The present invention is advantageous in that：On the premise of the low latch time is met, there is relatively low fan-in, reduce being fanned out to for comparator, comparator is worked at faster speed.

Description

Control logic circuit with low fan-in
Technical field
The present invention relates to a kind of control logic circuit, and in particular to a kind of control logic circuit with low fan-in, belongs to Field of analog integrated circuit.
Background technology
SAR ADC (gradual approaching A/D converter) are excellent because its is simple in construction, low in energy consumption, easy of integration, area is small etc. Gesture, turn into the study hotspot of industrial quarters in recent years and academia.High speed SAR ADC design mainly by comparator speed and The limitation of the settling time of DAC networks.With the raising of SAR ADC precision, using traditional control logic circuit, comparator Load capacitance can accordingly increase a lot so that the design of high-speed comparator is more difficult.If can be by control logic part The number of dynamic logic unit reduces, to reduce the load capacitance of comparator, then the speed of comparator will greatly promote.
In view of the foregoing, a kind of new low fan-in dynamic logic circuit turns into a kind of demand.
The content of the invention
It is an object of the invention to provide a kind of control logic circuit with low fan-in, by by control logic circuit Dynamic logic unit be divided into two kinds of different circuit forms of main control logic circuit and sub- control logic circuit so that 16 The load of comparator is reduced to original a quarter in SAR ADC, and ensures 16 comparative results correctly latching output.
In order to realize above-mentioned target, the present invention adopts the following technical scheme that：
A kind of control logic circuit with low fan-in, it is characterised in that in analog-digital converter, including：Main control Logic trigger circuit, main control logic circuit and sub- control logic circuit, wherein：
Foregoing main control logic triggers circuit is used to produce the trigger signal for making main control logic circuit work；
Foregoing main control logic circuit is used to produce the input of sub- control logic circuit, it include 1 it is identical with door and 4 Dynamic logic unit, 4 dynamic logic units are used for 16 comparative results of comparator points 4 groups and are latched successively；
Foregoing sub- control logic circuit includes 4 nor gates and 16 identical dynamic logic units, and 16 dynamics are patrolled Unit is collected to be used to 16 latch results of main control logic circuit latching output respectively.
The foregoing control logic circuit with low fan-in, it is characterised in that foregoing main control logic triggers circuit includes： Phase inverter I1, with OR gate XNOR, buffer BUF, phase inverter I2 and NAND gate NAND, wherein：
Foregoing phase inverter I1 input meets sampling clock Sample, foregoing phase inverter I1 output and foregoing same OR gate XNOR An input connect foregoing sub- control logic circuit, foregoing same OR gate XNOR another input and aforementioned buffers BUF's is defeated Enter to connect foregoing main control logic circuit, aforementioned buffers BUF output connects foregoing phase inverter I2 input, foregoing phase inverter I2's Output and foregoing same OR gate XNOR output connect foregoing NAND gate NAND two inputs respectively；Foregoing NAND gate NAND output Connect the input of foregoing main control logic circuit；
Foregoing phase inverter I1 output signal S0As the input signal of sub- control logic circuit, foregoing NAND gate NAND's Trigger signal of the output signal as foregoing main control logic circuit.
The foregoing control logic circuit with low fan-in, it is characterised in that foregoing main control logic circuit includes：With door AND, dynamic logic cells D L1, dynamic logic cells D L2, dynamic logic cells D L3 and dynamic logic cells D L4, wherein：
Foregoing and door AND input, foregoing dynamic logic cells D L1 input CMPP, a foregoing dynamic logic unit DL2 input CMPP, foregoing dynamic logic cells D L3 input CMPP and foregoing dynamic logic cells D L4 input CMPP are short Connect and connect the positive output CMPP of comparator, foregoing another input, foregoing dynamic logic cells D L1 input with door AND CMPN, foregoing dynamic logic cells D L2 input CMPN, foregoing dynamic logic cells D L3 input CMPN and foregoing dynamic are patrolled Collect cells D L4 input CMPN short circuits and meet the negative output CMPN of comparator；
Foregoing dynamic logic cells D L1, foregoing dynamic logic cells D L2, foregoing dynamic logic cells D L3 and foregoing dynamic Logic unit DL4 input CLK short circuits simultaneously connect foregoing and door AND output；
Foregoing dynamic logic cells D L1 input D connects the output of foregoing main control logic triggers circuit, foregoing dynamic logic Cells D L1 output Q connect foregoing dynamic logic cells D L2 input D, foregoing dynamic logic cells D L1 output P and N connect before State sub- control logic circuit；
Foregoing dynamic logic cells D L2 output Q connects foregoing dynamic logic cells D L3 input D, foregoing dynamic logic list First DL2 output P and N connects foregoing sub- control logic circuit；
Foregoing dynamic logic cells D L3 output Q connects foregoing dynamic logic cells D L4 input D, foregoing dynamic logic list First DL3 output P and N connects foregoing sub- control logic circuit；
Foregoing dynamic logic cells D L4 output Q connects foregoing main control logic triggers circuit, foregoing dynamic logic unit DL4 output P and N connects foregoing sub- control logic circuit；
Output signal P1 caused by foregoing dynamic logic cells D L10And N10, it is defeated caused by foregoing dynamic logic cells D L2 Go out signal P20And N20, output signal P3 caused by foregoing dynamic logic cells D L30And N30And foregoing dynamic logic unit Output signal P4 caused by DL40And N40Input signal as sub- control logic circuit；
Output signal Q caused by foregoing main control logic circuit0Input signal as main control logic triggers circuit.
The foregoing control logic circuit with low fan-in, it is characterised in that foregoing sub- control logic circuit includes：It is or non- Door NOR1, dynamic logic cells D L5, dynamic logic cells D L6, dynamic logic cells D L7, dynamic logic cells D L8, nor gate NOR2, dynamic logic cells D L9, dynamic logic cells D L10, dynamic logic cells D L11, dynamic logic cells D L12 or non- Door NOR3, dynamic logic cells D L13, dynamic logic cells D L14, dynamic logic cells D L15, dynamic logic cells D L16 or NOT gate NOR4, dynamic logic cells D L17, dynamic logic cells D L18, dynamic logic cells D L19 and dynamic logic unit DL20, wherein：
Foregoing dynamic logic cells D L5 input D, foregoing dynamic logic cells D L9 input D, foregoing dynamic logic list First DL13 input D and foregoing dynamic logic cells D L17 input D short circuits simultaneously connect main control logic triggers circuit；
Foregoing nor gate NOR1 input, foregoing dynamic logic cells D L5 input CMPP, a foregoing dynamic logic list First DL6 input CMPP, foregoing dynamic logic cells D L7 input CMPP and foregoing dynamic logic cells D L8 input CMPP Short circuit and the output signal P1 for connecing main dynamic logic circuit0, foregoing nor gate NOR1 another input, foregoing dynamic logic list First DL5 input CMPN, foregoing dynamic logic cells D L6 input CMPN, foregoing dynamic logic cells D L7 input CMPN and Foregoing dynamic logic cells D L8 input CMPN short circuits simultaneously meet the output signal N1 of main dynamic logic circuit0, foregoing dynamic logic Cells D L5 input CLK, foregoing dynamic logic cells D L6 input CLK, foregoing dynamic logic cells D L7 input CLK and Foregoing dynamic logic cells D L8 input CLK short circuits simultaneously connect foregoing nor gate NOR1 output, foregoing dynamic logic cells D L5 Output Q meet foregoing dynamic logic cells D L6 input D, foregoing dynamic logic cells D L6 output Q and connect foregoing dynamic logic Cells D L7 input D, foregoing dynamic logic cells D L7 output Q meets foregoing dynamic logic cells D L8 input D；
Foregoing nor gate NOR2 input, foregoing dynamic logic cells D L9 input CMPP, a foregoing dynamic logic list First DL10 input CMPP, foregoing dynamic logic cells D L11 input CMPP and foregoing dynamic logic cells D L12 input CMPP short circuits and the output signal P2 for connecing main dynamic logic circuit0, foregoing nor gate NOR2 another input, foregoing dynamic are patrolled Volume cells D L9 input CMPN, foregoing dynamic logic cells D L10 input CMPN, foregoing dynamic logic cells D L11 input CMPN and foregoing dynamic logic cells D L12 input CMPN short circuits simultaneously meet the output signal N2 of main dynamic logic circuit0, it is foregoing Dynamic logic cells D L9 input CLK, foregoing dynamic logic cells D L10 input CLK, foregoing dynamic logic cells D L11 Input CLK and foregoing dynamic logic cells D L12 input CLK short circuits and connect foregoing nor gate NOR2 output, foregoing dynamic is patrolled Before input D, foregoing dynamic logic cells D L10 that the output Q for collecting cells D L9 meets foregoing dynamic logic cells D L10 output Q connect The output Q for stating dynamic logic cells D L11 input D, foregoing dynamic logic cells D L11 connects foregoing dynamic logic cells D L12's Input D；
Foregoing nor gate NOR3 input, foregoing dynamic logic cells D L13 input CMPP, a foregoing dynamic logic Cells D L14 input CMPP, foregoing dynamic logic cells D L15 input CMPP and foregoing dynamic logic cells D L16 input CMPP short circuits and the output signal P3 for connecing main dynamic logic circuit0, foregoing nor gate NOR2 another input, foregoing dynamic are patrolled Volume cells D L13 input CMPN, foregoing dynamic logic cells D L14 input CMPN, foregoing dynamic logic cells D L15 it is defeated Enter CMPN and foregoing dynamic logic cells D L16 input CMPN short circuits and meet the output signal N3 of main dynamic logic circuit0, it is preceding State dynamic logic cells D L13 input CLK, foregoing dynamic logic cells D L14 input CLK, foregoing dynamic logic unit DL15 input CLK and foregoing dynamic logic cells D L16 input CLK short circuits simultaneously connect foregoing nor gate NOR3 output, foregoing Dynamic logic cells D L13 output Q meets foregoing dynamic logic cells D L14 input D, and foregoing dynamic logic cells D L14's is defeated The output Q for going out input D, foregoing dynamic logic cells D L15 that Q meets foregoing dynamic logic cells D L15 connects foregoing dynamic logic electricity Road DL16 input D；
Foregoing nor gate NOR4 input, foregoing dynamic logic cells D L17 input CMPP, a foregoing dynamic logic Cells D L18 input CMPP, foregoing dynamic logic cells D L19 input CMPP and foregoing dynamic logic cells D L20 input CMPP short circuits and the output signal P4 for connecing main dynamic logic circuit0, foregoing nor gate NOR4 another input, foregoing dynamic are patrolled Volume cells D L17 input CMPN, foregoing dynamic logic cells D L18 input CMPN, foregoing dynamic logic cells D L19 it is defeated Enter CMPN and foregoing dynamic logic cells D L20 input CMPN short circuits and meet the output signal N4 of main dynamic logic circuit0, it is preceding State dynamic logic cells D L17 input CLK, foregoing dynamic logic cells D L18 input CLK, foregoing dynamic logic unit DL19 input CLK and foregoing dynamic logic cells D L20 input CLK short circuits simultaneously connect foregoing nor gate NOR4 output, foregoing Dynamic logic cells D L17 output Q meets foregoing dynamic logic cells D L18 input D, and foregoing dynamic logic cells D L18's is defeated Go out Q and meet foregoing dynamic logic cells D L19 input D, foregoing dynamic logic cells D L19 output Q to connect foregoing dynamic logic list First DL20 input D；
Foregoing dynamic logic cells D L5 produces output signal P1 and N1, foregoing dynamic logic cells D L9 generations output signal P2 and N2, foregoing dynamic logic cells D L13 produce output signal P3 and N3, and foregoing dynamic logic cells D L17, which produces output, to be believed Number P4 and N4, foregoing dynamic logic cells D L6 produce output signal P5 and N5, and foregoing dynamic logic cells D L10 produces output letter Number P6 and N6, foregoing dynamic logic cells D L14 produce output signal P7 and N7, and foregoing dynamic logic cells D L18 produces output Signal P8 and N8, foregoing dynamic logic cells D L7 generation output signals P9 and N9, foregoing dynamic logic cells D L11, which is produced, to be exported Signal P10 and N10, foregoing dynamic logic cells D L15 produce output signal P11 and N11, foregoing dynamic logic cells D L19 productions Raw output signal P12 and N12, foregoing dynamic logic cells D L8 produce output signal P13 and N13, foregoing dynamic logic unit DL12 produces output signal P14 and N14, and foregoing dynamic logic cells D L16 produces output signal P15 and N15, and foregoing dynamic is patrolled Collect cells D L20 and produce output signal P16 and N16.
The present invention is advantageous in that：Because 4 dynamic logic units in main control logic circuit are recirculated Use, carry out 16 comparative results of latched comparator so that the load of comparator reduces from 16 traditional dynamic logic units To 4 dynamic logic units, so on the premise of the low latch time is met, control logic circuit of the invention has relatively low Fan-in, being fanned out to for comparator is reduced, comparator is worked at faster speed.
Brief description of the drawings
Fig. 1 is the circuit structure diagram of the control logic circuit of the present invention；
Fig. 2 is the circuit structure diagram of dynamic logic unit in main control logic circuit；
Fig. 3 is the circuit structure diagram of dynamic logic unit in sub- control logic circuit.
Embodiment
The control logic circuit of the present invention is located in analog-digital converter.
Make specific introduce to the present invention below in conjunction with the drawings and specific embodiments.
First, the structure of the control logic circuit of the present invention is introduced.
Reference picture 1, the control logic circuit with low fan-in of the invention, it includes：Main control logic triggers circuit, master Control logic circuit and sub- control logic circuit, wherein, main control logic triggers circuit, which is used for generation, makes main control logic circuit The trigger signal of work；Main control logic circuit is used for the input for producing sub- control logic circuit, and it includes 1 and door and 4 Identical dynamic logic unit, 4 dynamic logic units are locked successively for 4 groups by 16 comparative results of comparator point Deposit；Sub- control logic circuit includes 4 nor gates and 16 identical dynamic logic units, and 16 dynamic logic units are used for 16 latch results of main control logic circuit are latched into output respectively.
Be discussed in detail separately below main control logic triggers circuit, main control logic circuit and sub- control logic circuit this three Individual circuit.
First, main control logic triggers circuit
Reference picture 1, main control logic triggers circuit include：Phase inverter I1, with OR gate XNOR, buffer BUF, phase inverter I2 With NAND gate NAND.
In the main control logic triggers circuit, the annexation between each component is：Phase inverter I1 input, which connects, adopts Sample clock Sample, phase inverter I1 output and an input with OR gate XNOR connect sub- control logic circuit, with OR gate XNOR Another input and buffer BUF input connect main control logic circuit, buffer BUF output connects the defeated of phase inverter I2 Enter, phase inverter I2 output and the output with OR gate XNOR connect NAND gate NAND two inputs respectively；NAND gate NAND's is defeated Go out to connect the input of main control logic circuit.
Phase inverter I1 output signal S0As the input signal of sub- control logic circuit, NAND gate NAND output signal Trigger signal as main control logic circuit.
2nd, main control logic circuit
Reference picture 1, main control logic circuit includes：With door AND, dynamic logic cells D L1, dynamic logic cells D L2, dynamic State logic unit DL3 and dynamic logic cells D L4, wherein, 4 dynamic logic units are used for 16 comparative results of comparator Divide 4 groups to be latched successively.
In main control logic circuit, the annexation between each component is：Input with one of door AND, dynamically patrol Collect cells D L1 input CMPP, dynamic logic cells D L2 input CMPP, dynamic logic cells D L3 input CMPP and dynamic Logic unit DL4 input CMPP short circuits simultaneously meet the positive output CMPP of comparator, another input, dynamic logic with door AND Cells D L1 input CMPN, dynamic logic cells D L2 input CMPN, dynamic logic cells D L3 input CMPN and dynamic are patrolled Collect cells D L4 input CMPN short circuits and meet the negative output CMPN of comparator；
Dynamic logic cells D L1, dynamic logic cells D L2, dynamic logic cells D L3 and dynamic logic cells D L4 it is defeated Enter CLK short circuits and connect the output with door AND；
Dynamic logic cells D L1 input D connects the output of main control logic triggers circuit, and dynamic logic cells D L1's is defeated Go out the input D that Q meets dynamic logic cells D L2, dynamic logic cells D L1 output P and N connect sub- control logic circuit；
Dynamic logic cells D L2 output Q meets dynamic logic cells D L3 input D, dynamic logic cells D L2 output P Sub- control logic circuit is connect with N；
Dynamic logic cells D L3 output Q meets dynamic logic cells D L4 input D, dynamic logic cells D L3 output P Sub- control logic circuit is connect with N；
Dynamic logic cells D L4 output Q meets main control logic triggers circuit, dynamic logic cells D L4 output P and N Connect sub- control logic circuit.
Output signal P1 caused by dynamic logic cells D L10And N10, output signal P2 caused by dynamic logic cells D L20 And N20, output signal P3 caused by dynamic logic cells D L30And N30And output signal caused by dynamic logic cells D L4 P40And N40Input signal as sub- control logic circuit.
Output signal Q caused by main control logic circuit0Input signal as main control logic triggers circuit.
3rd, sub- control logic circuit
Reference picture 1, sub- control logic circuit include：Nor gate NOR1, dynamic logic cells D L5, dynamic logic unit DL6, dynamic logic cells D L7, dynamic logic cells D L8, nor gate NOR2, dynamic logic cells D L9, dynamic logic unit DL10, dynamic logic cells D L11, dynamic logic cells D L12, nor gate NOR3, dynamic logic cells D L13, dynamic logic list First DL14, dynamic logic cells D L15, dynamic logic cells D L16, nor gate NOR4, dynamic logic cells D L17, dynamic logic Cells D L18, dynamic logic cells D L19 and dynamic logic cells D L20, wherein, 16 dynamic logic units are used for master control 16 latch results of logic circuit processed latch output respectively.
In sub- control logic circuit, the annexation between each component is：Dynamic logic cells D L5 input D, move State logic unit DL9 input D, dynamic logic cells D L13 input D and dynamic logic cells D L17 input D short circuits and connect Main control logic triggers circuit；
A nor gate NOR1 input, dynamic logic cells D L5 input CMPP, dynamic logic cells D L6 input CMPP, dynamic logic cells D L7 input CMPP and dynamic logic cells D L8 input CMPP short circuits and connect main dynamic logic electricity The output signal P1 on road0, nor gate NOR1 another input, dynamic logic cells D L5 input CMPN, dynamic logic unit DL6 input CMPN, dynamic logic cells D L7 input CMPN and dynamic logic cells D L8 input CMPN short circuits and meet master The output signal N1 of dynamic logic circuit0, dynamic logic cells D L5 input CLK, dynamic logic cells D L6 input CLK, Dynamic logic cells D L7 input CLK and dynamic logic cells D L8 input CLK short circuits simultaneously connect nor gate NOR1 output, move State logic unit DL5 output Q meets dynamic logic cells D L6 input D, and dynamic logic cells D L6 output Q connects dynamic logic Cells D L7 input D, dynamic logic cells D L7 output Q meet dynamic logic cells D L8 input D；
A nor gate NOR2 input, dynamic logic cells D L9 input CMPP, dynamic logic cells D L10 input CMPP, dynamic logic cells D L11 input CMPP and dynamic logic cells D L12 input CMPP short circuits and connect main dynamic logic The output signal P2 of circuit0, nor gate NOR2 another input, dynamic logic cells D L9 input CMPN, dynamic logic list First DL10 input CMPN, dynamic logic cells D L11 input CMPN and dynamic logic cells D L12 input CMPN short circuits simultaneously Meet the output signal N2 of main dynamic logic circuit0, dynamic logic cells D L9 input CLK, dynamic logic cells D L10 input CLK, dynamic logic cells D L11 input CLK and dynamic logic cells D L12 input CLK short circuits and connect nor gate NOR2's Output, dynamic logic cells D L9 output Q meet dynamic logic cells D L10 input D, dynamic logic cells D L10 output Q Dynamic logic cells D L11 input D is met, dynamic logic cells D L11 output Q meets dynamic logic cells D L12 input D；
A nor gate NOR3 input, dynamic logic cells D L13 input CMPP, dynamic logic cells D L14 it is defeated Enter CMPP, dynamic logic cells D L15 input CMPP and dynamic logic cells D L16 input CMPP short circuits and connect active state and patrol Collect the output signal P3 of circuit0, nor gate NOR2 another input, dynamic logic cells D L13 input CMPN, dynamically patrol Volume cells D L14 input CMPN, dynamic logic cells D L15 input CMPN and dynamic logic cells D L16 input CMPN are short Connect and meet the output signal N3 of main dynamic logic circuit0, dynamic logic cells D L13 input CLK, dynamic logic cells D L14 Input CLK, dynamic logic cells D L15 input CLK and dynamic logic cells D L16 input CLK short circuits and connect nor gate NOR3 output, dynamic logic cells D L13 output Q meet dynamic logic cells D L14 input D, dynamic logic cells D L14 Output Q meet dynamic logic cells D L15 input D, dynamic logic cells D L15 output Q connects dynamic logic circuit DL16's Input D；
A nor gate NOR4 input, dynamic logic cells D L17 input CMPP, dynamic logic cells D L18 it is defeated Enter CMPP, dynamic logic cells D L19 input CMPP and dynamic logic cells D L20 input CMPP short circuits and connect active state and patrol Collect the output signal P4 of circuit0, nor gate NOR4 another input, dynamic logic cells D L17 input CMPN, dynamically patrol Volume cells D L18 input CMPN, dynamic logic cells D L19 input CMPN and dynamic logic cells D L20 input CMPN are short Connect and meet the output signal N4 of main dynamic logic circuit0, dynamic logic cells D L17 input CLK, dynamic logic cells D L18 Input CLK, dynamic logic cells D L19 input CLK and dynamic logic cells D L20 input CLK short circuits and connect nor gate NOR4 output, dynamic logic cells D L17 output Q meet dynamic logic cells D L18 input D, dynamic logic cells D L18 Output Q meet dynamic logic cells D L19 input D, dynamic logic cells D L19 output Q connects dynamic logic cells D L20's Input D.
Dynamic logic cells D L5 produces output signal P1 and N1, and dynamic logic cells D L9 produces output signal P2 and N2, Dynamic logic cells D L13 produces output signal P3 and N3, and dynamic logic cells D L17 produces output signal P4 and N4, dynamically patrolled Collect cells D L6 and produce output signal P5 and N5, dynamic logic cells D L10 produces output signal P6 and N6, dynamic logic unit DL14 produces output signal P7 and N7, and dynamic logic cells D L18 produces output signal P8 and N8, and dynamic logic cells D L7 is produced Output signal P9 and N9, dynamic logic cells D L11 produce output signal P10 and N10, and dynamic logic cells D L15 produces output Signal P11 and N11, dynamic logic cells D L19 produce output signal P12 and N12, and dynamic logic cells D L8 produces output signal P13 and N13, dynamic logic cells D L12 produce output signal P14 and N14, and dynamic logic cells D L16 produces output signal P15 And N15, dynamic logic cells D L20 produce output signal P16 and N16.
Next, introduce the operation principle of the control logic circuit of the present invention.
After sampling terminates (i.e. Sample signals are changed into low level), triggering letter is produced by main control logic triggers circuit Number, DL5, DL9, DL13 and DL17 in the DL1 and sub- control logic circuit in main control logic circuit is entered preparation Stage.When the output of comparator is effective (CMPP be respectively 1/0 or 0/1 with CMPN), CMPP and CMPN are quickly latched by DL1 And dynamic logic cells D L5, dynamic logic cells D L5 are output to by P10And N10Latch and export, it is defeated to produce top digit Go out a yard P1 (N1).At the same time, control signal caused by DL1 is input to DL2 input D, DL2 is entered preparation rank Section.When the output of comparator is effective again, CMPP and CMPN are quickly latched by DL2 and are output to dynamic logic unit DL9, dynamic logic cells D L9 are by P20And N20Latch and export generation time high-order digit output code P2 (N2).In this way until Produce digital output code P4 (N4).
After preceding 4 bit code latches, DL4 produces control signal Q0, this control signal enter main control logic triggers circuit it Afterwards, logical operation generation low level control signal is carried out with Sample signals makes the of short duration resets of DL1, reenters beam worker afterwards Make the stage.The course of work is same as described above afterwards, simply by the 5th~8 bit code by DL6, DL10 in sub- control logic circuit, DL14 and DL18, which is latched and exported, produces digital code P5 (N5)~P8 (N8).
After preceding 8 bit code latches, DL4 produces control signal makes the of short duration resets of DL1, re-enter preparation rank again Section.Said process repeats always, is exported until the comparative results of 16 times all latch, generation P1 (N1)~P16 (N16), one The latching process of change-over period terminates.
Fig. 2 is the internal circuit configuration of the dynamic logic unit (DL1~DL4) in the main control logic circuit of the present invention Figure.When D is high level, and when CLK by low transition is high level, the output signal CMPP and CMPN of comparator are delivered to P With N and latch output.Only after D is changed into low level again makes circuit reset, second could be carried out to CMPP and CMPN and locked Deposit.This dynamic logic circuit is exactly common, suitable for CMPP and CMPN in the situation that reseting stage is 0/0.
Fig. 3 is the internal circuit configuration of the dynamic logic unit (DL5~DL20) in the sub- control logic circuit of the present invention Figure.When D is high level, and when CLK by low transition is high level, the output signal CMPP and CMPN of comparator are delivered to P With N and latch output.Only after D is changed into low level again makes circuit reset, second could be carried out to CMPP and CMPN and locked Deposit.This dynamic logic circuit is applied to CMPP and CMPN in the situation that reseting stage is 1/1.
Control logic circuit provided by the invention with low fan-in, because 4 dynamics in main control logic circuit are patrolled Collect unit and be recirculated use, carry out 16 comparative results of latched comparator so that the load of comparator is from traditional 16 Dynamic logic unit is reduced to 4 dynamic logic units, so it when meeting normal latched comparator output, its fan-in is The a quarter of traditional control logic circuit so that in high speed SAR ADC design, the speed of comparator can obtain non- Often big raising.
By taking SMIC 180nm CMOS technologies as an example, contrast accesses traditional control logic circuit and accesses the low of the present invention The speed of the comparator of fan-in control logic circuit, supply voltage be 1.8V, input voltage difference be 20mV when, access traditional The delay of the comparator of control logic circuit is 930ps, and access the comparator of the low fan-in control logic circuit of the present invention Delay only has 470ps, and the speed of comparator improves nearly 1 times, and when the speed of comparator is limited by technique, the technology is to carrying The speed of high comparator is still effective.
It should be noted that the invention is not limited in any way for above-described embodiment, it is all to use equivalent substitution or equivalent change The technical scheme that the mode changed is obtained, all falls within protection scope of the present invention.

Claims (3)

  1. A kind of 1. control logic circuit with low fan-in, it is characterised in that in analog-digital converter, including：Main control is patrolled Triggers circuit, main control logic circuit and sub- control logic circuit are collected, wherein：
    The main control logic triggers circuit is used to produce the trigger signal for making main control logic circuit work；
    The main control logic circuit is used for the input for producing sub- control logic circuit, and it includes 1 and moved with door and 4 identicals State logic unit, 4 dynamic logic units are latched successively for 4 groups by 16 comparative results of comparator point；
    The sub- control logic circuit includes 4 nor gates and 16 identical dynamic logic units, 16 dynamic logic lists Member is used to 16 latch results of main control logic circuit latching output respectively；
    Wherein, the main control logic triggers circuit includes：Phase inverter I1, with OR gate XNOR, buffer BUF, phase inverter I2 and NAND gate NAND, wherein：
    The input of the phase inverter I1 connects sampling clock Sample, the phase inverter I1 output and the one of the same OR gate XNOR Individual input connects the sub- control logic circuit, and another input of the same OR gate XNOR and the input of the buffer BUF connect The main control logic circuit, the output of the buffer BUF connect the input of the phase inverter I2, the output of the phase inverter I2 Output with the same OR gate XNOR connects two inputs of the NAND gate NAND respectively；The output of the NAND gate NAND meets institute State the input of main control logic circuit；
    The output signal S of the phase inverter I10As the input signal of sub- control logic circuit, the output of the NAND gate NAND Trigger signal of the signal as the main control logic circuit.
  2. 2. the control logic circuit according to claim 1 with low fan-in, it is characterised in that the main control logic electricity Road includes：With door AND, dynamic logic cells D L1, dynamic logic cells D L2, dynamic logic cells D L3 and dynamic logic unit DL4, wherein：
    It is described with a door AND input, the input CMPP of the dynamic logic cells D L1, the dynamic logic cells D L2 Input CMPP, the dynamic logic cells D L3 input CMPP and the dynamic logic cells D L4 input CMPP short circuits and connect The positive output CMPP of comparator, described another input with door AND, the input CMPN, described of the dynamic logic cells D L1 Dynamic logic cells D L2 input CMPN, the input CMPN of the dynamic logic cells D L3 and the dynamic logic cells D L4 Input CMPN short circuits and meet the negative output CMPN of comparator；
    The dynamic logic cells D L1, the dynamic logic cells D L2, the dynamic logic cells D L3 and the dynamic logic Cells D L4 input CLK short circuits simultaneously connect the output with door AND；
    The input D of the dynamic logic cells D L1 connects the output of the main control logic triggers circuit, the dynamic logic unit The input D, the output P and N of the dynamic logic cells D L1 that DL1 output Q meets the dynamic logic cells D L2 connect the son Control logic circuit；
    The output Q of the dynamic logic cells D L2 connects the input D of the dynamic logic cells D L3, the dynamic logic unit DL2 output P and N connects the sub- control logic circuit；
    The output Q of the dynamic logic cells D L3 connects the input D of the dynamic logic cells D L4, the dynamic logic unit DL3 output P and N connects the sub- control logic circuit；
    The output Q of the dynamic logic cells D L4 connects the main control logic triggers circuit, the dynamic logic cells D L4's Output P and N connects the sub- control logic circuit；
    Output signal P1 caused by the dynamic logic cells D L10And N10, output letter caused by the dynamic logic cells D L2 Number P20And N20, output signal P3 caused by the dynamic logic cells D L30And N30And the dynamic logic cells D L4 productions Raw output signal P40And N40Input signal as sub- control logic circuit；
    Output signal Q caused by the main control logic circuit0Input signal as main control logic triggers circuit.
  3. 3. the control logic circuit according to claim 1 with low fan-in, it is characterised in that the sub- control logic electricity Road includes：Nor gate NOR1, dynamic logic cells D L5, dynamic logic cells D L6, dynamic logic cells D L7, dynamic logic list First DL8, nor gate NOR2, dynamic logic cells D L9, dynamic logic cells D L10, dynamic logic cells D L11, dynamic logic list First DL12, nor gate NOR3, dynamic logic cells D L13, dynamic logic cells D L14, dynamic logic cells D L15, dynamic logic Cells D L16, nor gate NOR4, dynamic logic cells D L17, dynamic logic cells D L18, dynamic logic cells D L19 and dynamic Logic unit DL20, wherein：
    The input D of the dynamic logic cells D L5, the input D of the dynamic logic cells D L9, the dynamic logic unit DL13 input D and the dynamic logic cells D L17 input D short circuits simultaneously connect main control logic triggers circuit；
    Input, the input CMPP of the dynamic logic cells D L5, the dynamic logic unit of the nor gate NOR1 DL6 input CMPP, the input CMPP of the dynamic logic cells D L7 and the dynamic logic cells D L8 input CMPP are short Connect and meet the output signal P1 of main dynamic logic circuit0, another input, described dynamic logic unit of the nor gate NOR1 DL5 input CMPN, the input CMPN of the dynamic logic cells D L6, the input CMPN of the dynamic logic cells D L7 and institute State dynamic logic cells D L8 input CMPN short circuits and meet the output signal N1 of main dynamic logic circuit0, the dynamic logic list First DL5 input CLK, the input CLK of the dynamic logic cells D L6, the input CLK of the dynamic logic cells D L7 and institute State dynamic logic cells D L8 input CLK short circuits and connect the output of the nor gate NOR1, the dynamic logic cells D L5's The input D, the output Q of the dynamic logic cells D L6 that output Q meets the dynamic logic cells D L6 connect the dynamic logic list First DL7 input D, the output Q of the dynamic logic cells D L7 meets the input D of the dynamic logic cells D L8；
    Input, the input CMPP of the dynamic logic cells D L9, the dynamic logic unit of the nor gate NOR2 DL10 input CMPP, the input CMPP of the dynamic logic cells D L11 and the dynamic logic cells D L12 input CMPP Short circuit and the output signal P2 for connecing main dynamic logic circuit0, another input, described dynamic logic list of the nor gate NOR2 First DL9 input CMPN, the input CMPN of the dynamic logic cells D L10, the input CMPN of the dynamic logic cells D L11 With the input CMPN short circuits of the dynamic logic cells D L12 and meet the output signal N2 of main dynamic logic circuit0, the dynamic Logic unit DL9 input CLK, the input CLK, the dynamic logic cells D L11 of the dynamic logic cells D L10 input CLK and the dynamic logic cells D L12 input CLK short circuits simultaneously connect the output of the nor gate NOR2, the dynamic logic list The output Q that first DL9 output Q meets the input D, the dynamic logic cells D L10 of the dynamic logic cells D L10 connects described move State logic unit DL11 input D, the output Q of the dynamic logic cells D L11 connects the input of the dynamic logic cells D L12 D；
    Input, the input CMPP of the dynamic logic cells D L13, the dynamic logic unit of the nor gate NOR3 DL14 input CMPP, the input CMPP of the dynamic logic cells D L15 and the dynamic logic cells D L16 input CMPP Short circuit and the output signal P3 for connecing main dynamic logic circuit0, another input, described dynamic logic list of the nor gate NOR2 First DL13 input CMPN, the input CMPN, the dynamic logic cells D L15 of the dynamic logic cells D L14 input CMPN and the dynamic logic cells D L16 input CMPN short circuits simultaneously meet the output signal N3 of main dynamic logic circuit0, it is described Dynamic logic cells D L13 input CLK, the input CLK of the dynamic logic cells D L14, the dynamic logic cells D L15 Input CLK and the dynamic logic cells D L16 input CLK short circuits and connect the output of the nor gate NOR3, the dynamic Logic unit DL13 output Q meets the input D, the output Q of the dynamic logic cells D L14 of the dynamic logic cells D L14 The input D, the output Q of the dynamic logic cells D L15 for meeting the dynamic logic cells D L15 connect the dynamic logic circuit DL16 input D；
    Input, the input CMPP of the dynamic logic cells D L17, the dynamic logic unit of the nor gate NOR4 DL18 input CMPP, the input CMPP of the dynamic logic cells D L19 and the dynamic logic cells D L20 input CMPP Short circuit and the output signal P4 for connecing main dynamic logic circuit0, another input, described dynamic logic list of the nor gate NOR4 First DL17 input CMPN, the input CMPN, the dynamic logic cells D L19 of the dynamic logic cells D L18 input CMPN and the dynamic logic cells D L20 input CMPN short circuits simultaneously meet the output signal N4 of main dynamic logic circuit0, it is described Dynamic logic cells D L17 input CLK, the input CLK of the dynamic logic cells D L18, the dynamic logic cells D L19 Input CLK and the dynamic logic cells D L20 input CLK short circuits and connect the output of the nor gate NOR4, the dynamic Logic unit DL17 output Q meets the input D, the output Q of the dynamic logic cells D L18 of the dynamic logic cells D L18 The input D, the output Q of the dynamic logic cells D L19 for meeting the dynamic logic cells D L19 connect the dynamic logic unit DL20 input D；
    The dynamic logic cells D L5 produces output signal P1 and N1, the dynamic logic cells D L9 produce output signal P2 and N2, dynamic logic cells D L13 generation the output signals P3 and N3, the dynamic logic cells D L17 produce output signal P4 And N4, dynamic logic cells D L6 generation the output signals P5 and N5, the dynamic logic cells D L10 produce output signal P6 And N6, the dynamic logic cells D L14 produce output signal P7 and N7, the dynamic logic cells D L18 generations output signal P8 and N8, the dynamic logic cells D L7 produce output signal P9 and N9, the dynamic logic cells D L11 generations output signal P10 and N10, the dynamic logic cells D L15 produce output signal P11 and N11, and the dynamic logic cells D L19 produces defeated Go out signal P12 and N12, the dynamic logic cells D L8 produces output signal P13 and N13, the dynamic logic cells D L12 productions Raw output signal P14 and N14, the dynamic logic cells D L16 produce output signal P15 and N15, the dynamic logic unit DL20 produces output signal P16 and N16.
CN201510451112.3A 2015-07-28 2015-07-28 Control logic circuit with low fan-in Expired - Fee Related CN104967450B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510451112.3A CN104967450B (en) 2015-07-28 2015-07-28 Control logic circuit with low fan-in

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510451112.3A CN104967450B (en) 2015-07-28 2015-07-28 Control logic circuit with low fan-in

Publications (2)

Publication Number Publication Date
CN104967450A CN104967450A (en) 2015-10-07
CN104967450B true CN104967450B (en) 2018-01-16

Family

ID=54221410

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510451112.3A Expired - Fee Related CN104967450B (en) 2015-07-28 2015-07-28 Control logic circuit with low fan-in

Country Status (1)

Country Link
CN (1) CN104967450B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101558451A (en) * 2006-12-12 2009-10-14 Nxp股份有限公司 Circuit with parallel functional circuits with multi-phase control inputs
CN103152050A (en) * 2013-03-04 2013-06-12 中国科学技术大学 High-speed successive approximation type analog-to-digital converter
CN103199864A (en) * 2013-02-07 2013-07-10 中国科学技术大学 Successive approximation type analog-digital converter

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101558451A (en) * 2006-12-12 2009-10-14 Nxp股份有限公司 Circuit with parallel functional circuits with multi-phase control inputs
CN103199864A (en) * 2013-02-07 2013-07-10 中国科学技术大学 Successive approximation type analog-digital converter
CN103152050A (en) * 2013-03-04 2013-06-12 中国科学技术大学 High-speed successive approximation type analog-to-digital converter

Also Published As

Publication number Publication date
CN104967450A (en) 2015-10-07

Similar Documents

Publication Publication Date Title
CN104967451B (en) Gradual approaching A/D converter
CN103650349B (en) Use SAR and TDC two level analog-digital converter
EP2296280B1 (en) Asynchronous SAR ADC
CN106067817A (en) 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate gradual approaching A/D converter
CN102006075B (en) Successive approximation type analog-to-digital converter of energy-saving capacitor array
CN109687872B (en) High-speed digital logic circuit for SAR _ ADC and sampling regulation method
CN105049043B (en) A kind of high-speed comparator with offset correction function
CN103178855B (en) Be applied to the syllogic capacitor array structure of high accuracy gradually-appoximant analog-digital converter
CN103905049A (en) High speed quick flashing plus alternating comparison type successive approximation analog to digital converter
CN102386923A (en) Asynchronous successive approximation analog-to-digital converter and conversion method
CN110535470B (en) Comparator clock generation circuit and high-speed successive approximation type analog-to-digital converter
CN106972861A (en) A kind of analog-digital converter
CN105306059A (en) Successive approximation analog to digital converter device
CN107040260A (en) Asynchronous successive approximation modulus change-over circuit
CN107017889A (en) A kind of successive approximation analog-digital converter
CN111446966A (en) Single-phase clock high-speed low-power-consumption dynamic comparator applied to SAR ADC
CN105827246A (en) Comparison circuit
CN101490961B (en) Successive approximation analog to digital converter
CN103427841B (en) A kind of system and method improving row parallel single-slope ADC switching rate
CN104967450B (en) Control logic circuit with low fan-in
CN103746715B (en) Miniature high-speed Larger Dynamic digital receiver system and method
CN110518912A (en) The comparator clock generation circuit and high speed gradual approaching A/D converter of SAR ADC
CN110690901A (en) High-speed low-power-consumption SAR ADC capacitance mismatch self-calibration method and circuit
CN106656190A (en) Continuous approximation type analog-to-digital conversion circuit and method therefor
CN114710155B (en) Logic control circuit for SAR analog-to-digital converter and SAR analog-to-digital converter

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20180116

Termination date: 20180728