CN104967437B - Silicon substrate low-leakage current cantilever beam grid cmos transmission gate and preparation method - Google Patents
Silicon substrate low-leakage current cantilever beam grid cmos transmission gate and preparation method Download PDFInfo
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- CN104967437B CN104967437B CN201510378250.3A CN201510378250A CN104967437B CN 104967437 B CN104967437 B CN 104967437B CN 201510378250 A CN201510378250 A CN 201510378250A CN 104967437 B CN104967437 B CN 104967437B
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- 230000005540 biological transmission Effects 0.000 title claims abstract description 50
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 36
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 36
- 239000010703 silicon Substances 0.000 title claims abstract description 36
- 239000000758 substrate Substances 0.000 title claims abstract description 25
- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 45
- 229920002120 photoresistant polymer Polymers 0.000 claims description 27
- 238000001259 photo etching Methods 0.000 claims description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 230000003647 oxidation Effects 0.000 claims description 13
- 238000007254 oxidation reaction Methods 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 238000013461 design Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 239000004642 Polyimide Substances 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 230000018044 dehydration Effects 0.000 claims description 3
- 238000006297 dehydration reaction Methods 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
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- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 239000008367 deionised water Substances 0.000 claims 1
- 229910021641 deionized water Inorganic materials 0.000 claims 1
- 230000005611 electricity Effects 0.000 description 4
- 238000011160 research Methods 0.000 description 2
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The present invention is a kind of silicon substrate low-leakage current cantilever beam grid cmos transmission gate and preparation method, and the transmission gate is made up of cantilever beam grid NMOS tube and cantilever beam grid PMOS.On a si substrate, its grid is suspended in above gate oxide for the making of the metal-oxide-semiconductor of the transmission gate, forms cantilever beam structure.The envisaged underneath of cantilever beam grid has battery lead plate.Cantilever beam grid actuation voltage is designed as the absolute value of the threshold voltage equal to metal-oxide-semiconductor.When the voltage between cantilever beam grid and battery lead plate is less than the absolute value of threshold voltage, cantilever beam grid are suspended in the top of gate oxide and when the voltage only between cantilever beam grid and battery lead plate reach or surpass the absolute value of threshold voltage, cantilever beam grid can just be pulled down to and are attached on gate oxide, if now input is different from the level value of output end, metal-oxide-semiconductor conducting.Field strength in gate oxide at work of the invention is smaller, so reducing grid leakage current, significantly reduces power consumption.
Description
Technical field
The present invention proposes silicon substrate low-leakage current cantilever beam grid cmos transmission gate, belongs to the technology neck of microelectromechanical systems
Domain.
Background technology
With the appearance of modern various Mobile portable formula equipment, the heat dispersion and endurance of electronic equipment face huge
Challenge.Meanwhile as the development of integrated circuit, the integrated level more and more higher of chip, the characteristic size of device constantly reduce, core
The number for the metal-oxide-semiconductor that piece is internally integrated sharply increases, clock frequency also more and more higher.Substantial amounts of metal-oxide-semiconductor is under very high frequency
Work, causes the power consumption of chip constantly to increase.This is disagreed with requirement of the modern electronic equipment to low-power consumption.Not only such as
This, too high power consumption can make chip overheating, and can not only reduce chip performance can also shorten its service life.For chip designer
For, the speed of chip and the area of silicon chip used are no longer only paid close attention in the design of chip.The power consumption of chip also sets as chip
The major issue that meter person must be concerned about.Low power dissipation design is more and more important during VLSI designs.
The power consumption of common MOS transistor device mainly includes two aspects, on the one hand refers to that AC signal produces during metal-oxide-semiconductor work
Dynamic power consumption；And on the other hand it is loss caused by leakage current.And mainly having two kinds for leakage current, one kind is grid voltage
The grid leakage current brought, leakage current when ending when another between source and drain.And the research for MOS transistor device at present collects more
In in the reduction to metal-oxide-semiconductor dynamic power consumption.The research of reduction to leakage current is seldom.The present invention is based on Si technological designs
A kind of silicon substrate low-leakage current cantilever beam grid cmos transmission gate with extremely low grid leakage current.
The content of the invention
Technical problem:It is an object of the invention to provide a kind of silicon substrate low-leakage current cantilever beam grid cmos transmission gate and preparation side
Method, when COMS transmission gates work, it is often desirable that it is for 0 in the DC current of grid.And in fact, due to conventional MOS pipe
Gate oxide it is very thin, so the field strength in gate oxide is very big, it will usually cause certain DC leakage current.Particularly same
In one cmos transmission gate, the voltage added by the grid of NMOS tube and PMOS is opposite, so with regard to shape between two grids
Into current loop.In large scale integrated circuit, the presence of this leakage current can increase power consumption of the transmission gate in work.
And this leakage current is effectively reduced in the present invention.
Technical scheme：The silicon substrate low-leakage current cantilever beam grid cmos transmission gate of the present invention is by cantilever beam grid NMOS tube and cantilever
Beam grid PMOS is formed, and cantilever beam grid NMOS tube and cantilever beam grid PMOS are connected in parallel, and the metal-oxide-semiconductor in the transmission gate is system
Make on p-type Si substrates, its lead is made using Al, and for the metal-oxide-semiconductor in transmission gate, its grid is suspended in gate oxidation
Layer top, cantilever beam grid structure is formed, this cantilever beam Shan Mao areas are produced on gate oxide, cantilever beam grid envisaged underneath
There is a battery lead plate, the upper surface of battery lead plate is provided with the covering of gate oxide, the electrode plate earthing of cantilever beam grid NMOS tube, and cantilever beam
The battery lead plate of grid PMOS connects power supply.
The threshold voltage designs of cantilever beam grid NMOS tube for just, the threshold voltage designs of cantilever beam grid PMOS be it is negative, two
The absolute value of the threshold voltage of individual metal-oxide-semiconductor is designed as equal, and the actuation voltages of cantilever beam grid is designed as the threshold value electricity equal to metal-oxide-semiconductor
The absolute value of pressure, at work, the cantilever beam grid and the cantilever beam grid of cantilever beam grid PMOS of cantilever beam grid NMOS tube are loaded
Signal on the contrary, when transmission gate is opened, the cantilever beam grid of cantilever beam grid NMOS tube connect high level, its cantilever beam grid with it is electric below
The voltage of pole plate is more than the absolute value of threshold voltage, so cantilever beam grid are pulled down on gate oxide, and cantilever beam grid PMOS
Cantilever beam grid connect low level, the voltage of its cantilever beam grid and battery lead plate below also greater than threshold voltage absolute value, so
Its cantilever beam grid is also pulled down on gate oxide, and now transmission gate of the invention is similar with traditional cmos transmission gate, as long as defeated
Go out different with incoming level, two metal-oxide-semiconductors will turn on, and realize the transmission of level, and when transmission gate closes, the lucky phase of situation
Instead, the cantilever beam grid of cantilever beam grid NMOS tube connect low level, and the cantilever beam grid of cantilever beam grid PMOS meet high level, two MOS
The cantilever beam grid of pipe float, and now no matter input and output is to be in high level or low level, what two metal-oxide-semiconductors were all off,
So transmission level value is unable to, it is achieved thereby that the function of transmission gate.
When the voltage between cantilever beam grid and battery lead plate is less than the absolute value of threshold voltage, cantilever beam grid are suspended in grid
The top of oxide layer, and when the voltage only between cantilever beam grid and battery lead plate reaches or surpasses the absolute value of threshold voltage, hang
Arm beam grid, which can just pull down to, to be attached on gate oxide, if now input is different from the level value of output end, metal-oxide-semiconductor conducting,
Compared to traditional metal-oxide-semiconductor, the present invention is due to the design of cantilever beam grid, and the field strength in gate oxide is smaller, therefore DC leakage
Stream greatly reduces, so as to effectively reduce power consumption.
The preparation method of the silicon substrate low-leakage current cantilever beam grid cmos transmission gate of the present invention is as follows：
1) p-type Si substrates are prepared；
2) initial oxidation, SiO is grown2Layer, the screen layer as doping；
3) photoetching SiO2Layer, carves N trap hand-holes；
4) N traps inject, and anneal in a nitrogen environment；After the completion of annealing, dopant redistribution is carried out at high temperature, forms N traps；
5) whole oxide layers of silicon face are removed；
6) bottom oxide growth.One layer of uniform oxide layer is grown in smooth silicon face by thermal oxide, as cushion.
7) deposited silicon nitride, then photoetching and etch nitride silicon layer retain the silicon nitride of active area, and the silicon nitride of place is gone
Remove；
8) field aoxidizes.High-temperature thermal oxidation is carried out to silicon chip, required thick oxide layer is grown in place；
9) silicon nitride and basal oxygen sheet are removed, is all gone the silicon nitride of silicon chip surface and bottom oxygen using dry etching technology
Remove.
10) one layer of photoresist, photoetching and etching photoresist are coated on silicon chip, removal needs to make cantilever beam battery lead plate position
The photoresist put.Then one layer of Al is deposited, removes the Al on photoresist and photoresist, forms battery lead plate；
11) gate oxidation is carried out.Gate oxidation is carried out, forms the oxide layer of a floor height quality；
12) CVD technology deposit polycrystalline silicon, photoetching gate figure and polysilicon lead figure are utilized, passes through dry etching technology
Etches polycrystalline silicon, retain the polysilicon of the anchor zone position of cantilever beam.
13) PMGI sacrifice layers are formed by spin coating mode, then photoetching sacrifice layer, only retains the sacrifice below cantilever beam grid
Layer；
14) evaporation growth Al；
15) photoresist is coated, retains the photoresist above cantilever beam grid；
16) Al is anti-carved, forms cantilever beam grid；
17) photoresist, photoetching and the hand-hole for etching boron are coated, injects boron, forms the active of cantilever beam grid PMOS
Area；
18) photoresist, photoetching and the hand-hole for etching phosphorus are coated, injects phosphorus, forms the active of cantilever beam grid NMOS tube
Area；
19) through hole and lead are made；
20) polyimide sacrificial layer is discharged：Developer solution soak, remove cantilever beam grid under polyimide sacrificial layer, go from
Sub- water soaks slightly, absolute ethyl alcohol dehydration, is volatilized under normal temperature, dries, form the cantilever beam grid of suspension.
In the present invention, the grid of metal-oxide-semiconductor is not directly attached on gate oxide, and is suspended in the upper of gate oxide
Side, form a cantilever beam structure.In the present invention, the threshold voltage designs of cantilever beam grid NMOS tube are just cantilever beam grid PMOS
The threshold voltage designs of pipe are negative, and the absolute value of the threshold voltage of two metal-oxide-semiconductors is designed as identical.The cantilever beam grid of metal-oxide-semiconductor
Actuation voltage is designed as equal with the absolute value of the threshold voltage of metal-oxide-semiconductor.At work, the cantilever beam grid of cantilever beam grid NMOS tube
It is opposite with the signal that the cantilever beam grid of cantilever beam grid PMOS are loaded.When transmission gate is opened, the cantilever of cantilever beam grid NMOS tube
Beam grid connect high level, and the voltage of its cantilever beam grid and battery lead plate below is more than the absolute value of threshold voltage, so cantilever beam grid
Pull down on gate oxide, and the cantilever beam grid of cantilever beam grid PMOS connect low level, its cantilever beam grid and battery lead plate below
Voltage also greater than threshold voltage absolute value, so its cantilever beam grid is also pulled down on gate oxide, now biography of the invention
Defeated door is similar with traditional cmos transmission gate, as long as output is different with incoming level, two metal-oxide-semiconductors will turn on, and realize level
Transmission.And when transmission gate closes, situation is just the opposite, and the cantilever beam grid of cantilever beam grid NMOS tube connect low level, cantilever beam grid
The cantilever beam grid of PMOS connect high level, and the cantilever beam grid of two metal-oxide-semiconductors suspend, and now no matter input and output is in high electricity
Flat or low level, what two metal-oxide-semiconductors were all off, so during metal-oxide-semiconductor in the present invention works, in cantilever beam grid and electrode
When voltage between plate is less than the absolute value of threshold voltage, cantilever beam grid are suspended in the top of gate oxide, and only in cantilever
When voltage between beam grid and battery lead plate reaches or surpasses the absolute value of threshold voltage, cantilever beam grid can just pull down to and be attached to gate oxidation
On layer, if now input is different from the level value of output end, metal-oxide-semiconductor conducting.Compared to traditional metal-oxide-semiconductor, in the present invention
Voltage of the cantilever beam grid only between grid and battery lead plate of metal-oxide-semiconductor when being more than or equal to the absolute value of threshold voltage, just meeting
It is attached on gate oxide, and is all to suspend in the case of other, so the field strength in gate oxide is smaller, therefore DC leakage current
Also greatly reduce.
Beneficial effect：Field strength of the cantilever beam grid transmission gate of the present invention at work in gate oxide is smaller, effectively reduces
Grid leakage current.So that the power consumption of the cantilever beam grid transmission gate in the present invention is effectively reduced.
Brief description of the drawings
Fig. 1 is the schematic diagram of silicon substrate low-leakage current cantilever beam grid cmos transmission gate of the present invention,
Fig. 2 is the top view of silicon substrate low-leakage current cantilever beam grid cmos transmission gate of the present invention,
Fig. 3 be Fig. 2 silicon substrate low-leakage current cantilever beam grid cmos transmission gates P-P ' to profile,
Fig. 4 be Fig. 2 silicon substrate low-leakage current cantilever beam grid cmos transmission gates A-A ' to profile,
Fig. 5 be Fig. 2 silicon substrate low-leakage current cantilever beam grid cmos transmission gates B-B ' to profile,
Figure includes：Cantilever beam grid NMOS tube 1, cantilever beam grid PMOS 2, p-type Si substrates 3, lead 4, gate oxide 5,
Cantilever beam grid 6, anchor area 7, battery lead plate 8, N traps 9, cantilever beam grid PMOS active area 10, cantilever beam grid NMOS tube active area 11, lead to
Hole 12.
Embodiment
The present invention is made up of cantilever beam grid NMOS tube 1 and cantilever beam grid PMOS 2, cantilever beam grid NMOS tube 1 and cantilever
Beam grid PMOS 2 is connected in parallel.The MOS of the transmission gate is made based on p-type Si substrates 3, and its lead 4 is made using Al.This
The grid of NMOS and PMOS in invention are suspended in the top of gate oxide 5, form cantilever beam grid 6.The anchor area of cantilever beam grid 6
7 are produced on gate oxide using polysilicon.In the lower section of each cantilever beam grid 6, two battery lead plates 8 are devised.Battery lead plate 8
There is the covering of gate oxide 5 top.The battery lead plate 8 of cantilever beam grid NMOS tube 1 is ground connection, and the electrode of cantilever beam grid PMOS 2
Plate 8 is to connect power supply.
In the present invention, the grid of metal-oxide-semiconductor is not directly attached on gate oxide 5, and is suspended in gate oxide 5
Top, form a cantilever beam grid 6.The threshold voltage designs of cantilever beam grid NMOS tube 1 are the just threshold of cantilever beam grid PMOS 2
Threshold voltage is designed as bearing, and the absolute value of the threshold voltage of two metal-oxide-semiconductors is designed as equal.The actuation voltage of the cantilever beam grid 6 is set
It is calculated as equal with the absolute value of the threshold voltage of metal-oxide-semiconductor.At work, the cantilever beam grid 6 and cantilever beam of cantilever beam grid NMOS tube 1
The signal that the cantilever beam grid 6 of grid PMOS 2 are loaded is opposite.When transmission gate is opened, the cantilever beam grid 6 of cantilever beam grid NMOS tube 1
High level is connect, the voltage of its cantilever beam grid 6 and battery lead plate 8 below is more than the absolute value of threshold voltage, so under cantilever beam grid 6
Move on gate oxide 5, and the cantilever beam grid 6 of cantilever beam grid PMOS 2 connect low level, its cantilever beam grid 6 and electrode below
The voltage of plate 8 also greater than threshold voltage absolute value, it is now of the invention so its cantilever beam grid 6 is also pulled down on gate oxide 5
Transmission gate it is similar with traditional cmos transmission gate, as long as output it is different with incoming level, two metal-oxide-semiconductors will turn on, realization
The transmission of level.And when transmission gate closes, situation is just the opposite, and the cantilever beam grid 6 of cantilever beam grid NMOS tube 1 connect low level, hangs
The cantilever beam grid 6 of arm beam grid PMOS 2 connect high level, and the cantilever beam grid 6 of two metal-oxide-semiconductors suspend, now no matter input and export
It is to be in high level or low level, what two metal-oxide-semiconductors were all off, so being unable to transmission level value.MOS in the present invention
In pipe work, when the voltage between cantilever beam grid 6 and battery lead plate 8 is less than the absolute value of threshold voltage, cantilever beam grid 6 are suspended in
The top of gate oxide 5, and the voltage only between cantilever beam grid 6 and battery lead plate 8 reaches or surpasses the absolute value of threshold voltage
When, cantilever beam grid 6 can just be pulled down to and are attached on gate oxide, if now input is different from the level value of output end, metal-oxide-semiconductor
Conducting.Compared to traditional metal-oxide-semiconductor, the electricity of the cantilever beam grid 6 of the metal-oxide-semiconductor in the present invention only between cantilever beam grid and battery lead plate
Pressure is just attached on gate oxide 5 when being more than or equal to the absolute value of threshold voltage, and is all to suspend in the case of other, so grid
Field strength in oxide layer 5 is smaller, therefore DC leakage current also greatly reduces.
The preparation method of silicon substrate low-leakage current cantilever beam grid cmos transmission gate includes following steps：
1) p-type Si substrates 3 are prepared；
2) initial oxidation, SiO is grown2Layer, the screen layer as doping；
3) photoetching SiO2Layer, carves the hand-hole of N traps 9；
4) N traps 9 inject, and anneal in a nitrogen environment；After the completion of annealing, dopant redistribution is carried out at high temperature, forms N traps
9；
5) whole oxide layers of silicon face are removed；
6) bottom oxide growth.One layer of uniform oxide layer is grown in smooth silicon face by thermal oxide, as cushion.
7) deposited silicon nitride, then photoetching and etch nitride silicon layer retain the silicon nitride of active area, and the silicon nitride of place is gone
Remove；
8) field aoxidizes.High-temperature thermal oxidation is carried out to silicon chip, required thick oxide layer is grown in place；
9) silicon nitride and basal oxygen sheet are removed, is all gone the silicon nitride of silicon chip surface and bottom oxygen using dry etching technology
Remove.
10) one layer of photoresist, photoetching and etching photoresist are coated on silicon chip, removing needs to make the position of battery lead plate 8
Photoresist.Then one layer of Al is deposited, removes the Al on photoresist and photoresist, forms battery lead plate；
11) gate oxidation is carried out.Form the oxide layer of a floor height quality；
12) CVD technology deposit polycrystalline silicon, photoetching gate figure and polysilicon lead figure are utilized, passes through dry etching technology
Etches polycrystalline silicon, retain the polysilicon of the position of anchor area 7 of cantilever beam grid 6.
13) PMGI sacrifice layers are formed by spin coating mode, then photoetching sacrifice layer, only retains the sacrificial of the lower section of cantilever beam grid 6
Domestic animal layer；
14) evaporation growth Al；
15) photoresist is coated, retains the photoresist of the top of cantilever beam grid 6；
16) Al is anti-carved, forms cantilever beam grid 6；
17) photoresist, photoetching and the hand-hole for etching boron are coated, injects boron, forms the active of cantilever beam grid PMOS 2
Area 10；
18) photoresist, photoetching and the hand-hole for etching phosphorus are coated, injects phosphorus, forms the active of cantilever beam grid NMOS tube 1
Area 11；
19) through hole 12 and lead 4 are made；
20) polyimide sacrificial layer is discharged：Developer solution soaks, and removes the polyimide sacrificial layer under cantilever beam grid 6, go from
Sub- water soaks slightly, absolute ethyl alcohol dehydration, is volatilized under normal temperature, dries, form the cantilever beam grid 6 of suspension.
Difference with the prior art of the present invention is：
The present invention can effectively reduce the grid leakage current of metal-oxide-semiconductor at work, reduce power consumption.Transmission in the present invention
Door is made up of cantilever beam grid NMOS tube and cantilever beam grid PMOS.The difference maximum with traditional metal-oxide-semiconductor of cantilever beam grid metal-oxide-semiconductor exists
In the grid of cantilever beam grid metal-oxide-semiconductor is suspended in the top of oxide layer, forms cantilever beam structure.The electricity of cantilever beam grid NMOS tube
Pole plate is ground connection, and the battery lead plate of cantilever beam grid PMOS is to connect power supply.The actuation voltage of cantilever beam grid is designed as being equal to metal-oxide-semiconductor
Threshold voltage absolute value.When the voltage between cantilever beam grid and battery lead plate is less than the absolute value of the threshold voltage of metal-oxide-semiconductor, hang
Arm beam grid have certain gap with oxide layer below.And only when voltage between cantilever beam grid and battery lead plate is equal to or greatly
When the absolute value of the threshold voltage of metal-oxide-semiconductor, cantilever beam grid can be just pulled down in the oxide layer being attached to below.So
When transmission gate in the present invention works, cantilever beam grid are only more than or equal to the exhausted of threshold voltage in its voltage between battery lead plate
During to value, just it is attached on gate oxide, and is all to suspend in the case of other, the field strength in gate oxide is smaller, so grid
AC and DC leakage current will greatly reduce so that power consumption is effectively lowered.
Meet that the structure of conditions above is considered as the silicon substrate low-leakage current cantilever beam grid cmos transmission gate of the present invention.
Claims (2)
- A kind of 1. silicon substrate low-leakage current cantilever beam grid cmos transmission gate, it is characterized in that the transmission gate is by cantilever beam grid NMOS tube (1) Formed with cantilever beam grid PMOS (2), cantilever beam grid NMOS tube (1) and cantilever beam grid PMOS (2) are connected in parallel, the transmission Metal-oxide-semiconductor in door is produced on p-type Si substrates (3), and its lead (4) is made using Al, for the MOS in transmission gate Pipe, its grid are suspended in above gate oxide (5), form cantilever beam grid structure, the anchor area (7) of this cantilever beam grid (6) It is produced on gate oxide (5), cantilever beam grid (6) envisaged underneath has battery lead plate (8), and the upper surface of battery lead plate (8) is provided with grid oxygen Change the covering of layer (5), the battery lead plate (8) of cantilever beam grid NMOS tube (1) is grounded, and the battery lead plate (8) of cantilever beam grid PMOS (2) Connect power supply；The threshold voltage designs of cantilever beam grid NMOS tube (1) for just, the threshold voltage designs of cantilever beam grid PMOS (2) be it is negative, The absolute value of the threshold voltage of two metal-oxide-semiconductors is designed as equal, and the actuation voltage of the cantilever beam grid (6) is designed as and metal-oxide-semiconductor The absolute value of threshold voltage is equal；The NMOS when the voltage between cantilever beam grid and battery lead plate is more than or equal to threshold voltage absolute value Pipe or the cantilever beam grid of PMOS are just attached on gate oxide (5), and are all to suspend in the case of other, the field in gate oxide Strong to reduce, the AC and DC leakage current of grid will reduce, so that power consumption is effectively lowered.
- 2. a kind of preparation method of silicon substrate low-leakage current cantilever beam grid cmos transmission gate as claimed in claim 1, its feature exist It is as follows in the preparation method of the transmission gate：1) p-type Si substrates are prepared；2) initial oxidation, SiO is grown2Layer, the screen layer as doping；3) photoetching SiO2Layer, carves N trap hand-holes；4) N traps inject, and anneal in a nitrogen environment；After the completion of annealing, dopant redistribution is carried out at high temperature, forms N traps；5) whole oxide layers of silicon face are removed；6) bottom oxide growth, one layer of uniform oxide layer is grown in smooth silicon face by thermal oxide, as cushion；7) deposited silicon nitride, then photoetching and etch nitride silicon layer retain the silicon nitride of active area, and the silicon nitride of place removes；8) field aoxidizes, and carries out high-temperature thermal oxidation to silicon chip, required thick oxide layer is grown in place；9) silicon nitride and basal oxygen sheet are removed, is all removed the silicon nitride of silicon chip surface and bottom oxygen using dry etching technology；10) one layer of photoresist, photoetching and etching photoresist are coated on silicon chip, removing needs to make cantilever beam electrode Board position Photoresist, one layer of Al is then deposited, remove the Al on photoresist and photoresist, form battery lead plate；11) gate oxidation is carried out, carries out gate oxidation, forms the oxide layer of a floor height quality；12) CVD technology deposit polycrystalline silicon, photoetching gate figure and polysilicon lead figure are utilized, is etched by dry etching technology Polysilicon, retain the polysilicon of the anchor zone position of cantilever beam；13) PMGI sacrifice layers are formed by spin coating mode, then photoetching sacrifice layer, only retains the sacrifice layer below cantilever beam grid；14) evaporation growth Al；15) photoresist is coated, retains the photoresist above cantilever beam grid；16) Al is anti-carved, forms cantilever beam grid；17) photoresist, photoetching and the hand-hole for etching boron are coated, injects boron, forms the active area of cantilever beam grid PMOS；18) photoresist, photoetching and the hand-hole for etching phosphorus are coated, injects phosphorus, forms the active area of cantilever beam grid NMOS tube；19) through hole and lead are made；20) polyimide sacrificial layer is discharged：Developer solution soaks, and removes the polyimide sacrificial layer under cantilever beam grid, deionized water Soak slightly, absolute ethyl alcohol dehydration, volatilized under normal temperature, dry, form the cantilever beam grid of suspension.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510378250.3A CN104967437B (en) | 2015-07-01 | 2015-07-01 | Silicon substrate low-leakage current cantilever beam grid cmos transmission gate and preparation method |
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| GB2192106A (en) * | 1986-05-21 | 1987-12-31 | Clarion Co Ltd | TTL to CMOS interface using clocked latch |
| EP0339737A1 (en) * | 1988-04-29 | 1989-11-02 | Koninklijke Philips Electronics N.V. | Integrated circuit having combinatorial logic functionality and provided with transmission gates having a low threshold voltage |
| CN101431330A (en) * | 2008-11-25 | 2009-05-13 | 中国科学院微电子研究所 | NOR gate logic circuit and forming method thereof |
| CN102385001A (en) * | 2011-08-11 | 2012-03-21 | 东南大学 | Three-channel micro-mechanical cantilever beam indirect-type microwave power sensor and preparation method |
| CN102735934A (en) * | 2012-06-20 | 2012-10-17 | 东南大学 | Phase detector based on micro-mechanical gallium arsenide-based cantilever beam and detection method |
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| CN102735935B (en) * | 2012-06-20 | 2014-08-13 | 东南大学 | Phase detector based on micro-mechanical silicon-based cantilever beam and detection method |
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Patent Citations (5)
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| GB2192106A (en) * | 1986-05-21 | 1987-12-31 | Clarion Co Ltd | TTL to CMOS interface using clocked latch |
| EP0339737A1 (en) * | 1988-04-29 | 1989-11-02 | Koninklijke Philips Electronics N.V. | Integrated circuit having combinatorial logic functionality and provided with transmission gates having a low threshold voltage |
| CN101431330A (en) * | 2008-11-25 | 2009-05-13 | 中国科学院微电子研究所 | NOR gate logic circuit and forming method thereof |
| CN102385001A (en) * | 2011-08-11 | 2012-03-21 | 东南大学 | Three-channel micro-mechanical cantilever beam indirect-type microwave power sensor and preparation method |
| CN102735934A (en) * | 2012-06-20 | 2012-10-17 | 东南大学 | Phase detector based on micro-mechanical gallium arsenide-based cantilever beam and detection method |
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