CN104967428B - Frequency domain implementation method for FPGA high-order and high-speed FIR filter - Google Patents
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Abstract
The invention discloses the frequency domain implementation method of the high-order and high-speed FIR filter for FPGA, when this method is to using frequency domain processing convolution algorithm, data caused by being taken due to zero padding can not be handled this problem in real time and be improved, and the original conventional scheme that sequence is handled using a FFT IP be changed to carry out computing to the data of input using two FFT IP.Two FFT export sectional convolution data respectively, and the latter convolution just differs N number of clock with previous convolution.Because sectional convolution length is 2N, top n data are added with previous sectional convolution, and rear N number of data are added with the latter sectional convolution.Unnecessary delay is not needed to obtain the result of convolution during such overlap-add, so as to reach real time signal processing.Therefore, frequency domain implementation method provided by the invention can not only reduce FPGA resource consumption, additionally it is possible to eliminate zero padding delay phenomenon of the prior art, improve processing speed, can realize processing in real time.
Description
Technical Field
The invention relates to the technical field of discrete signal processing, in particular to a frequency domain implementation method of a high-speed high-order FIR filter for FPGA.
Background
In digital signal processing systems, fir (finite Impulse response) filters are the most basic units. Due to its strict linear phase-frequency characteristics and stable system, FIR is the main means for processing data in many fields. With the development of electronic technology, the signal sampling frequency is continuously improved, under high-speed sampling, the FIR filter based on the multiplier structure and the FIR filter based on the distributed algorithm can perform fast pipeline real-time processing in the FPGA, but like the FIR filter based on the pulse compression technology, the order of the FIR filter is thousands of orders, and the consumption of FPGA resources is too large.
Fast Fourier Transform (FFT) is a relatively resource-consuming method that can implement such a high-order FIR filter. The design principle of the Fourier transform method is as follows:
the essence of the FIR filter is the linear convolution of a finite length sequence and an infinite length sequence, the frequency domain expression of the linear convolution is:
y(n)＝x(n)*h(n)＝IFFT{FFT[x(n)]×FFT[h(n)]}
wherein, represents discrete linear convolution relation, y (n) is output sequence, x (n) is input sequence, h (n) is filter impact response. The FFT method realizes a convolution flow chart as shown in FIG. 1: the impulse responses for the input sequence of length N and length M are complemented by M-1 0 s and N-1 0 s, respectively, and the lengths are both complemented by L-M + N-1, thus being as long as the convolved output sequence (the sequences of the convolved outputs of lengths M and N have a sequence length of M + N-1). However, the device is not suitable for use in a kitchenThen FFT operation is carried out on the input sequence and the impulse response with the length of L after zero padding, the input sequence and the impulse response are transferred to a frequency domain, then the input sequence and the impulse response are multiplied by the frequency spectrum, and then IFFT operation (inverse transform) is carried out, so that a convolution result with the length of L can be obtained. In practical application, the length of the sequence x (n) is very long, a large number of points are needed for FFT and IFFT, and hardware resources are limited, so that FFT cannot be performed on excessively long data. The data x (N) is generally segmented into a plurality of finite sets of subsequences x of length Nm(k) Then x (n) can be expressed as:
wherein,
obtaining a sequence h after zero filling of an impact response h (n) with the length of M1(n)
The linear convolution of the sequence x (n) and the sequence h (n) is therefore:
wherein, ym(k)＝h1(k)*xm(k) In that respect The linear convolution thus solved is divided into the sum of infinite short-length linear convolutions of length N + M-1, ym(k) And ym+1(k) There will be an overlap of M-1 samples with a range of mN ≦ n ≦ mN + M-2.
Obviously, the FFT method based on the above principle can significantly reduce the consumption of FPGA resources. However, the zero padding part takes time to reduce the processing speed, and forms a delay interval to prevent real-time processing of data. This makes it difficult to combine reduction of resource consumption and improvement of processing speed.
Disclosure of Invention
In order to solve the above problems, an object of the present invention is to provide a frequency domain implementation method for a high-speed high-order FIR filter of an FPGA, which improves an existing FFT method to solve the problem that it is difficult to combine the reduction of FPGA resource consumption and the increase of processing speed, that is: on one hand, the consumption of FPGA resources under the condition of high-order and high-speed is reduced, and on the other hand, the processing speed is improved to realize real-time processing.
The above purpose is realized by the following technical scheme:
a frequency domain implementation method for a high-speed high-order FIR filter for an FPGA, the method comprising:
step A: determining impulse response h (N) of FIR filter with length M, segmenting data sequence x (N) input to FIR filter into multiple segment sequences with length N, setting number of points for FFT of impulse response h (N) and segment sequences as 2N, wherein N is 2iI is a positive integer; making M equal to N +1, and if the length of M is insufficient, using zero to supplement;
and B: performing FFT operation with the point number of 2N on the impulse response h (N) to obtain an impulse response frequency spectrum H (k), dividing the segmented sequence into an odd segment and an even segment, respectively inputting the odd segment segmented sequence and the even segment segmented sequence into two FFT IP cores by using ping-pong operation to complement N zeros, then performing FFT operation with the point number of 2N to obtain an odd segment segmented sequence frequency spectrum and an even segment segmented sequence frequency spectrum with the time sequence difference of N clocks and the length of 2N, and then respectively multiplying the odd segment segmented sequence frequency spectrum and the even segment segmented sequence frequency spectrum by the impulse response frequency spectrum H (k);
and C: products of odd segment segmented sequence frequency spectrums, even segment segmented sequence frequency spectrums and impulse response frequency spectrums H (k) are respectively input into two IFFT IP cores, and odd segment convolutions and even segment convolutions with the length of 2N are respectively obtained;
step D: and adding the convolution result of the odd section and the convolution result of the even section to obtain an output signal of the FIR filter.
The number of points of FFT and IFFT operation is two times of the length N of each sequence segment, and the order is N + 1; if the order is not satisfied, the order needs to be zeroed to N + 1.
Further, in the step B, the impulse response h (N) is first zero-padded to a length of 2N, and then FFT operation with a point number of 2N is performed.
Further, in the step B, the FFT operation result with the point number of 2N is stored in the RAM, and the RAM uses the write-first mode. Because the impulse response firstly enters the FFT module, the output data firstly enters the two RAMs, the RAM uses a write mode, and the entered data can be read without being transmitted completely.
Further, in the step B, the segmented sequences 1, 3 and 5 … … enter a first FFT IP core in sequence to perform FFT operation with a point number of 2N, and the segmented sequences 2, 4 and 6 … … enter a second FFT IP core in sequence to perform FFT operation with a point number of 2N; inputting the 1 st (length N) segment sequence into the first FFT IP, then supplementing N0 s, while supplementing zero, inputting the 2 nd (length N) segment sequence into the second FFT IP, after inputting, supplementing N0 s, while supplementing zero, inputting the 3 rd segment sequence into the first FFT IP and supplementing N0 s, thus inputting the odd segment sequence and the even segment sequence in turn, the clock period of the difference between the two adjacent segment sequences is always N.
The invention has the beneficial effects that:
(1) the frequency domain implementation method of the high-speed high-order FIR filter for the FPGA provided by the invention can not only reduce the FPGA resource consumption, but also eliminate the zero filling delay phenomenon in the prior art, improve the processing speed and realize real-time processing.
(2) The frequency domain implementation scheme of the FIR filter solves the problem of resource consumption of high-speed processing under the high-order condition, optimizes the hardware structure and has configurable coefficients.
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FIG. 1: the prior art frequency domain implements a linear convolution flow diagram of two sequences.
FIG. 2: the invention provides a structure diagram for designing an FIR filter in an FPGA.
FIG. 3: the invention provides a specific timing diagram of an input signal.
FIG. 4: the invention provides a timing diagram of an output signal after segmented convolution.
FIG. 5: the invention uses FFT IP core module sketch map.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following will describe the embodiments of the present invention in further detail with reference to the accompanying drawings.
The invention provides a frequency domain implementation method of a high-speed high-order FIR filter for FPGA, which improves the problem that data cannot be processed in real time due to zero padding and time consumption when convolution operation is processed by using a frequency domain, and changes the conventional scheme of processing a sequence by using one FFT IP into the conventional scheme of processing the sequence by using two FFT IPs, wherein the sequence time sequence is shown in figure 3. The method is suitable for systems with coefficients being real integers or complex integers, for ultra-high order systems, for pulse compression systems and for systems with configurable coefficients.
The technical scheme of the invention is illustrated by taking an FPGA (field programmable gate array) of XILINX company as a platform.
The nature of an FIR filter is the linear convolution of a finite length sequence with an infinite length sequence, i.e.:
y(n)＝x(n)*h(n)＝IFFT{FFT[x(n)]×FFT[h(n)]}
for convolution of infinite length sequence, segmenting x (N) into multiple finite length sub-sequence sets x with length Nm(N) convolving in the frequency domain, wherein the impulse response h (N) has a length M ═ N + 1; x is the number ofmAnd (N) and h (N) respectively complementing N and N-1 zeros to form two sequences with the length of 2N, carrying out FFT operation of 2N points, multiplying the operated values, and carrying out IFFT operation to obtain a convolution result. The number of points of FFT and IFFT operation is two times of the length N of each sequence segment, and the order is N + 1; if the order is not satisfied, the order needs to be zeroed to N + 1. The convolution results of a plurality of lengths of 2N are added by overlap-add. Integers N, N +1 and 2N are parameters designed according to the FIR filter implementation, where N is 2iAnd i is a positive integer. The invention needs to use a XILINX FFT IP core, a pin diagram of which is shown in figure 5, firstly selects a tapelined I/O mode, the number of processing points is 2N, and the IP core can continuously carry out FFT operation on data with the length of 2N. The ports used are mainly the following:
clk: a clock port; XN _ RE, XN _ IM: inputting a real part and an imaginary part of the signal, and inputting XN _ IM as 0 when the input signal is a real signal; START: and an FFT starting signal, which can control the port to carry out continuous FFT on the signal. FWD _ INV _ WE, FWD _ INV: FWD _ INV _ WE is set to be 1, when FWD _ INV is 1, FFT operation is performed, and when FWD _ INV is 0, IFFT operation is performed; XK _ RE, XK _ IM: outputting the complex result; XK _ INDEX: and the output signal identifier represents the number of FFT output data performed at this time, the coefficient FFT module takes the signal as an address for storing FFT values, and the data FFT is taken as an address for reading values in the RAM. XN _ INDEX: the identifier of the input data indicates the number of input data of the FFT performed at this time, and is used to control the start of the next FFT.
The specific method for realizing the frequency domain of the high-speed high-order FIR filter for the FPGA provided by the invention comprises the following steps, as shown in FIG. 2:
step 1: and judging whether the impulse response or the data sequence is the impulse response or the data sequence through the CoefOrSignal signal. When the input number reaches N +1, zero is complemented according to the clock, when the length reaches 2N, the coefficient input is finished, the output results are respectively stored in two RAMs, and the RAM uses a write priority mode.
Step 2: setting the CoefOrSignal signal to be low, inputting a sequence x (N), segmenting the sequence by the length of N to obtain an odd-numbered segment segmentation sequence x1(n) and even segment segmentation sequence x2(n) separately combining the sequences x in a ping-pong operation1(n)、x2(N) inputting the signal into two FFTIPs, and when one of the FFTIPs inputs a sequence signal, zero padding is carried out on the other FFTIP, so that the FFT IP processing length is always 2N; the method comprises the following steps:
wherein,
each FFT IP always sets the start signal one clock higher before starting the input sequence, which can be judged by the XN _ INDEX signal, so that the infinite-length sequence can be processed in real time. The timing diagram is shown in fig. 3.
And step 3: respectively searching coefficient frequency spectrums (namely impulse response frequency spectrums) in respective RAMs by taking the FFT processing results of the 2 segmented sequence signals as addresses through XK _ INDEX, and thenMultiplying the rows and then respectively passing through IFFT IP (inverse fast Fourier transform) kernels to obtain a segmented convolution sequence ym(n); the output timing is shown in fig. 4. The concrete expression is as follows:
and 4, step 4: according to the overlap-add method, ym(n) and ym+1(N) there is an overlap of M-1 samples with mN ≦ N ≦ mN + M-2, since N ≦ M-1, the overlap is mN ≦ N ≦ mN + N-1, the overlap length is exactly half the convolution output length, and the last N values of the previous sequence are added to the first N values of the next sequence to obtain the result of the convolution. The concrete expression is as follows:
from the above, it can be seen that the output results are consistent with the principles.
In practical application, as long as the order N of the FIR filter is determined, other parameters such as the length of the sequence segment and the number of FFT points are determined, so that the hardware structure for increasing the order is not changed. The design can be carried out according to a larger number of points, and even if the order is small, the parameters required by the design can be achieved by zero padding. Therefore, not only the coefficient can be flexibly changed, but also the length of the coefficient can be flexibly changed.
The frequency domain implementation method of the FIR filter solves the speed problem of implementing the FIR filter on an ultra-high-order frequency domain, reduces resources, can process at high speed, and can flexibly configure FIR filter coefficients. The above-described embodiments are intended to illustrate the substance of the present invention, but are not intended to limit the scope of the present invention. It will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the invention.
Claims (3)
1. A frequency domain implementation method of a high-speed high-order FIR filter for FPGA is characterized by comprising the following steps:
step A: determining impulse response h (N) of FIR filter with length M, segmenting data sequence x (N) input to FIR filter into multiple segment sequences with length N, setting number of points for FFT of impulse response h (N) and segment sequences as 2N, wherein N is 2iI is a positive integer; making M equal to N +1, and if the length of M is insufficient, using zero to supplement;
and B: performing FFT operation with the point number of 2N on the impulse response h (N) to obtain an impulse response frequency spectrum H (k), dividing the segmented sequence into an odd segment and an even segment, respectively inputting the odd segment segmented sequence and the even segment segmented sequence into two FFT IP cores by using ping-pong operation to complement N zeros, then performing FFT operation with the point number of 2N to obtain an odd segment segmented sequence frequency spectrum and an even segment segmented sequence frequency spectrum with the time sequence difference of N clocks and the length of 2N, and then respectively multiplying the odd segment segmented sequence frequency spectrum and the even segment segmented sequence frequency spectrum by the impulse response frequency spectrum H (k);
and C: products of odd segment segmented sequence frequency spectrums, even segment segmented sequence frequency spectrums and impulse response frequency spectrums H (k) are respectively input into two IFFT IP cores, and odd segment convolutions and even segment convolutions with the length of 2N are respectively obtained;
step D: adding the convolution results of the odd sections and the convolution results of the even sections to obtain an output signal of the FIR filter;
in the step B, the segmented sequences 1, 3 and 5 … … enter a first FFT IP core in sequence to perform FFT operation with the point number of 2N, and the segmented sequences 2, 4 and 6 … … enter a second FFT IP core in sequence to perform FFT operation with the point number of 2N; after the 1 st segmented sequence is input into the first FFT IP, N0 blocks are supplemented, zero padding is carried out simultaneously, the 2 nd segmented sequence starts to be input into the second FFT IP, N0 blocks are supplemented after the input, and when zero padding is carried out, the 3 rd segmented sequence with the length of N is input into the first FFT IP and N0 blocks are supplemented, so that the odd segmented sequence and the even segmented sequence are input in sequence, and the clock period of the phase difference between the two adjacent segmented sequences is always N.
2. The frequency domain implementation method of the high-speed high-order FIR filter for FPGAs of claim 1, wherein: in the step B, the impulse response h (N) is first zero-filled to 2N length, and then FFT operation with point number of 2N is performed.
3. The frequency domain implementation method of the high-speed high-order FIR filter for FPGAs of claim 2, characterized in that: in the step B, the FFT operation result with the point number of 2N is stored in the RAM, and the RAM uses a write priority mode.
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