CN104952479A - 嵌入式非易失性存储器 - Google Patents
嵌入式非易失性存储器 Download PDFInfo
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- CN104952479A CN104952479A CN201510089671.4A CN201510089671A CN104952479A CN 104952479 A CN104952479 A CN 104952479A CN 201510089671 A CN201510089671 A CN 201510089671A CN 104952479 A CN104952479 A CN 104952479A
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- 238000000034 method Methods 0.000 claims abstract description 57
- 239000010410 layer Substances 0.000 claims description 271
- 239000000758 substrate Substances 0.000 claims description 105
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 75
- 229920005591 polysilicon Polymers 0.000 claims description 75
- 239000012044 organic layer Substances 0.000 claims description 31
- 238000007667 floating Methods 0.000 claims description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 23
- 229910052710 silicon Inorganic materials 0.000 claims description 23
- 239000010703 silicon Substances 0.000 claims description 23
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 20
- 230000015572 biosynthetic process Effects 0.000 claims description 19
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 239000002131 composite material Substances 0.000 claims description 7
- 229910021332 silicide Inorganic materials 0.000 abstract description 23
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 23
- 239000002184 metal Substances 0.000 abstract description 19
- 239000000126 substance Substances 0.000 abstract description 4
- 239000003989 dielectric material Substances 0.000 abstract description 3
- 238000007517 polishing process Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 238000000059 patterning Methods 0.000 description 7
- 238000005498 polishing Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000003860 storage Methods 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 239000011368 organic material Substances 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 229920000620 organic polymer Polymers 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 1
- 229920000636 poly(norbornene) polymer Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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Abstract
本发明提供了一种嵌入在先进的逻辑电路中的非易失性存储器及其形成方法。在非易失性存储器中,字线和擦除栅极的顶面低于控制栅极的顶面。此外,在实施自对准硅化工艺之前字线和擦除栅极被介电材料围绕。因此,在字线和擦除栅极上不能形成金属硅化物以在随后的化学机械抛光工艺中产生短路和电流泄漏的问题。
Description
技术领域
本发明涉及嵌入式非易失性存储器。
背景技术
可以通过将非易失性存储器嵌入先进的逻辑电路来进一步提高用于移动应用的先进的逻辑电路的功能和性能。然而,仍需要解决一些问题以将非易失性存储器的工艺与先进的逻辑电路集成。
发明内容
为了解决现有技术中的问题,本发明提供了一种非易失性存储器,包括:至少两个栅极堆叠件,位于衬底上,其中,每个所述栅极堆叠件均从底部到顶部依次包括隧道氧化物层、浮置栅极、中间介电层、控制栅极和掩模层;第一间隔件,位于所述两个栅极堆叠件的侧壁上;栅极介电层,位于暴露的所述衬底上;擦除栅极,位于两个所述栅极堆叠件之间并且具有不高于所述控制栅极的顶面的非平坦顶面;两条字线,位于两个所述栅极堆叠件的外侧上并且具有不高于所述控制栅极的顶面的非平坦顶面;以及覆盖层,分别位于所述擦除栅极和所述字线上。
在上述非易失性存储器中,其中,所述字线的顶面是U形。
在上述非易失性存储器中,其中,所述擦除栅极和所述字线由多晶硅制成。
在上述非易失性存储器中,其中,所述第一间隔件和所述覆盖层均包括内部氧化硅层和外部氮化硅层。
在上述非易失性存储器中,还包括位于所述字线的外侧壁上的第二间隔件。
在上述非易失性存储器中,还包括位于所述字线的外侧壁上的第二间隔件;其中,每个所述第二间隔件均包括内部氧化硅层和外部氮化硅层。
根据本发明的另一个方面,提供了一种形成非易失性存储器的方法,所述方法包括:在衬底上形成两个栅极堆叠件,其中,每个所述栅极堆叠件均从底部到顶部依次包括隧道氧化物层、浮置栅极、中间介电层、控制栅极和掩模层;在所述两个栅极堆叠件的侧壁上形成第一间隔件;在暴露的所述衬底上形成栅极介电层;形成位于所述两个栅极堆叠件之间的擦除栅极和位于所述两个栅极堆叠件的外侧上的两条字线,其中,所述擦除栅极和两条所述字线的顶面不高于所述控制栅极的顶面;在所述擦除栅极和所述字线的顶面上分别形成复合覆盖层。
在上述方法中,其中,所述擦除栅极和所述字线的形成包括:形成具有厚度大于所述栅极堆叠件的厚度的多晶硅层;各向异性地蚀刻所述多晶硅层直到暴露出所述衬底以形成所述擦除栅极和所述字线。
在上述方法中,其中,所述复合覆盖层的形成包括:在所述衬底之上形成第一介电层;各向异性地蚀刻所述第一介电层直到暴露出所述衬底以在所述字线和所述擦除栅极上形成第一覆盖层;在所述衬底之上形成第二介电层;以及各向异性地蚀刻所述第二介电层直到暴露出所述衬底以在所述字线的侧壁上形成第二间隔件以及在所述擦除栅极上形成第二覆盖层,其中,复合覆盖层包括所述第一覆盖层和所述第二覆盖层。
在上述方法中,其中,所述复合覆盖层的形成包括:在所述衬底之上形成第一介电层;各向异性地蚀刻所述第一介电层直到暴露出所述衬底以在所述字线和所述擦除栅极上形成第一覆盖层;在所述衬底之上形成第二介电层;以及各向异性地蚀刻所述第二介电层直到暴露出所述衬底以在所述字线的侧壁上形成第二间隔件以及在所述擦除栅极上形成第二覆盖层,其中,复合覆盖层包括所述第一覆盖层和所述第二覆盖层;其中,每个所述第一介电层和所述第二介电层均包括底部氧化硅层和顶部氮化硅层。
在上述方法中,其中,每个所述第一间隔件均包括内部氧化硅层和外部氮化硅层。
根据本发明的又一个方面,提供了一种形成非易失性存储器的方法,所述方法包括:在衬底上形成两个栅极堆叠件,其中,每个所述栅极堆叠件均从底部到顶部依次包括隧道氧化物层、浮置栅极、中间介电层、控制栅极和掩模层;在所述两个栅极堆叠件的侧壁上形成第一间隔件;在暴露的所述衬底上形成栅极介电层;在所述衬底之上依次形成多晶硅层和有机层,其中,所述多晶硅层的厚度小于所述隧道氧化物层、所述浮置栅极、所述中间介电层和所述控制栅极的总厚度,以及所述有机层的顶面高于所述栅极堆叠件的顶面;蚀刻所述有机层和所述多晶硅层直到所述多晶硅层的顶面不高于所述控制栅极的顶面;去除所述有机层的残留物;在所述衬底之上形成第一介电层;以及各向异性地蚀刻所述第一介电层和所述第一介电层下方的所述多晶硅层直到暴露出所述衬底,其中,蚀刻所述多晶硅层以在两个所述栅极堆叠件之间形成擦除栅极以及形成位于所述两个栅极堆叠件的外侧上的字线,以及蚀刻所述第一介电层以在所述字线和所述擦除栅极上形成第一覆盖层。
在上述方法中,其中,每个所述第一间隔件均包括内部氧化硅层和外部氮化硅层。
在上述方法中,还包括:在所述衬底之上形成第二介电层;以及各向异性地蚀刻所述第二介电层直到暴露出所述衬底以在所述字线的外侧壁上形成第二间隔件。
根据本发明的又一个方面,提供了一种形成非易失性存储器的方法,所述方法包括:在衬底上形成两个栅极堆叠件,其中,每个所述栅极堆叠件均从底部到顶部依次包括隧道氧化物层、浮置栅极、中间介电层、控制栅极和掩模层;在所述两个栅极堆叠件的侧壁上形成第一间隔件;在暴露的所述衬底上形成栅极介电层;在所述衬底之上依次形成多晶硅层和第一介电层,其中,所述多晶硅层的厚度小于所述隧道氧化物层、所述浮置栅极、所述中间介电层和所述控制栅极的总厚度;各向异性地蚀刻所述第一介电层和所述第一介电层下方的所述多晶硅层直到暴露出所述衬底,其中,蚀刻所述多晶硅层以在两个所述栅极堆叠件之间形成擦除栅极以及形成位于两个所述栅极堆叠件的外侧上的字线,以及蚀刻所述第一介电层以在所述字线和所述擦除栅极上形成第一覆盖层;在暴露的所述衬底上形成有机层;蚀刻暴露的所述字线和暴露的所述擦除栅极直到所述擦除栅极和所述字线的顶面低于所述控制栅极的顶面;去除所述有机层;在所述衬底之上形成第二介电层;以及各向异性地蚀刻所述第二介电层以在所述字线的外侧壁上形成第二间隔件并且在所述字线和所述擦除栅极上形成第二覆盖层。
在上述方法中,其中,每个所述第一间隔件均包括内部氧化硅层和外部氮化硅层。
在上述方法中,所述第一介电层和所述第二介电层均包括底部氧化硅层和顶部氮化硅层。
在上述方法中,其中,通过干蚀刻实施对暴露的所述字线和暴露的所述擦除栅极的蚀刻。
在上述方法中,其中,通过干蚀刻实施对暴露的所述字线和暴露的所述擦除栅极的蚀刻;其中,通过将SF6用作等离子体源在多晶硅蚀刻机中实施所述干蚀刻。
在上述方法中,其中,通过干蚀刻实施对暴露的所述字线和暴露的所述擦除栅极的蚀刻;其中,通过将CxHyFz和氧用作等离子体源在远程等离子体蚀刻机中实施所述干蚀刻,并且CxHyFz是CH2F2、CHF3、CF4、C2F6、C3F8、C4F6或C5F8。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或减小。
图1A至图1H是根据本发明的一些实施例的示出了嵌入式非易失性存储器的工艺的截面图。
图2A至图2D是根据本发明的一些其他实施例的示出了嵌入式非易失性存储器的工艺的截面图。
图3A至图3D是根据本发明的一些其他实施例的示出了嵌入式非易失性存储器的工艺的截面图。
图、图表和图解是说明性的且不旨在限制,而是本发明的实施例的实例,仅用于解释的目的,并且未按比例绘制。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为了便于描述,在此可以使用诸如“在…下方”、“在…下面”、“下”、“在…之上”、“上”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),并且在此使用的空间相对描述符可以同样地作出相应的解释。
将用于移动应用的先进的逻辑工艺与非易失性存储器工艺集成的一个问题是当金属硅化物在逻辑区的源极/漏极区上形成时在非易失性存储区中的字线和擦除栅极的顶部上形成金属硅化物导致的。化学机械抛光工艺之后,字线的顶部上的金属硅化物将在整个晶圆上方扩散并且由此产生短路和电流泄漏的问题。因此,本发明提供一种制造可以与用于移动应用的先进的逻辑工艺集成以解决上述问题的非易失性存储器的新方法。根据本发明的各个实施例,非易失性存储器可以是堆叠栅极存储器。
图1A至图1H是根据本发明的一些实施例的示出了嵌入式非易失性存储器的工艺的截面图。在图1A至图1H中,在图F中将回蚀刻在图1E中形成的非易失性存储器的字线122a和擦除栅极122b。因此,字线122a和擦除栅极122b的顶面不高于控制栅极108的顶面以避免在字线122a和擦除栅极122b的顶面上形成金属硅化物。
在图1A中,隧道(tunneling)氧化物层102和第一多晶硅层随后在衬底100上形成,衬底100具有形成在其中的隔离结构(未在图1A中示出)。然后图案化第一多晶硅层以形成与纸的表面平行的多个多晶硅条104。例如,上述隔离结构可以是浅沟槽隔离(STI)。例如,可以通过热氧化工艺形成隧道氧化物层102。可以通过化学汽相沉积以及然后通过光刻以及随后的干蚀刻来图案化第一多晶硅层以形成多个多晶硅条104。第一多晶硅可以具有至的厚度,诸如
接下来,在衬底100之上依次形成中间介电层106、第二多晶硅层和第一介电层以覆盖多个多晶硅条104和隧道氧化物层102。例如,中间介电层106可以包括底部氧化硅层、中间氮化硅层和顶部氧化硅层。例如,底部和顶部氧化硅层可以通过在800℃至1200℃的温度下的热氧化以及随后在1000℃的温度下退火来形成,并且可以具有的厚度。例如,中间氮化硅层可以通过低压化学汽相沉积(LPCVD)来形成,并且具有的厚度。第二多晶硅层可以通过化学汽相沉积来形成,并且具有至的厚度,诸如第一介电层可以由通过LPCVD沉积的氮化硅制成,并且具有至的厚度,诸如
然后,图案化第一介电层和第二多晶硅层以分别形成掩模层110和控制栅极108。可以通过光刻和随后的干蚀刻来实施图案化的方法。在第二多晶硅层的蚀刻期间,掩模层110用作蚀刻掩模。
在图1B中,在衬底100之上形成第二介电层以共形地覆盖掩模层110、控制栅极108和中间介电层106。接下来,各向异性地蚀刻第二介电层以在掩模层110和控制栅极108的侧壁上形成第一间隔件112。随后蚀刻位于其下方的暴露的中间介电层106、多晶硅条104和隧道氧化物层102以形成中间介电层106a、浮置栅极104a和隧道氧化物层102a从而形成衬底100上的栅极堆叠件114。第二介电层可以包括底部氧化硅层、中间氮化硅层和顶部氧化硅层。
在图1C中,随后在衬底100之上形成第一缓冲层116a和第三介电层以共形地覆盖栅极堆叠件114的暴露表面和暴露的衬底100。例如,第一缓冲层116a可以是通过化学汽相沉积形成的氧化硅层。例如,第三介电层可以是通过LPCVD形成的氮化硅层。然后各向异性地蚀刻第三介电层以在栅极堆叠件114的侧壁上形成第二间隔件118。可以通过干蚀刻实施各向异性蚀刻。
上述缓冲层116a通常用于释放当上述晶格失配明显时由第三介电层和暴露的硅层之间的晶格失配导致的应变。例如,暴露的硅层包括在图1C中的浮置栅极104a和衬底100。然而,如果第三介电层和暴露的硅层之间的晶格失配不明显而无法产生明显的应变,则可以省略缓冲层116a。
接下来,通过旋转涂覆、曝光和显影工艺的组合形成图案化的光刻胶层121以暴露衬底100的共源极区域。然后将离子注入至暴露的衬底100内以形成共源极120。随后,去除通过图案化的光刻胶层121暴露的第二间隔件118,并且可以通过例如干蚀刻或湿蚀刻实施去除方法。在暴露的第二间隔件118的去除期间,可以最终消耗缓冲层116a以暴露共源极120。
在图1D中,去除图案化的光刻胶层121并且例如可以通过溶剂剥离或等离子体灰化来实施去除方法。然后,形成栅极氧化物层116b以覆盖暴露的衬底,即共源极120。可以通过热氧化形成栅极氧化物层116b。
接下来,在衬底100之上依次形成第三多晶硅层122和第四介电层124。第三多晶硅层122的厚度小于隧道氧化物层102a、浮置栅极104a、中间介电层106a和控制栅极108的总厚度,诸如在从约至约的范围内。第四介电层124的厚度在从约至约的范围内。例如,第四介电层124可以由氧化硅制成并且通过LPCVD形成。
在图1E中,各向异性地蚀刻第四介电层124以在字线122a上形成第一侧覆盖层124a以及在擦除栅极122b上形成第一中间覆盖层124b,并且蚀刻停止在第三多晶硅层122上。随后,各向异性地蚀刻第三多晶硅层122以形成紧挨着第二间隔件118的字线122a和共源极120之上的擦除栅极122b,并且蚀刻停止在第一缓冲层116a上。上述各向异性蚀刻可以通过干蚀刻来实施。
需要注意的是,由于第一缓冲层116a很薄,并且因此在第三多晶硅层122的蚀刻期间可以容易地蚀刻掉第一缓冲层116a的暴露的部分以暴露其下方的衬底100。因此,可以在衬底100之上旋涂有机材料以形成覆盖衬底100的暴露顶面的有机层126,以保护暴露的衬底100。同时,由于蚀刻后的字线122a和擦除栅极122b的暴露顶面以具有凹形顶面,因此可以在字线122a和擦除栅极122b的顶面上旋涂有机材料。此外,覆盖衬底100的有机层126的厚度大于覆盖字线122a和擦除栅极122b的有机层126的厚度以提供对衬底100的更好的保护。上述有机材料可以是可被旋涂以在随后的字线122a和擦除栅极122b的蚀刻期间保护暴露的衬底100的光刻胶或其他有机聚合物。
在图1F中,蚀刻有机层126以暴露字线122a和擦除栅极122b的顶面,但是衬底100的顶面仍由有机层126覆盖。接下来,通过各向同性干蚀刻选择性地回蚀刻暴露的字线122a和暴露的擦除栅极122b以避免损坏由氮化硅制成的第二间隔件118、第一侧覆盖层124a和第一中间覆盖层124b。因此,字线122a和擦除栅极122b的顶面的水平面降低。然后,例如,通过溶剂剥离去除衬底100上的剩余的有机层126。
根据一些实施例,可以通过电感耦合等离子体(IPC)多晶硅蚀刻机(poly etcher)实施上述各向同性干蚀刻。蚀刻等离子体的源可以包括5至50sccm的SF6和100至600sccm的载气的混合物,并且载气可以是Ar或He。反应室的压力可以增加至3至50毫托,并且ICP功率可以增加至200至600瓦。此外,偏置电压可以降低至0至100伏。由于SF6用作蚀刻等离子体的源,因此干蚀刻可以是各向同性的。
根据一些其他实施例,可以通过化学干蚀刻机实施上述干蚀刻。化学干蚀刻机配备有远程等离子体源以将生成的等离子体的动能降低为近乎零。因此,可以实施各向同性蚀刻以降低由高动能等离子体导致的损坏。在化学干蚀刻(CDE)工艺中,等离子的源可以包括CxHyFz和氧气的混合物。混合气体的总流速可以是300至800sccm,并且CxHyFz与氧气的流速比率可以是0.5至1.5。CxHyFz可以是CH2F2、CHF3、CF4、C2F6、C3F8、C4F6或C5F8。反应室的压力可以是200至500豪托。硅相对于氮化硅的蚀刻选择性为约3至10,并且因此有效地降低第二间隔件118、第一侧覆盖层124a和第一中间覆盖层124b的损坏。
在图1G中,随后在衬底100之上形成第二缓冲层128和第五介电层以覆盖衬底100上的结构。然后各向异性地蚀刻第五介电层以在字线122a的侧壁上形成第三间隔件130a、在字线122a的顶面上形成第二侧覆盖层130b、以及在擦除栅极122b上形成第二中间覆盖层130c。同时,在第五介电层的蚀刻期间也蚀刻掉暴露的第二缓冲层128,由于第二缓冲层128是薄的。第二缓冲层128可以是通过CVD形成的氧化硅层。第五介电层可以是通过LPCVD形成的氮化硅层。例如,可以通过干蚀刻实施各向异性蚀刻。类似地,当第五介电层和暴露的硅层之间的晶格失配不明显而无法产生明显的应变时,可以省略第二缓冲层128。
随后,实施自对准硅化(自对准硅化物)工艺以在非易失性存储区和逻辑区上的硅材料的暴露表面上形成金属硅化物。因此,金属硅化物可以在衬底100和其他多晶硅层的暴露表面上形成。请注意,由于字线122a和擦除栅极122b的暴露的表面已经被第二缓冲层128、第一侧覆盖层124a、第一中间覆盖层124b、第三间隔件130a、第二侧覆盖层130b和第二中间覆盖层130c覆盖,因此在字线122a和擦除栅极122b的顶面上未形成金属硅化物。在非易失性存储区,可以仅在衬底100的暴露的表面上形成金属硅化物层132以用作漏极。
在图1H中,在衬底100之上形成蚀刻停止层134以共形地覆盖衬底100上的结构。例如,蚀刻停止层134的材料可以是通过LPCVD形成的氮化硅。然后,在衬底100之上形成低k介电层136以覆盖形成在衬底100上的结构。随后实施化学机械抛光(CMP)的工艺以抛光整个晶圆以去除低k介电层136的上部,并且CMP停止在掩模层110上。因此,掩模层110的厚度进一步降低。
低k介电层136的材料可以由具有介电常数比二氧化硅(即,低k介电材料)的介电常数更小的介电材料制成。常见的低k介电材料包括氟掺杂的二氧化硅、碳掺杂的二氧化硅、多孔二氧化硅、碳掺杂的多孔二氧化硅、自旋有机聚合物电介质(诸如聚酰亚胺、聚降冰片烯、苯并环丁烯或聚四氟乙烯)、自旋硅树脂基高分子电介质(诸如氢倍半硅氧烷和甲基倍硅氧烷)。
图2A至图2D是根据本发明的一些其他实施例的示出了嵌入式非易失性存储器的工艺的截面图。由于在图2A之前的工艺类似于图1A至图1C,因此在此省略了图和详细的描述。此外,通过将至图1C中的参考标号增加100而获得表示相同或类似组件的图2A中的参考标号,并且因此不重复描述表示相同或类似组件的图2A中的参考标号的意思。在图2A至图2D中,在图1D中的第三多晶硅层122和第四介电层124仅被图2A中的第三多晶硅层222替代,并且蚀刻第三多晶硅层222以形成具有顶面不高于图2B中的控制栅极208的顶面的字线222a和擦除栅极222b以避免在字线222a和擦除栅极222b的顶面上形成金属硅化物。以下描述图2A至图2D的详细描述。
在去除图1C中的光刻胶层121之后,然后去除图2A中的暴露的第一缓冲层216a。例如,暴露的第一缓冲层216a的去除方法可以是湿蚀刻。生长栅极氧化物层216b以覆盖衬底200、浮置栅极204a和共源极220的暴露的表面。可以通过热氧化实施栅极氧化物层216b的形成方法。接下来,形成第三多晶硅层222以覆盖衬底200,并且第三多晶硅层222的厚度大于栅极堆叠件214的总厚度。根据一些实施例,第三多晶硅层的厚度在从约至约的范围内。
在图2B中,各向异性地蚀刻第三多晶硅层222直到暴露衬底200以形成字线222a和擦除栅极222b。然后,随后在衬底200之上形成第二缓冲层224和第四介电层。各向异性地蚀刻第四介电层以在字线222a上形成侧覆盖层226a以及在擦除栅极222b上形成第一中间覆盖层226b,并且在第四介电层的蚀刻期间消耗掉暴露的第二缓冲层224。接下来,通过使用侧覆盖层226a作为蚀刻掩模进一步蚀刻暴露的字线222a以修改字线222a的轮廓。至于擦除栅极222b,因为第四介电层比擦除栅极222b厚,因此在字线222a的回蚀刻期间最终不蚀刻擦除栅极222b。
在图2C中,随后在衬底200之上形成第三缓冲层228和第五介电层。各向异性地蚀刻第五介电层以在字线222a的侧壁上形成第三间隔件230a以及在擦除栅极222b上形成第二中间覆盖层230b。在第五介电层的蚀刻期间消耗掉暴露的第三缓冲层228。第三缓冲层228可以是通过CVD形成的氧化硅层。第五介电层可以是通过LPCVD形成的氮化硅层。类似地,如果第五介电层和暴露的硅层之间的压力不是很大,则可以省略第三缓冲层228。
然后,实施自对准硅化(自对准硅化物)工艺以在非易失性存储区和逻辑区上的硅材料的暴露的表面上形成金属硅化物。因此,衬底200和其他多晶硅层的暴露的表面上将具有形成在其上的金属硅化物232。请注意,由于字线222a和擦除栅极222b的顶面没有暴露,因此在字线222a和擦除栅极222b的顶部上未形成金属硅化物。
在图2D中,在衬底200之上形成蚀刻停止层234以共形地覆盖衬底200上的结构。例如,蚀刻停止层234的材料可以是氮化硅。然后,在衬底200之上形成低k介电层236以覆盖形成在衬底200上的结构。随后实施化学机械抛光(CMP)的工艺以抛光整个晶圆以去除低k介电层236的上部,并且CMP停止在掩模层210上。因此,掩模层210的厚度进一步降低。低k介电层236的材料类似于低k介电层136的材料,因此在此省略。
图3A至图3D是根据本发明的一些其他实施例的示出了嵌入式非易失性存储器的工艺的截面图。由于在图3A之前的工艺类似于图1A至图1C,因此在此省略了图和详细的描述。此外,通过将图1C中的参考标号增加200而获得表示相同或类似组件的图3A中的参考标号,并且因此不重复描述表示相同或类似组件的图3A中的参考标号的意思。在图3A至图3D中,图2A中的第三多晶硅层222被图3A中的第三多晶硅层322和有机层324替代。因此,非选择性地回蚀刻有机层324和第三多晶硅层322,以使得第三多晶硅层具有不高于图3B中的控制栅极308的顶面的顶面。因此可以避免金属硅化物形成在字线322a和擦除栅极322b的顶面上。以下描述图3A至图3D的详细描述。
在去除图1C中的光刻胶层121之后,然后去除图3A中的暴露的第一缓冲层316a。例如,暴露的第一缓冲层316a的去除方法可以是湿蚀刻。生长栅极氧化物层316b以覆盖衬底300、浮置栅极304a和共源极320的暴露的表面。可以通过热氧化实施栅极氧化物层316b的形成方法。接下来,形成第三多晶硅层322和有机层324以覆盖衬底300。第三多晶硅层322的厚度小于隧道氧化物层302a、浮置栅极304a、中间介电层306a和控制栅极308的总厚度,诸如在从约至约的范围内。有机层的顶面高于栅极堆叠件314的顶面。因此根据一些实施例,有机层324的厚度可以在从约至约的范围内。
在图3B中,非选择性地蚀刻第三多晶硅层322和有机层324直到第三多晶硅层的顶面低于控制栅极308的顶面。根据一些实施例,剩余的第三多晶硅层322的厚度在从约至约的范围内。在该步骤中,形成擦除栅极322b。然后,去除有机层324的残留物,并且可以通过等离子体灰化实施去除。
接下来,在衬底320之上依次形成第二缓冲层326和第四介电层。各向异性地蚀刻第四介电层以在字线322a上形成侧覆盖层328a以及在擦除栅极322b上形成第一中间覆盖层328b,并且在第四介电层的蚀刻期间消耗掉一些暴露的第二缓冲层326。接下来,通过使用侧覆盖层328a作为蚀刻掩模进一步蚀刻暴露的第三多晶硅层322以形成字线322a。第二缓冲层326可以是通过CVD形成的氧化硅层。第四介电层可以是通过LPCVD形成的氮化硅层。类似地,当第四介电层和暴露的硅层之间的应变不是很大时,可以省略第二缓冲层326。
在图3C中,在衬底300之上依次形成第三缓冲层330和第五介电层。各向异性地蚀刻第五介电层以在字线322a的侧壁上形成第三间隔件332a以及在擦除栅极322b上形成第二中间覆盖层332b。在第五介电层的蚀刻期间消耗掉暴露的第三缓冲层330。第三缓冲层330可以是通过CVD形成的氧化硅层。第五介电层可以是通过LPCVD形成的氮化硅层。类似地,当第五介电层和暴露的硅层之间的应变不是很大时,可以省略第三缓冲层330。
然后,实施自对准硅化(自对准硅化物)工艺以在非易失性存储区和逻辑区上的硅材料的暴露的表面上形成金属硅化物。因此,衬底300和其他多晶硅层的暴露的表面上将具有形成在其上的金属硅化物334。请注意,由于字线322a和擦除栅极322b的顶面没有暴露,因此在字线322a和擦除栅极322b的顶部上未形成金属硅化物。
在图3D中,在衬底300之上形成蚀刻停止层336以共形地覆盖衬底300上的结构。例如,蚀刻停止层336的材料可以是氮化硅。然后,在衬底300之上形成低k介电层338以覆盖形成在衬底300上的结构。随后实施化学机械抛光(CMP)的工艺以抛光整个晶圆以去除低k介电层338的上部,并且CMP停止在掩模层310上。因此,掩模层310的厚度进一步降低。低k介电层338的材料类似于低k介电层136的材料,因此在此省略。
因此,本发明提供了降低字线和擦除栅极的顶面的三种不同的方法,因此字线和擦除栅极的顶面可以低于控制栅极的顶面。此外,介电覆盖层在字线和擦除栅极的顶面上形成,并且介电间隔件形成在字线的侧壁上。因此当在非易失性存储区和28HPM逻辑区上实施自对准硅化工艺时,不暴露字线和擦除栅极的表面,并且在字线和擦除栅极上未形成金属硅化物。随后,在CMP工艺中,没有金属硅化物扩散出以产生电流泄漏和短路的问题。
根据本发明的一些实施例,提供了一种非易失性存储器,并且非易失性存储器包括以下组件。至少两个栅极堆叠件位于衬底上,其中每个栅极堆叠件从底部到顶部均依次包括隧道氧化物层、浮置栅极、中间介电层、控制栅极和掩模层。第一间隔件位于两个栅极堆叠件的侧壁上。栅极介电层位于暴露的衬底上。擦除栅极位于两个栅极堆叠件之间并且具有不高于控制栅极的顶面的非平坦顶面。两条字线位于两个栅极堆叠件的外侧上并且具有不高于控制栅极的顶面的非平坦顶面。覆盖层分别位于擦除栅极和字线上。
根据本发明的一些其他实施例,提供了一种形成非易失性存储器的方法。在衬底上形成两个栅极堆叠件,其中每个栅极堆叠件从底部到顶部均依次包括隧道氧化物层、浮置栅极、中间介电层、控制栅极和掩模层。在两个栅极堆叠件的侧壁上形成第一间隔件。在暴露的衬底上形成栅极介电层。同时形成位于两个栅极堆叠件之间的擦除栅极和位于两个栅极堆叠件的外侧上的两条字线,其中擦除栅极和两条字线的顶面不高于控制栅极的顶面。在擦除栅极和字线的顶面上分别形成复合覆盖层。
根据本发明的一些其他实施例,提供了一种形成非易失性存储器的方法。在衬底上形成两个栅极堆叠件,其中每个栅极堆叠件从底部到顶部均依次包括隧道氧化物层、浮置栅极、中间介电层、控制栅极和掩模层。在两个栅极堆叠件的侧壁上形成第一间隔件。在暴露的衬底上形成栅极介电层。在衬底之上依次形成多晶硅层和有机层,其中多晶硅层的厚度小于隧道氧化物层、浮置栅极、中间介电层和控制栅极的总厚度,以及有机层的顶面高于栅极堆叠件的顶面。非选择性蚀刻有机层和多晶硅层直到多晶硅层的顶面不高于控制栅极的顶面。去除有机层的残留物。在衬底之上形成第一介电层。各向异性地蚀刻第一介电层和其下方的多晶硅层直到暴露出衬底。蚀刻多晶硅层以在两个栅极堆叠件之间形成擦除栅极以及形成位于两个栅极堆叠件的外侧上的字线,以及蚀刻第一介电层以在字线和擦除栅极上形成第一覆盖层。
根据本发明的一些其他实施例,提供了一种形成非易失性存储器的方法。在衬底上形成两个栅极堆叠件,其中每个栅极堆叠件从底部到顶部均依次包括隧道氧化物层、浮置栅极、中间介电层、控制栅极和掩模层。在两个栅极堆叠件的侧壁上形成第一间隔件。在暴露的衬底上形成栅极介电层。在衬底之上依次形成多晶硅层和第一介电层,其中多晶硅层的厚度小于隧道氧化物层、浮置栅极、中间介电层和控制栅极的总厚度。各向异性地蚀刻第一介电层和其下方的多晶硅层直到暴露出衬底。蚀刻多晶硅层以在两个栅极堆叠件之间形成擦除栅极以及形成位于两个栅极堆叠件的外侧上的字线,以及蚀刻第一介电层以在字线和擦除栅极上形成第一覆盖层。在暴露的衬底上形成有机层。蚀刻暴露的字线和暴露的擦除栅极直到擦除栅极和字线的顶面低于控制栅极的顶面。去除有机层。在衬底之上形成第二介电层。各向异性地蚀刻第二介电层以在字线的外侧壁上形成第二间隔件并且在字线和擦除栅极上形成第二覆盖层。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (10)
1.一种非易失性存储器,包括:
至少两个栅极堆叠件,位于衬底上,其中,每个所述栅极堆叠件均从底部到顶部依次包括隧道氧化物层、浮置栅极、中间介电层、控制栅极和掩模层;
第一间隔件,位于所述两个栅极堆叠件的侧壁上;
栅极介电层,位于暴露的所述衬底上;
擦除栅极,位于两个所述栅极堆叠件之间并且具有不高于所述控制栅极的顶面的非平坦顶面;
两条字线,位于两个所述栅极堆叠件的外侧上并且具有不高于所述控制栅极的顶面的非平坦顶面;以及
覆盖层,分别位于所述擦除栅极和所述字线上。
2.根据权利要求1所述的非易失性存储器,其中,所述字线的顶面是U形。
3.根据权利要求1所述的非易失性存储器,其中,所述擦除栅极和所述字线由多晶硅制成。
4.根据权利要求1所述的非易失性存储器,其中,所述第一间隔件和所述覆盖层均包括内部氧化硅层和外部氮化硅层。
5.根据权利要求1所述的非易失性存储器,还包括位于所述字线的外侧壁上的第二间隔件。
6.根据权利要求5所述的非易失性存储器,其中,每个所述第二间隔件均包括内部氧化硅层和外部氮化硅层。
7.一种形成非易失性存储器的方法,所述方法包括:
在衬底上形成两个栅极堆叠件,其中,每个所述栅极堆叠件均从底部到顶部依次包括隧道氧化物层、浮置栅极、中间介电层、控制栅极和掩模层;
在所述两个栅极堆叠件的侧壁上形成第一间隔件;
在暴露的所述衬底上形成栅极介电层;
形成位于所述两个栅极堆叠件之间的擦除栅极和位于所述两个栅极堆叠件的外侧上的两条字线,其中,所述擦除栅极和两条所述字线的顶面不高于所述控制栅极的顶面;
在所述擦除栅极和所述字线的顶面上分别形成复合覆盖层。
8.根据权利要求7所述的方法,其中,所述擦除栅极和所述字线的形成包括:
形成具有厚度大于所述栅极堆叠件的厚度的多晶硅层;
各向异性地蚀刻所述多晶硅层直到暴露出所述衬底以形成所述擦除栅极和所述字线。
9.一种形成非易失性存储器的方法,所述方法包括:
在衬底上形成两个栅极堆叠件,其中,每个所述栅极堆叠件均从底部到顶部依次包括隧道氧化物层、浮置栅极、中间介电层、控制栅极和掩模层;
在所述两个栅极堆叠件的侧壁上形成第一间隔件;
在暴露的所述衬底上形成栅极介电层;
在所述衬底之上依次形成多晶硅层和有机层,其中,所述多晶硅层的厚度小于所述隧道氧化物层、所述浮置栅极、所述中间介电层和所述控制栅极的总厚度,以及所述有机层的顶面高于所述栅极堆叠件的顶面;
蚀刻所述有机层和所述多晶硅层直到所述多晶硅层的顶面不高于所述控制栅极的顶面;
去除所述有机层的残留物;
在所述衬底之上形成第一介电层;以及
各向异性地蚀刻所述第一介电层和所述第一介电层下方的所述多晶硅层直到暴露出所述衬底,其中,蚀刻所述多晶硅层以在两个所述栅极堆叠件之间形成擦除栅极以及形成位于所述两个栅极堆叠件的外侧上的字线,以及蚀刻所述第一介电层以在所述字线和所述擦除栅极上形成第一覆盖层。
10.一种形成非易失性存储器的方法,所述方法包括:
在衬底上形成两个栅极堆叠件,其中,每个所述栅极堆叠件均从底部到顶部依次包括隧道氧化物层、浮置栅极、中间介电层、控制栅极和掩模层;
在所述两个栅极堆叠件的侧壁上形成第一间隔件;
在暴露的所述衬底上形成栅极介电层;
在所述衬底之上依次形成多晶硅层和第一介电层,其中,所述多晶硅层的厚度小于所述隧道氧化物层、所述浮置栅极、所述中间介电层和所述控制栅极的总厚度;
各向异性地蚀刻所述第一介电层和所述第一介电层下方的所述多晶硅层直到暴露出所述衬底,其中,蚀刻所述多晶硅层以在两个所述栅极堆叠件之间形成擦除栅极以及形成位于两个所述栅极堆叠件的外侧上的字线,以及蚀刻所述第一介电层以在所述字线和所述擦除栅极上形成第一覆盖层;
在暴露的所述衬底上形成有机层;
蚀刻暴露的所述字线和暴露的所述擦除栅极直到所述擦除栅极和所述字线的顶面低于所述控制栅极的顶面;
去除所述有机层;
在所述衬底之上形成第二介电层;以及
各向异性地蚀刻所述第二介电层以在所述字线的外侧壁上形成第二间隔件并且在所述字线和所述擦除栅极上形成第二覆盖层。
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