CN104950246A - Hardware trojan detection method and system based on time delay - Google Patents

Abstract

The invention discloses a hardware trojan detection method and system based on time delay. The method comprises the following steps of firstly obtaining bypass time delay information of a chip to be detected, wherein the bypass time delay information includes an amplitude frequency response curve and/or a phase frequency response curve of each signal path of the chip to be detected; obtaining the resonance valley frequency and the resonance peak frequency of each signal path in the chip to be detected according to the bypass time delay information; finally and respectively comparing the resonance valley frequency and the resonance peak frequency of each signal path in the chip to be detected with the corresponding preset resonance valley frequency threshold and the resonance peak frequency threshold of each signal path; judging whether hardware Trojan exists in the chip to be detected or not according to the comparison result. The addition of the additional chip area for test is not needed, the workload and the test cost are greatly reduced, and the work efficiency is improved.

Description

Based on hardware Trojan horse detection method and the system of time delay

Technical field

The present invention relates to integrated circuit detection technique field, particularly relate to a kind of hardware Trojan horse detection method based on time delay and system.

Background technology

Along with the development of semiconductor technology, hardware outsourcing design and flow become the trend of globalization, have occurred a kind of New Hardware attack pattern for integrated circuit (IC) chip in recent years, have been called " hardware Trojan horse ".Hardware Trojan horse mainly refers to that malice is added some illegal circuit or distorts original design file artificially in IC (integrated circuit, integrated circuit) Design and manufacture process, thus leaves " time bomb " or " electronics back door " etc.

Existing hardware Trojan horse detection method mainly judges whether there is wooden horse in chip by the by-passing signal detected in analysis circuit, as maximum operation frequency, time delay, power consumption, static state and dynamic current, electromagnetism and thermal effect etc., come whether there is wooden horse in decision circuitry.But traditional hardware Trojan horse based on by-passing signal analysis detects to be needed to characterize the time-delay characteristics of chip at integrated circuit critical path insertion shadow register or ring oscillator or carry out scanning monitoring to the clock of critical path, when integrated circuit has the path of more than 1,000,000, hardware Trojan horse not necessarily colonizes among critical path, therefore shadow register or ring oscillator are inserted to critical path or carry out clock scan monitoring and differ and detect hardware Trojan horse surely, if increase the detection to non-critical path, then need to increase extra chip area to test, greatly can increase workload and testing cost.

Summary of the invention

Based on above-mentioned situation, the present invention proposes a kind of hardware Trojan horse detection method based on time delay and system, reduce workload and testing cost, improve testing efficiency.

To achieve these goals, the embodiment of technical solution of the present invention is:

Based on a hardware Trojan horse detection method for time delay, comprise the following steps:

Obtain the bypass delayed data of chip to be measured, described bypass delayed data comprises amplitude-frequency response and/or the phase-frequency response curve of each signal path of described chip to be measured;

Resonance paddy frequency and the harmonic peak frequency of each signal path in described chip to be measured is obtained according to described bypass delayed data;

The resonance paddy frequency of each signal path in described chip to be measured and harmonic peak frequency are compared with the default resonance paddy frequency threshold of each corresponding signal path and harmonic peak frequency threshold respectively, judges whether there is hardware Trojan horse in described chip to be measured according to comparative result.

The embodiment of technical solution of the present invention is:

Based on a hardware Trojan horse detection system for time delay, comprising:

Acquisition module, for obtaining the bypass delayed data of chip to be measured, described bypass delayed data comprises amplitude-frequency response and/or the phase-frequency response curve of each signal path of described chip to be measured;

Processing module, for obtaining resonance paddy frequency and the harmonic peak frequency of each signal path of described chip to be measured according to described bypass delayed data;

Detection module, for the resonance paddy frequency of each signal path in described chip to be measured and harmonic peak frequency being compared with the default resonance paddy frequency threshold of each corresponding signal path and harmonic peak frequency threshold respectively, judge whether there is hardware Trojan horse in described chip to be measured according to comparative result.

Compared with prior art, beneficial effect of the present invention is: the hardware Trojan horse detection method and the system that the present invention is based on time delay, resonance paddy frequency and the harmonic peak frequency of each signal path in chip to be measured is obtained according to the bypass delayed data of the chip to be measured obtained, the resonance paddy frequency of each signal path and harmonic peak frequency are compared with the default resonance paddy frequency threshold of each corresponding signal path and harmonic peak frequency threshold respectively, judge whether there is hardware Trojan horse in chip to be measured according to comparative result, extra chip area need not be increased test, greatly reduce workload and testing cost, be of very high actual application value.

Accompanying drawing explanation

Fig. 1 is the hardware Trojan horse detection method process flow diagram based on time delay in an embodiment;

Fig. 2 is the theory diagram based on the sweep check of clock network path in an embodiment;

Fig. 3 is the equivalent physical model figure that the annexation between Fig. 2 clock CLK1 pin and CLK2 pin is abstract;

Fig. 4 is the hardware Trojan horse testing result schematic diagram of wooden horse chip and non-wooden horse chip in an embodiment;

Fig. 5 is for based on the hardware Trojan horse detection method process flow diagram based on time delay in the concrete example of method one shown in Fig. 1;

Fig. 6 is the hardware Trojan horse detection system structural representation based on time delay in an embodiment.

Embodiment

For making object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is described in further detail.Should be appreciated that embodiment described herein only in order to explain the present invention, do not limit protection scope of the present invention.

Based on the hardware Trojan horse detection method of time delay in an embodiment, as shown in Figure 1, comprise the following steps:

Step S101: the bypass delayed data obtaining chip to be measured, described bypass delayed data comprises amplitude-frequency response and/or the phase-frequency response curve of each signal path of described chip to be measured;

Step S102: the resonance paddy frequency and the harmonic peak frequency that obtain each signal path in described chip to be measured according to described bypass delayed data;

Step S103: the resonance paddy frequency of each signal path in described chip to be measured and harmonic peak frequency are compared with the default resonance paddy frequency threshold of each corresponding signal path and harmonic peak frequency threshold respectively, judges whether there is hardware Trojan horse in described chip to be measured according to comparative result.

Known from the above description, the present invention is based on the hardware Trojan horse detection method of time delay, by determining resonance paddy frequency and the harmonic peak frequency of each signal path in chip to be measured to the bypass delayed data of the chip to be measured obtained, whether hardware Trojan horse is there is according in the resonance paddy frequency of each signal path and harmonic peak frequency detecting chip to be measured, test without the need to increasing extra chip area, reduce test job amount and testing cost, improve testing efficiency, have very high actual application value.

As an embodiment, the resonance paddy frequency of each signal path in described chip to be measured and harmonic peak frequency are compared with the default resonance paddy frequency threshold of each corresponding signal path and harmonic peak frequency threshold respectively, judge that the step that whether there is hardware Trojan horse in described chip to be measured comprises according to comparative result:

Relational matrix is obtained according to the resonance paddy frequency of each signal path in described chip to be measured and harmonic peak frequency:

$G=\left[\begin{array}{cccccc}{g}_{11}& g_{12}& \·& \·& \·& g_{1n}\\ g_{21}& g_{22}& \·& \·& \·& g_{2n}\\ \·& \·& & \·& & \·\\ \·& \·& & \·& & \·\\ \·& \·& & \·& & \·\\ g_{m1}& g_{m2}& \·& \·& \·& g_{\mathrm{mn}}\end{array}\right],$ Wherein m represents total number of input signal in described chip to be measured, and n represents the total number outputed signal in described chip to be measured, wherein f _xy2represent the resonance paddy frequency of signal path, f _xy1represent the harmonic peak frequency of signal path;

The parameter that parameter in described relational matrix G is corresponding with preset relation matrix G ' compares, and judges whether there is hardware Trojan horse in described chip to be measured, wherein according to comparative result $G^{\′}=\left[\begin{array}{cccccc}{g}_{11}^{\′}& g_{12}^{\′}& \·& \·& \·& g_{1n}^{\′}\\ g_{21}^{\′}& g_{22}^{\′}& \·& \·& \·& g_{2n}^{\′}\\ \·& \·& & \·& & \·\\ \·& \·& & \·& & \·\\ \·& \·& & \·& & \·\\ g_{m1}^{\′}& g_{m2}^{\′}& \·& \·& \·& h_{\mathrm{mn}}^{\′}\end{array}\right],g_{\mathrm{xy}}^{\′}=\frac{f_{\mathrm{xy}2}^{\′2}}{f_{\mathrm{xy}1}^{\′2}},$ F ' _xy2represent the default resonance paddy frequency threshold of signal path, f ' _xy1represent the default harmonic peak frequency threshold of signal path, wherein x=1,2 ..., m, y=1,2 ..., n;

As shown in Figure 2 in an embodiment based on the theory diagram of clock network path sweep check, the abstract equivalent physical model of annexation wherein between clock CLK1 pin and CLK2 pin as shown in Figure 3, wherein, R, L are respectively parasitic lumped resistance and the inductance of interconnection line between clock network CLK1 pin and CLK2 pin, C ₁be the parasitic lumped capacitance between two pins, C ₂for the load capacitance of clock pins CLK2 and the summation of stray capacitance over the ground, V _infor the swept frequency excitation voltage signal of CLK1 input, V _outfor the response signal that CLK2 exports, the mathematical transfer function of this circuit model can be obtained from frequency domain:

$G\left(s\right)=\frac{V_{\mathrm{out}}\left(s\right)}{V_{\mathrm{in}}\left(s\right)}=\frac{1+\mathrm{sR}{C}_1+s^{2}L{C}_1}{1+\mathrm{sR}(C_1+C_2)+s^{2}L(C_1+C_2)},$

G (s) can see a second order band as and lead to the superposition with rejection filter, wherein passband central frequency (harmonic peak frequency) quality factor stopband center frequency (resonance paddy frequency) $f_2=\frac{1}{2\mathrm{\π}}\sqrt{\frac{1}{L{C}_1}},$ Quality factor $Q_2=\sqrt{\frac{L}{R^2{C}_1}},$ Obtain further $g=\frac{f_2^2}{f_1^2}=\frac{Q_2^2}{Q_1^2}=1+\frac{C_2}{C_1};$ Consider technological fluctuation, i-th g value without hardware Trojan horse chip is: wherein, Δ C _{i, 1}with Δ C _{i, 2}for the electric capacity Small variables that different chip technology fluctuation is introduced, during consideration technological fluctuation, g value becomes large; Consider that there is hardware Trojan horse in chip can produce extra parasitic load capacitance C _t, the g value of a jth hardware Trojan horse chip is: when there is hardware Trojan horse in chip, g value becomes large further; Visible have the g value of hardware Trojan horse chip to be greater than g value without hardware Trojan horse chip, C _tlarger, then distinguish more obvious, resolution is higher, and these characteristics may be embodied in or relation curve in, have hardware Trojan horse chip owing to producing extra parasitic load capacitance C _t, resonance frequency diminishes, and quality factor diminishes, and therefore, path delay characteristic can be reflected by spectral response (amplitude-frequency response and/or phase-frequency response curve), can carry out the detection analysis of hardware Trojan horse according to this characteristic; Can predetermined threshold value g ' according to above-mentioned analysis, when the g value of chip to be measured is greater than predetermined threshold value g ', judge to there is hardware Trojan horse in chip, when the g value of chip to be measured is less than predetermined threshold value g ', judge in chip without hardware Trojan horse;

Consider in complex chip there is m input signal, n output signal, then can obtain relational matrix according to above-mentioned analysis $G=\left[\begin{array}{cccccc}{g}_{11}& g_{12}& \·& \·& \·& g_{1n}\\ g_{21}& g_{22}& \·& \·& \·& g_{2n}\\ \·& \·& & \·& & \·\\ \·& \·& & \·& & \·\\ \·& \·& & \·& & \·\\ g_{m1}& g_{m2}& \·& \·& \·& g_{\mathrm{mn}}\end{array}\right],$ By the parameter g in matrix G _xywith corresponding predetermined threshold value g ' _xycompare, work as g _xybe greater than g ' _xytime, judge to there is hardware Trojan horse in chip, simple, accurate, be applicable to application;

The hardware Trojan horse testing result of wooden horse chip and non-wooden horse chip in an embodiment as shown in Figure 4, wherein the hardware Trojan horse circuit area of wooden horse chip and the ratio of original chip circuit area are 0.1%, carry out clock network sweep check obtain amplitude-frequency response to this wooden horse chip and non-wooden horse chip; Resonance paddy frequency and the harmonic peak frequency of each clock signal in wooden horse chip and non-wooden horse chip is obtained according to amplitude-frequency response; Obtain respective relational matrix according to the resonance paddy frequency of each clock signal in wooden horse chip and non-wooden horse chip and harmonic peak frequency and map, wooden horse chip and non-wooden horse chip can separate completely, dotted line is their boundary line, verifies the correctness of above-mentioned analysis.

As an embodiment, after judge whether there is hardware Trojan horse in described chip to be measured according to comparative result, also comprise step:

When judging to there is hardware Trojan horse in described chip to be measured, locate the path of described hardware Trojan horse according to the parameter in described relational matrix G;

Work as g _xybe greater than corresponding predetermined threshold value g ' _xytime, judge to there is hardware Trojan horse, g in chip to be measured _xyrepresent that in chip to be measured, an xth input signal exists hardware Trojan horse to the signal path that y outputs signal, path orientation greatly can improve the efficiency of subsequent physical positioning analysis, reduces workload and testing cost.

As an embodiment, after obtaining relational matrix G according to the resonance paddy frequency of each signal path in described chip to be measured and harmonic peak frequency, before being compared by the parameter that parameter in described relational matrix G is corresponding with preset relation matrix G ', also comprise step:

Feature extraction is carried out to described relational matrix G and described preset relation matrix G ';

Carry out feature extraction, remove the common mode information between relational matrix G and preset relation matrix G ', amplify the differential mode information between them, improve feature accuracy of identification.

As an embodiment, described signal path comprises clock network path or electric power network path, each chip has multiple clock network or electric power network, and the hardware Trojan horse of sequential type or incorporating aspects type is directly or indirectly connected with clock network or electric power network, therefore the existence of hardware Trojan horse will inevitably bring impact to clock network path or electric power network path delay, can carry out the detection analysis of hardware Trojan horse according to this characteristic; Above-mentioned signal path can also comprise other signal network path except clock network path and electric power network path.

In order to understand this method better, below elaborate a hardware Trojan horse detection method application example, this application example is applied to clock network path.

As shown in Figure 5, this application example can comprise the following steps:

Step S501: the amplitude-frequency response being obtained the clock network path of chip to be measured by sinusoidal wave sweep check;

Step S502: the resonance paddy frequency and the harmonic peak frequency that obtain each signal path in chip to be measured according to the amplitude-frequency response in the clock network path of the chip to be measured of above-mentioned acquisition;

Step S503: obtain relational matrix according to the resonance paddy frequency of each signal path in above-mentioned chip to be measured and harmonic peak frequency:

$G=\left[\begin{array}{cccccc}{g}_{11}& g_{12}& \·& \·& \·& g_{1n}\\ g_{21}& g_{22}& \·& \·& \·& g_{2n}\\ \·& \·& & \·& & \·\\ \·& \·& & \·& & \·\\ \·& \·& & \·& & \·\\ g_{m1}& g_{m2}& \·& \·& \·& g_{\mathrm{mn}}\end{array}\right],$ Wherein m represents total number of input signal in chip to be measured, and n represents in chip to be measured the total number outputed signal, wherein f _xy2represent the resonance paddy frequency of signal path, f _xy1represent the harmonic peak frequency of signal path, wherein x=1,2 ..., m, y=1,2 ..., n;

Step S504: adopt statistical study or mode identification method to carry out feature extraction to above-mentioned relation matrix G and preset relation matrix G ', wherein preset relation matrix $G^{\′}=\left[\begin{array}{cccccc}{g}_{11}^{\′}& g_{12}^{\′}& \·& \·& \·& g_{1n}^{\′}\\ g_{21}^{\′}& g_{22}^{\′}& \·& \·& \·& g_{2n}^{\′}\\ \·& \·& & \·& & \·\\ \·& \·& & \·& & \·\\ \·& \·& & \·& & \·\\ g_{m1}^{\′}& g_{m2}^{\′}& \·& \·& \·& h_{\mathrm{mn}}^{\′}\end{array}\right],$ Wherein f ' _xy2represent the default resonance paddy frequency threshold of signal path, f ' _xy1represent the default harmonic peak frequency threshold of signal path; Carry out feature extraction, remove the common mode information between relational matrix G and preset relation matrix G ', amplify the differential mode information between them, improve feature accuracy of identification;

Step S505: will the g after feature extraction in relational matrix G be carried out _xywith the g ' carried out after feature extraction in relational matrix G ' _xycompare, work as g _xybe greater than g ' _xytime, judge to there is hardware Trojan horse in chip to be measured;

Step S506: according to g _xythe path of above-mentioned hardware Trojan horse is located in chip to be measured; g _xyrepresent that in chip to be measured, an xth input signal exists hardware Trojan horse to the signal path that y outputs signal, path orientation greatly can improve the efficiency of subsequent physical positioning analysis, reduces workload and testing cost.

This application example obtains resonance paddy frequency and the harmonic peak frequency of each signal path in chip to be measured according to the amplitude-frequency response in the clock network path of the chip to be measured obtained, the relational matrix of chip to be measured is determined according to the resonance paddy frequency of each signal path and harmonic peak frequency, the relational matrix of chip to be measured and preset relation matrix are compared, judge whether there is hardware Trojan horse in chip to be measured according to comparative result, extra chip area need not be increased test, greatly reduce workload and testing cost, be applicable to application.

Based on the hardware Trojan horse detection system of time delay in an embodiment, as shown in Figure 6, comprising:

Acquisition module 601, for obtaining the bypass delayed data of chip to be measured, described bypass delayed data comprises amplitude-frequency response and/or the phase-frequency response curve of each signal path of described chip to be measured;

Processing module 602, for obtaining resonance paddy frequency and the harmonic peak frequency of each signal path of described chip to be measured according to described bypass delayed data;

Detection module 603, for the resonance paddy frequency of each signal path in described chip to be measured and harmonic peak frequency being compared with the default resonance paddy frequency threshold of each corresponding signal path and harmonic peak frequency threshold respectively, judge whether there is hardware Trojan horse in described chip to be measured according to comparative result.

As shown in Figure 6, first acquisition module 601 obtains the bypass delayed data of chip to be measured; Then processing module 602 obtains resonance paddy frequency and the harmonic peak frequency of each signal path of chip to be measured according to above-mentioned bypass delayed data; The resonance paddy frequency of each signal path in chip to be measured and harmonic peak frequency compare with the default resonance paddy frequency threshold of each corresponding signal path and harmonic peak frequency threshold by last detection module 603 respectively, judge whether there is hardware Trojan horse in chip to be measured according to comparative result.

Known from the above description, the present invention is based on the hardware Trojan horse detection system of time delay, extra chip area need not be increased and test, greatly reduce workload and testing cost, realistic application.

As an embodiment, described detection module 603 comprises:

Processing unit 6031, for obtaining relational matrix according to the resonance paddy frequency of each signal path in described chip to be measured and harmonic peak frequency: $G=\left[\begin{array}{cccccc}{g}_{11}& g_{12}& \·& \·& \·& g_{1n}\\ g_{21}& g_{22}& \·& \·& \·& g_{2n}\\ \·& \·& & \·& & \·\\ \·& \·& & \·& & \·\\ \·& \·& & \·& & \·\\ g_{m1}& g_{m2}& \·& \·& \·& g_{\mathrm{mn}}\end{array}\right],$ Wherein m represents total number of input signal in described chip to be measured, and n represents the total number outputed signal in described chip to be measured, wherein f _xy2represent the resonance paddy frequency of signal path, f _xy1represent the harmonic peak frequency of signal path;

Judging unit 6032, compares for the parameter that the parameter in described relational matrix G is corresponding with preset relation matrix G ', judges whether there is hardware Trojan horse in described chip to be measured, wherein according to comparative result $G^{\′}=\left[\begin{array}{cccccc}{g}_{11}^{\′}& g_{12}^{\′}& \·& \·& \·& g_{1n}^{\′}\\ g_{21}^{\′}& g_{22}^{\′}& \·& \·& \·& g_{2n}^{\′}\\ \·& \·& & \·& & \·\\ \·& \·& & \·& & \·\\ \·& \·& & \·& & \·\\ g_{m1}^{\′}& g_{m2}^{\′}& \·& \·& \·& h_{\mathrm{mn}}^{\′}\end{array}\right],g_{\mathrm{xy}}^{\′}=\frac{f_{\mathrm{xy}2}^{\′2}}{f_{\mathrm{xy}1}^{\′2}},$ F ' _xy2represent the default resonance paddy frequency threshold of signal path, f ' _xy1represent the default harmonic peak frequency threshold of signal path, wherein x=1,2 ..., m, y=1,2 ..., n;

There is the g value of hardware Trojan horse chip different from the g value without hardware Trojan horse chip, the g value of hardware Trojan horse chip is had to be greater than g value without hardware Trojan horse chip, can predetermined threshold value g ' according to this characteristic, when the g value of chip to be measured is greater than predetermined threshold value g ', judge to there is hardware Trojan horse in chip, when the g value of chip to be measured is less than predetermined threshold value g ', judge in chip without hardware Trojan horse.

As an embodiment, also comprise locating module 604, after detecting at described detection module 603 and there is hardware Trojan horse in described chip to be measured, locate the path of described hardware Trojan horse according to the parameter in described relational matrix G;

Work as g _xybe greater than corresponding predetermined threshold value g ' _xytime, judge to there is hardware Trojan horse, g in chip to be measured _xyrepresent that in chip to be measured, an xth input signal exists hardware Trojan horse to the signal path that y outputs signal, path orientation greatly can improve the efficiency of subsequent physical positioning analysis, reduces workload and testing cost.

As an embodiment, described detection module 603 also comprises extraction unit 6033, for after described processing unit 6031 obtains relational matrix G according to the resonance paddy frequency of each signal path in described chip to be measured and harmonic peak frequency, feature extraction is carried out to described relational matrix G and described preset relation matrix G ';

Described judging unit 6032 by the parameter in relational matrix G after carrying out feature extraction with carry out feature extraction after parameter corresponding in relational matrix G ' compare, judge whether there is hardware Trojan horse in described chip to be measured according to comparative result;

Carry out feature extraction, remove the common mode information between relational matrix G and preset relation matrix G ', amplify the differential mode information between them, improve feature accuracy of identification.

As an embodiment, described signal path comprises clock network path or electric power network path, each chip has multiple clock network or electric power network, and the hardware Trojan horse of sequential type or incorporating aspects type is all directly or indirectly connected with clock network or electric power network, therefore the existence of hardware Trojan horse will inevitably bring impact to clock network path or electric power network path delay, can carry out the detection analysis of hardware Trojan horse according to this characteristic; Above-mentioned signal path can also comprise other signal network path except clock network path and electric power network path.

Each technical characteristic of the above embodiment can combine arbitrarily, for making description succinct, each technical characteristic (as phase-frequency response curve etc.) all possible combination in above-described embodiment is not all described, but, as long as the combination of these technical characteristics does not exist contradiction, be all considered to be the scope that this instructions is recorded.

The above embodiment only have expressed several embodiment of the present invention, and it describes comparatively concrete and detailed, but can not therefore be construed as limiting the scope of the patent.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.

Claims (10)

1., based on a hardware Trojan horse detection method for time delay, it is characterized in that, comprise the following steps:

Obtain the bypass delayed data of chip to be measured, described bypass delayed data comprises amplitude-frequency response and/or the phase-frequency response curve of each signal path of described chip to be measured;

Resonance paddy frequency and the harmonic peak frequency of each signal path in described chip to be measured is obtained according to described bypass delayed data;

The resonance paddy frequency of each signal path in described chip to be measured and harmonic peak frequency are compared with the default resonance paddy frequency threshold of each corresponding signal path and harmonic peak frequency threshold respectively, judges whether there is hardware Trojan horse in described chip to be measured according to comparative result.

2. the hardware Trojan horse detection method based on time delay according to claim 1, it is characterized in that, the resonance paddy frequency of each signal path in described chip to be measured and harmonic peak frequency are compared with the default resonance paddy frequency threshold of each corresponding signal path and harmonic peak frequency threshold respectively, judge that the step that whether there is hardware Trojan horse in described chip to be measured comprises according to comparative result:

Relational matrix is obtained according to the resonance paddy frequency of each signal path in described chip to be measured and harmonic peak frequency:

$G=\left[\begin{array}{cccc}{g}_{11}& g_{12}& ...& g_{1n}\\ g_{21}& g_{22}& ...& g_{2n}\\ .& .& .& .\\ .& .& .& .\\ .& .& .& .\\ g_{m1}& g_{m2}& ...& g_{\mathrm{mn}}\end{array}\right],$ Wherein m represents total number of input signal in described chip to be measured, and n represents the total number outputed signal in described chip to be measured, wherein f _xy2represent the resonance paddy frequency of signal path, f _xy1represent the harmonic peak frequency of signal path;

The parameter that parameter in described relational matrix G is corresponding with preset relation matrix G ' compares, and judges whether there is hardware Trojan horse in described chip to be measured, wherein according to comparative result $G^{\′}=\left[\begin{array}{cccc}{g}_{11}^{\′}& g_{12}^{\′}& ...& g_{1n}^{\′}\\ g_{21}^{\′}& g_{22}^{\′}& ...& g_{2n}^{\′}\\ .& .& .& .\\ .& .& .& .\\ .& .& .& .\\ g_{m1}^{\′}& g_{m2}^{\′}& ...& g_{\mathrm{mn}}^{\′}\end{array}\right],$ f ' _xy2represent the default resonance paddy frequency threshold of signal path, f ' _xy1represent the default harmonic peak frequency threshold of signal path, wherein x=1,2 ..., m, y=1,2 ..., n.

3. the hardware Trojan horse detection method based on time delay according to claim 2, is characterized in that, after judge whether there is hardware Trojan horse in described chip to be measured according to comparative result, also comprises step:

When judging to there is hardware Trojan horse in described chip to be measured, locate the path of described hardware Trojan horse according to the parameter in described relational matrix G.

4. the hardware Trojan horse detection method based on time delay according to Claims 2 or 3, it is characterized in that, after obtaining relational matrix G according to the resonance paddy frequency of each signal path in described chip to be measured and harmonic peak frequency, before being compared by the parameter that parameter in described relational matrix G is corresponding with preset relation matrix G ', also comprise step:

Feature extraction is carried out to described relational matrix G and described preset relation matrix G '.

5. the hardware Trojan horse detection method based on time delay according to claim 1, is characterized in that, described signal path comprises clock network path or electric power network path.

6. based on a hardware Trojan horse detection system for time delay, it is characterized in that, comprising:

Acquisition module, for obtaining the bypass delayed data of chip to be measured, described bypass delayed data comprises amplitude-frequency response and/or the phase-frequency response curve of each signal path of described chip to be measured;

Processing module, for obtaining resonance paddy frequency and the harmonic peak frequency of each signal path of described chip to be measured according to described bypass delayed data;

Detection module, for the resonance paddy frequency of each signal path in described chip to be measured and harmonic peak frequency being compared with the default resonance paddy frequency threshold of each corresponding signal path and harmonic peak frequency threshold respectively, judge whether there is hardware Trojan horse in described chip to be measured according to comparative result.

7. the hardware Trojan horse detection system based on time delay according to claim 6, is characterized in that, described detection module comprises:

Processing unit, for obtaining relational matrix according to the resonance paddy frequency of each signal path in described chip to be measured and harmonic peak frequency: $G=\left[\begin{array}{cccc}{g}_{11}& g_{12}& ...& g_{1n}\\ g_{21}& g_{22}& ...& g_{2n}\\ .& .& .& .\\ .& .& .& .\\ .& .& .& .\\ g_{m1}& g_{m2}& ...& g_{\mathrm{mn}}\end{array}\right],$ Wherein m represents total number of input signal in described chip to be measured, and n represents the total number outputed signal in described chip to be measured, wherein f _xy2represent the resonance paddy frequency of signal path, f _xy1represent the harmonic peak frequency of signal path;

Judging unit, compares for the parameter that the parameter in described relational matrix G is corresponding with preset relation matrix G ', judges whether there is hardware Trojan horse in described chip to be measured, wherein according to comparative result $G^{\′}=\left[\begin{array}{cccc}{g}_{11}^{\′}& g_{12}^{\′}& ...& g_{1n}^{\′}\\ g_{21}^{\′}& g_{22}^{\′}& ...& g_{2n}^{\′}\\ .& .& .& .\\ .& .& .& .\\ .& .& .& .\\ g_{m1}^{\′}& g_{m2}^{\′}& ...& g_{\mathrm{mn}}^{\′}\end{array}\right],$ f ' _xy2represent the default resonance paddy frequency threshold of signal path, f ' _xy1represent the default harmonic peak frequency threshold of signal path, wherein x=1,2 ..., m, y=1,2 ..., n.

8. the hardware Trojan horse detection system based on time delay according to claim 7, it is characterized in that, also comprise locating module, for there is hardware Trojan horse in the described chip to be measured of described detection module detection after, locate the path of described hardware Trojan horse according to the parameter in described relational matrix G.

9. the hardware Trojan horse detection system based on time delay according to claim 7 or 8, it is characterized in that, described detection module also comprises extraction unit, for after described processing unit obtains relational matrix G according to the resonance paddy frequency of each signal path in described chip to be measured and harmonic peak frequency, feature extraction is carried out to described relational matrix G and described preset relation matrix G ';

Described judging unit by the parameter in relational matrix G after carrying out feature extraction with carry out feature extraction after parameter corresponding in relational matrix G ' compare, judge whether there is hardware Trojan horse in described chip to be measured according to comparative result.

10. the hardware Trojan horse detection system based on time delay according to claim 6, is characterized in that, described signal path comprises clock network path or electric power network path.