CN104935936A - Entropy decoder authentication method based on UVM and device - Google Patents
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Abstract
The invention discloses an entropy decoder authentication method based on a UVM (Universal Verification Methodology), and belongs to the video encoding and decoding technical field. According to the invention, the method authenticates the entropy decoder by using the UVM. The invention further discloses a entropy decoder authentication device based on the UVM. The device comprises a test case, a sequence generator, a driving module, a monitoring module, an entropy decoder reference model, a scoreboard and a function coverage module. Compared with the prior art, the entropy decoder authentication method based on the UVM and the entropy decoder authentication device based on the UVM can simply transplant and authenticate entropy decoders with various configurations, effectively improve the authentication reusability and efficiency and monitor the function coverage.
Description
Technical field
The present invention relates to a kind of entropy decoder verification method, particularly relate to a kind of entropy decoder verification method based on generic validation methodology (Universal Verification Methodology, UVM) and device, belong to video coding and decoding technology field.
Background technology
The fast development of chip design and verification technique makes the requirement of the functional verification of module more and more higher, completes functions of modules checking at short notice, ensures that logic function is correct, to the completeness of verification environment, automation and reusability has very high requirement.
H.264 standard is international video encoding standard, and AVS standard is domestic legal audio/video encoding standard, and domestic video reception apparatus must support AVS standard.H.264 be a kind of inevitable with the fusion of AVS, this proposes video decoding chip can the requirement of these two kinds of standards compatible.Even nowadays commercial AVS decoding chip is few, the decoding chip of these two kinds of standards compatible is less, therefore studies and design the chip of these two kinds of standards compatible simultaneously to have important value and significance.Entropy decoder is most important as the first order of video decoding chip, the functional verification of entropy decoder needs a large amount of manpower and materials, especially the entropy decoder that every money redesigns or changes all needs through a large amount of regression tests, and even repeatedly flow can really use in project.In the process of checking entropy decoder module, regenerate various different entropy decoder packet not only pretty troublesome, and interim writing is easy to occur mistake, this method is very low to the verification efficiency of entropy decoder module, and cannot reuse.
Summary of the invention
Technical problem to be solved by this invention is to overcome prior art deficiency, a kind of entropy decoder verification method based on UVM and device are provided, can better simply transplanting the entropy decoder of the different configuration of checking, effectively improve reusability and the efficiency of checking, and can monitor function coverage.
The present invention specifically solves the problems of the technologies described above by the following technical solutions:
Based on the entropy decoder verification method of UVM, generic validation methodology UVM is utilized to verify entropy decoder.
Preferably, described entropy decoder verification method comprises the following steps:
Step 1, sequence generator generate test video packet according to predefined video data;
Step 2, entropy decoder reference model and entropy decoder to be verified is utilized to carry out entropy decoding to test video packet respectively;
Step 3, the entropy decoded data that entropy decoder reference model and entropy decoder to be verified export to be compared, obtain the result of entropy decoder to be verified according to comparative result.
In order to improve versatility, further, described entropy decoder reference model comprises the sub-reference model of entropy decoder of at least two switchable employing different coding standards.
The present invention is based on the entropy decoder demo plant of UVM, comprising:
Test case, comprises one group of predefined video data;
Sequence generator, for being completed the definition of randomization data bag by test case, and after the specific features having retrained data, generates test video packet automatically;
Driver module, the test video packet for being generated by sequence generator converts the real input signal excitation of entropy decoder to be verified on interface to;
Monitoring modular, obtains entropy decoded data for the output interface from entropy decoder to be verified;
Entropy decoder reference model, carries out standard entropy decoding for the test video packet generated sequence generator;
Scoring board, obtains monitoring modular, entropy decoded data that entropy decoder reference model exports respectively, and compares both;
Functional coverage module, adds up for the function coverage of comparative result to entropy decoder to be verified according to scoring board.
Further, described entropy decoder reference model comprises the sub-reference model of entropy decoder of at least two switchable employing different coding standards.
Preferably, described driver module comprises sequencer, driver and monitor; The function of sequencer is organization and administration sequence generators, and when driver requires data, sequencer is transmitted to driver the affairs that sequence generator generates; The function of driver the test video packet that sequence generator generates is converted to the real input signal excitation of entropy decoder to be verified on interface; The function of monitor receives real input signal excitation from the input interface of entropy decoder to be verified, and send to entropy decoder reference model after the real input signal excitation received is changed into data packet level.
Compare prior art, the present invention has following beneficial effect:
UVM technology is applied to the checking of entropy decoder by the present invention first, achieve the checking structure of a stratification, the present invention can better simply transplanting the entropy decoder of the different configuration of checking, according to reference model generating reference data, and the output of monitoring entropy decoder to be verified generates result data, is verified entropy decoder by the consistency of judged result data and reference data; The present invention can utilize existing reference model to complete checking fast, improves reusability and the efficiency of checking, and function coverage model can be utilized in addition to collect and monitoring function coverage rate.
Accompanying drawing explanation
Fig. 1 is UVM basic frame structure;
Fig. 2 is the structural representation of entropy decoder demo plant of the present invention.
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is described in detail:
Basic ideas of the present invention utilize generic validation methodology (UVM) to verify entropy decoder.For the ease of public understanding, first the substance of UVM is briefly introduced.
Along with the complexity of design constantly increases, need more resource to be placed in checking, not only require that checking can cover all functions, also wish can provide a large amount of abnormal conditions to check the corresponding abnormal treatment state of design under test.In traditional test and method, above-mentioned requirements be difficult to often realize.In addition design and constantly reuse, and checking is also wished to reuse similar authentication module, this has just expedited the emergence of the verification method of stratification.UVM provides the verification method based on SystemVerilog, includes constrained generating random number, the checking structure of stratification, and is the checking flow process of index with function coverage.
SystemVerilog is a kind of hardware description and checking language, it is based upon on the basis of Verilog hardware description language, combine the feature of C++ object based programming simultaneously, and add assert, concept that interface, structure etc. are new, thus possessed object based programming, object-based random generation and constraint, the dynamically essential characteristic such as thread and inter-thread communication.SystemVerilog language is as the checking language of latest development, obtain the support of the companies such as Cadence, Mentor Graphics, multiple simulator can both support the compiling of this language, has become the checking language of design and checking engineer first-selection at present.
Generic validation methodology (Universal Verification Methodology, UVM) is a kind of standard realizing the efficient and reusable verification environment of rapid build and checking IP (VIP) in checking flow process.It is the verification methodology based on SystemVerilog language development complete set out.Accellera is the verification methodology alliance of company's united organizations such as Cadence, Mentor Graphics, Synopsys, this alliance is proposed UVM based on OVM verification methodology, and UVM is in fact a class libraries using the syntax and semantics definition of SystemVerilog.This verification method is tree-like verification platform, wherein incorporate a lot of up-to-date verification methodology, farthest achieve checking to reuse, thus improve the efficiency of checking, use it can create checking IP and testing process (testbench) assembly of solid, reusable, tool interoperability, generally accepted by industry and adopt.The concise and to the point frame structure of UVM as shown in Figure 1.
UVM is mainly used in the correctness verifying Digital Logical Circuits, and in the design cycle of digital circuit, first must define the specification of chip, be then refined into characteristic list, namely statement of requirements book, is called specification in engineering.System divides is become concrete module by the characteristic list according to refinement, and designer uses Verilog language to realize these modules, obtains RTL code.In this process, due to understanding deviation or the carelessness of designer, obtain RTL code and all characteristics of a complete reaction chip surely, therefore characteristic list and RTL code is needed to compare, namely so-called checking, is exactly that checking engineer proposes authentication function point according to specification, builds verification environment, write reference model, whether consistent both being observed by the operation of platform.In FIG, except verification platform assembly adopt port connect, namely affairs level (TLM, Transaction Level Modeling) transmission, this be relative in design to be measured between modules holding wire rank communication.So-called transaction is exactly the class that one group of Information encapsulation with a certain specific function is become together, and in the proof procedure in entropy decoder, transaction is exactly the data encapsulation of a two field picture together.
In addition, it is target that UVM methodology proposes with coverage rate, and constrained arbitrary excitation is the verification method of approach.Under the control of constraint, can produce the excitation of random combine, arbitrary excitation, touching some border condition being difficult to verify by direct test case, can utilize UVM verification environment to verify more test case more.Here coverage rate also has function coverage except conventional code coverage, as long as all function points of checking that needs all are converted into function coverage model, so in whole proof procedure, emulation tool can collect coverage rate information.Finally function coverage result can be merged, only have the function coverage of 100% just to represent proof procedure and terminate.
UVM methodology not only provides the methodology setting up verification environment, also provides a whole set of and verifies basic class libraries, contains the basic class of authentication module, and the framework of the flow process of checking, contains some macrodefinitions and message mechanism in addition.Class libraries can set up the verification environment of oneself very soon, as long as pay close attention to functional verification itself, and does not need the bottom running too much considering environment.
Fig. 2 shows a specific embodiment of entropy decoder demo plant of the present invention, and adopt SystemVerilog to complete, wherein the superiors region is all test cases and verification environment, and lowermost part is entropy decoder (design under test) to be measured.The present invention redefines the sequence generator in UVM platform, and sequence generator can produce different test scenes, and each scene is made up of a series of video data.Wherein the test scene of difference in functionality can be generated by the coded portion of canonical reference software, and video packets of data is sent to entropy decoder by driver, and result data and the collected scoring board of reference data compare automatically.As shown in Figure 2, this entropy decoder demo plant mainly comprises following 7 assemblies: test case, sequence generator (sequence), driver module (in_agent), monitoring modular (out_agent), entropy decoder reference model (reference model), scoring board (scoreboard), function coverage module.Be connected by port (port) or communicate between UVM assembly.
The present invention uses the test scene of UVM platform simulation entropy decoder, and entropy decoder module and entropy decoder reference model are decoded to the video packets of data that test scene produces, and the result collected is compared by scoring board, and statistical testing of business cycles coverage rate.
According to the flow process of entropy decoding, different entropy decoding functions needs different test scenes, joint video team (Joint Video Team, and digital audio/video encoding and decoding technique standard operation group (Audio Video Standard JVT), AVS) standard testing video code flow is each provided, UVM platform builds test scene according to standard testing code stream, and code stream is packaged into data packet format.In Fig. 2, test case represents the test scene of checking entropy decoder, and simulation process writes different test cases according to demonstration plan, and gives different priority according to the importance difference of test function point, effectively can improve the efficiency of emulation like this.
After determining test case, packet sends into driver module, and it is made up of sequence generator, sequencer, driver.Sequence generator sequence is according to predefined video data, complete the definition of randomization data bag, after the specific features having retrained data, by automatically generated data bag function automatically generated data bag, different sequence is comprised in test case, different sequence can be arranged to default sequence, different excitations can be produced like this, this verification platform needs two kinds of excitations, and sequential has successively difference, therefore adopt the method for virtual sequence to carry out Control timing sequence problem;
The function of sequencer sequencer is organization and administration sequence, very close relationship is had with driver driver, connected by port port, when driver asks video data to sequence people, sequencer is transmitted to driver the affairs that sequence generates;
Driver driver is connected with entropy decoder module by interface, owing to adopting the communication mode of transaction-level model between Verification Components, the transaction-level packet that driver will receive, convert the actual signal excitation of pin level on entropy decoder interface to, the concrete operations of driver all define in run () task, according to the time sequence information on entropy decoder interface, the function that one or more run_time stage improves driver can be performed;
Entropy decoder module completes entropy decoding function in video, first judge the type of code stream according to the code stream information in video packets of data, if H.264 code stream, hang up uncorrelated module, entropy decoder is configured to H.264 entropy decoder, completes the decoding of macroblock layer and the above syntactic element of macroblock layer; If AVS code stream, equally entropy decoder is configured to AVS decoder, various syntactic element of decoding.Detection module comprises monitor monitor, and it will monitor the syntactic element that entropy decoder module exports, and sends into scoring board.Monitor monitor has two types, the first is the monitor in driver module in_agent, receive data from the input interface of entropy decoder module to be verified, and the data transformations received is become data packet level, and send to the reference model of entropy decoder; The second is the monitor in monitoring modular out_agent, receives data from the output interface of entropy decoder, and by Packet Generation in scoring board, for comparing reference data and testing data.
Scoring board scoreboard obtains result data bag respectively by port from monitoring modular and entropy decoder reference model reference model, real-time comparing data, scoreboard verifies whether design to be measured normally runs on a functional, it is by port exp_port, act_port respectively with reference model, monitor is connected, in the run_phase stage, the get function of exp_port constantly reads the affairs of reference model generation, and be temporarily stored in exp_queue queue, and the affairs that Real-Time Monitoring act_port port is caught by monitor, compare with the affairs in exp_queue, if both just print correct information always, otherwise print error message, facilitate location of mistake,
In the starting stage of emulation, first to passing through smoke test, by writing the groundwork flow process of simple testing case entropy decoder, getting through whole data path, whether can office normally work with authentication module; Then carry out according to the function point of disparate modules the emulation having emphasis; Finally to carry out loopback test and regression test, all test cases are all run one time, ensure entropy decoder design code after amendment also by all emulation testings.
Function coverage module by functional coverage group (cover_group) function definition functional coverage point, and covers crawl statistics coverage rate by sampling functions.
The present invention adopts the hierarchical structure of UVM, utilizes video standard reference software to complete the generation of excited data and the realization of reference model, significantly reduces checking workload; Realize automatized script to run, automatic comparative result, and the statistics of coverage rate, improve verification efficiency.The present invention can complete the comprehensive checking comprising H.264 standard and AVS standard, realizes the comprehensively complete functional level simulating, verifying of entropy decoder; Also certain checking is had to the compatible aspect of entropy decoder module.The invention enables the checking of entropy decoder module complete and fully, randomized excitation producing method, the results contrast of automation, also convenient checking regression test (Regression).
Claims (9)
1. based on the entropy decoder verification method of UVM, it is characterized in that, utilize generic validation methodology UVM to verify entropy decoder.
2. entropy decoder verification method as claimed in claim 1, is characterized in that, comprise the following steps:
Step 1, sequence generator generate test video packet according to predefined video data;
Step 2, entropy decoder reference model and entropy decoder to be verified is utilized to carry out entropy decoding to test video packet respectively;
Step 3, the entropy decoded data that entropy decoder reference model and entropy decoder to be verified export to be compared, obtain the result of entropy decoder to be verified according to comparative result.
3. entropy decoder verification method as claimed in claim 2, it is characterized in that, described entropy decoder reference model comprises the sub-reference model of entropy decoder of at least two switchable employing different coding standards.
4. entropy decoder verification method as claimed in claim 3, it is characterized in that, the sub-reference model of described entropy decoder comprises the sub-reference model of H.264 entropy decoder and the sub-reference model of AVS entropy decoder.
5. entropy decoder verification method as claimed in claim 4, it is characterized in that, H.264 the sub-reference model of entropy decoder and the sub-reference model of AVS entropy decoder all adopt c programming language to write.
6., based on the entropy decoder demo plant of UVM, it is characterized in that, comprising:
Test case, comprises one group of predefined video data;
Sequence generator, for being completed the definition of randomization data bag by test case, and after the specific features having retrained data, generates test video packet automatically;
Driver module, the test video packet for being generated by sequence generator converts the real input signal excitation of entropy decoder to be verified on interface to;
Monitoring modular, obtains entropy decoded data for the output interface from entropy decoder to be verified;
Entropy decoder reference model, carries out standard entropy decoding for the test video packet generated sequence generator;
Scoring board, obtains monitoring modular, entropy decoded data that entropy decoder reference model exports respectively, and compares both;
Functional coverage module, adds up for the function coverage of comparative result to entropy decoder to be verified according to scoring board.
7. entropy decoder demo plant as claimed in claim 6, it is characterized in that, described entropy decoder reference model comprises the sub-reference model of entropy decoder of at least two switchable employing different coding standards.
8. entropy decoder demo plant as claimed in claim 7, it is characterized in that, the sub-reference model of described entropy decoder comprises the sub-reference model of H.264 entropy decoder and the sub-reference model of AVS entropy decoder.
9. entropy decoder demo plant as claimed in claim 6, it is characterized in that, described driver module comprises sequencer, driver and monitor; The function of sequencer is organization and administration sequence generators, and when driver requires data, sequencer is transmitted to driver the affairs that sequence generator generates; The function of driver the test video packet that sequence generator generates is converted to the real input signal excitation of entropy decoder to be verified on interface; The function of monitor receives real input signal excitation from the input interface of entropy decoder to be verified, and send to entropy decoder reference model after the real input signal excitation received is changed into data packet level.
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