CN104934439B - The production method and its structure of TFT substrate - Google Patents
The production method and its structure of TFT substrate Download PDFInfo
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Abstract
The present invention provides a kind of production method and its structure of TFT substrate.The production method of the TFT substrate retains certain thickness by the way that amorphous silicon layer (51) to be located to the part of non-TFT zone in first of dry ecthing procedure, while forming back of the body raceway groove (515) in second dry ecthing procedure, etch away the amorphous silicon layer (51) remained in non-TFT zone, to prevent gate insulating layer (4) to be damaged in second dry ecthing procedure, improve the quality of TFT substrate, reduce the risk of quality problem generation, and due to the etch quantity for reducing first of dry ecthing procedure, to reduce the dry ecthing procedure time, shorten the production cycle, improve factory's production capacity.A kind of TFT substrate provided by the invention, simple in structure, the quality of liquid crystal display can be improved in gate insulating layer (4) intact wound.
Description
Technical field
The present invention relates to display technology field more particularly to the production methods and its structure of a kind of TFT substrate.
Background technology
With the development of display technology, the planes such as liquid crystal display (Liquid Crystal Display, LCD) display dress
It sets because having many advantages, such as that high image quality, power saving, fuselage are thin, and is widely used in mobile phone, TV, personal digital assistant, number
The various consumer electrical products such as camera, laptop, desktop computer, become the mainstream in display device.
Liquid crystal display device on existing market is largely backlight liquid crystal display comprising liquid crystal display panel and
Backlight module (backlight module).The operation principle of liquid crystal display panel is put in the parallel glass substrate of two panels
Liquid crystal molecule is set, there are many tiny electric wires vertically and horizontally for two panels glass substrate centre, and liquid crystal is controlled whether by being powered
The light refraction of backlight module is out generated picture by molecular changes direction.
Usual liquid crystal display panel is by color film (Color Filter, CF) substrate, thin-film transistor array base-plate (Thin
Film Transistor Array Substrate, TFT Array Substrate), be sandwiched between CF substrates and TFT substrate
Liquid crystal (Liquid Crystal, LC) and sealing glue frame (Sealant) composition, moulding process generally comprises：Leading portion array
(Array) processing procedure (film, yellow light, etching and stripping), stage casing at box (Cell) processing procedure (TFT substrate is bonded with CF substrates) and after
Section module group assembling processing procedure (driving IC is pressed with printed circuit board).Wherein, leading portion Array processing procedures mainly form TFT substrate, with
Convenient for controlling the movement of liquid crystal molecule；Stage casing Cell processing procedures mainly add liquid crystal between TFT substrate and CF substrates；Back segment mould
Group assembling processing procedure is mainly to drive the integration of IC pressing and printed circuit board, and then drive liquid crystal molecule rotation, shows image.
As shown in figures 1 to 6, the production method of existing a kind of TFT substrate, includes the following steps：
Step 1, as shown in Figure 1, providing a substrate 100, the substrate 100 is equipped with TFT zone and non-TFT zone, institute
Meaning TFT zone refers to the corresponding residing regions on substrate final TFT obtained；The first metal is deposited on the substrate 100
Layer, and the first metal layer is patterned by one of lithographic process, form the grid 300 being located in the middle part of TFT zone；
Step 2, as shown in Fig. 2, being sequentially depositing gate insulating layer 400, non-crystalline silicon on the grid 300 and substrate 100
Layer 510 and N-type heavily doped amorphous silicon layer 520；
Step 3, as shown in figure 3, using one lithographic process simultaneously to the N-type heavily doped amorphous silicon layer 520 and amorphous
Silicon layer 510 carries out patterned process so that the N-type heavily doped amorphous silicon layer 520 forms island N-type heavily doped amorphous silicon layer
540, the amorphous silicon layer 510 forms island amorphous silicon layer 530, the island N-type heavily doped amorphous silicon layer 540 and island amorphous
Silicon layer 530 is overlapped, and the two is corresponding positioned at the top of the grid 300, and the cross sectional dimensions of the two is exhausted less than the grid
The cross sectional dimensions of edge layer 300；
Lithographic process in the step 3 includes applying photoresist, exposure, development, first of dry ecthing and removing photoresistance processing procedure；
Step 4, as shown in figure 4, being deposited on the island N-type heavily doped amorphous silicon layer 540 and gate insulating layer 400
Second metal layer 700；
Step 5, as shown in figure 5, patterned to the first metal layer 700 using one of lithographic process, form position
Source electrode 710 in TFT zone and drain electrode 720；
Lithographic process in the step 5 includes applying photoresist, exposure, development, wet etching and removing photoresistance processing procedure；
Step 6, as shown in fig. 6, with the source electrode 710 with drain electrode 720 to block, using second dry ecthing procedure to institute
It states island N-type heavily doped amorphous silicon layer 540 to be etched with island amorphous silicon layer 530 so that the island N-type heavy doping amorphous
Silicon layer 540 is not now completely etched away by the part that source electrode 710 is blocked with drain electrode 720, and the island amorphous silicon layer 530 is not by source electrode
The thickness of 710 parts blocked with drain electrode 720 reduces, and forms back of the body raceway groove 535.
The production method of above-mentioned TFT substrate, due to carry out step 3 first of dry ecthing procedure when, by amorphous
The part that silicon layer 510 is located at non-TFT zone with N-type heavily doped amorphous silicon layer 520 is fully etched (as shown in Figure 3), works as progress
When the second dry ecthing procedure of step 6, the upper that the gate insulating layer 400 is located at non-TFT zone does not block, because
This is often etched a part, to make the gate insulating layer 400 be located at non-TFT zone part thickness reduce,
Damage (as shown in Figure 6) is caused, according to practical experience, the etch quantity of second dry ecthing procedure isIt would generally cause
Gate insulating layer 400 is thinnedActual liquid crystal capacitance and storage capacitance (MII capacitances) can be caused to deviate simulation in this way
As a result, causing the deviation of the parameters such as image flicker (Flicker) and coupled voltages (Vft), response time and charge rate.
It is therefore desirable to provide a kind of production method of improved TFT substrate, to overcome above-mentioned technical problem.
Invention content
The purpose of the present invention is to provide a kind of production methods of TFT substrate, gate insulating layer can be prevented in second
It is damaged in dry ecthing procedure, improves the quality of TFT substrate, and shorten the production cycle, promote factory's production capacity.
The present invention also aims to provide a kind of TFT substrate structure, simple in structure, gate insulating layer is intact
Wound, can improve the quality of liquid crystal display.
To achieve the above object, present invention firstly provides a kind of production method of TFT substrate, include the following steps：
Step 1 provides a substrate, and the substrate is equipped with TFT zone and non-TFT zone；Is deposited on the substrate
One metal layer, and the first metal layer is patterned by one of lithographic process, form the grid being located in the middle part of TFT zone；
Step 2 is sequentially depositing gate insulating layer, amorphous silicon layer and N-type heavy doping amorphous on the grid and substrate
Silicon layer；
Step 3 coats photoresist layer on the N-type heavily doped amorphous silicon layer, by one of optical cover process to the photoresist layer
It is exposed, develops, obtain the etch stop layer that the top in the middle part of the grid covers the N-type heavily doped amorphous silicon layer, then
It is to block with the etch stop layer, using first of dry ecthing procedure simultaneously to the N-type heavily doped amorphous silicon layer and amorphous
Silicon layer carries out patterned process, is fully etched the portion that the N-type heavily doped amorphous silicon layer is not blocked by the etch stop layer
Point, while the thickness for the part that the amorphous silicon layer is not blocked by the etch stop layer is thinned, it is formed corresponding positioned at the grid
The island N-type heavily doped amorphous silicon layer of top in the middle part of pole, by the amorphous silicon layer of island N-type heavily doped amorphous silicon layer covering
Thick-layer region and the coating region for being distributed in thick-layer region both sides；
After step 4, the removal etch stop layer, sink on the island N-type heavily doped amorphous silicon layer and amorphous silicon layer
Product second metal layer；
Step 5 patterns the second metal layer using one of lithographic process, is formed positioned at the source of TFT zone
Pole and drain electrode；
Lithographic process in the step 5 includes applying photoresist, exposure, development, wet etching and removing photoresistance processing procedure；
Step 6 is blocked with the source electrode with drain electrode, using second dry ecthing procedure to the island N-type heavy doping
Amorphous silicon layer and amorphous silicon layer are etched so that the island N-type heavily doped amorphous silicon layer is not hidden by the source electrode and drain electrode
The part of gear is now completely etched away, and the thick-layer region of the amorphous silicon layer is not by the thickness of the source electrode and the part blocked that drains
It is thinned, forms back of the body raceway groove；
The part that the coating region of the amorphous silicon layer is located at non-TFT zone is now completely etched away；
Amorphous silicon layer after second dry ecthing collectively forms semiconductor layer with island N-type heavily doped amorphous silicon layer.
In the step 1, the first metal layer, the material of the first metal layer are deposited using physical vaporous deposition
For copper, aluminium or molybdenum.
In the step 2, using gate insulating layer, amorphous silicon layer described in chemical vapor deposition and N-type heavy doping
The material of amorphous silicon layer, the gate insulating layer is silicon oxide or silicon nitride.
In the step 4, the second metal layer, the material of the second metal layer are deposited using physical vaporous deposition
For copper, aluminium or molybdenum.
The etch quantity of second dry ecthing procedure has carried out first of dry corrosion more than the step 3 and has scribed in the step 6
The thickness of the coating region of the amorphous silicon layer after journey.
The present invention also provides a kind of TFT substrate structures, including：
Substrate, the substrate are equipped with TFT zone and non-TFT zone；
Grid, the grid are set in the middle part of the TFT zone on the substrate；
Gate insulating layer, the gate insulating layer cover the grid and substrate；
And it is cascadingly set on the non-crystalline silicon on the gate insulating layer from top to bottom corresponding to the TFT zone
Layer, island N-type heavily doped amorphous silicon layer and source electrode and drain electrode；
The amorphous silicon layer includes carrying on the back raceway groove, positioned at the thick-layer region of back of the body raceway groove both sides and positioned at the separate back of the body in thick-layer region
The coating region of raceway groove side；The island N-type heavily doped amorphous silicon layer is Chong Die with thick-layer region, and the two is corresponded to positioned at described
Top in the middle part of grid；The coating region is located between the source electrode and gate insulating layer and the drain electrode is exhausted with grid
Between edge layer；
The amorphous silicon layer collectively forms semiconductor layer with island N-type heavily doped amorphous silicon layer.
The substrate is glass substrate.
The material of the grid is copper, aluminium or molybdenum.
The material of the gate insulating layer is silicon oxide or silicon nitride.
The source, drain electrode material be copper, aluminium or molybdenum.
Beneficial effects of the present invention：The production method of a kind of TFT substrate provided by the invention, by first of dry ecthing
The part that the amorphous silicon layer is located to non-TFT zone in processing procedure retains certain thickness, the shape in second dry ecthing procedure
While at back of the body raceway groove, the amorphous silicon layer remained in non-TFT zone is etched away, to prevent gate insulating layer in second
It is damaged in dry ecthing procedure, improves the quality of TFT substrate, reduce the risk of quality problem generation, and due to subtracting
The etch quantity for having lacked first of dry ecthing procedure shortens the production cycle, improves work to reduce the dry ecthing procedure time
Factory's production capacity.A kind of TFT substrate structure provided by the invention, simple in structure, liquid crystal can be improved in wound that gate insulating layer is intact
The quality of display.
For further understanding of the features and technical contents of the present invention, it please refers to below in connection with the detailed of the present invention
Illustrate and attached drawing, however, the drawings only provide reference and explanation, is not intended to limit the present invention.
Description of the drawings
Below in conjunction with the accompanying drawings, it is described in detail by the specific implementation mode to the present invention, technical scheme of the present invention will be made
And other beneficial effects are apparent.
In attached drawing,
Fig. 1 is a kind of existing schematic diagram of the production method step 1 of TFT substrate；
Fig. 2 is a kind of existing schematic diagram of the production method step 2 of TFT substrate；
Fig. 3 is a kind of existing schematic diagram of the production method step 3 of TFT substrate；
Fig. 4 is a kind of existing schematic diagram of the production method step 4 of TFT substrate；
Fig. 5 is a kind of existing schematic diagram of the production method step 5 of TFT substrate；
Fig. 6 is a kind of existing schematic diagram of the production method step 6 of TFT substrate；
Fig. 7 is the flow chart of the production method of the TFT substrate of the present invention；
Fig. 8 is the schematic diagram of the production method step 1 of the TFT substrate of the present invention；
Fig. 9 is the schematic diagram of the production method step 2 of the TFT substrate of the present invention；
Figure 10 is the schematic diagram of the production method step 3 of the TFT substrate of the present invention；
Figure 11 is the schematic diagram of the production method step 4 of the TFT substrate of the present invention；
Figure 12 is the schematic diagram of the production method step 5 of the TFT substrate of the present invention；
Figure 13 is the schematic diagram of the production method step 6 of the TFT substrate of the present invention and showing for TFT substrate structure of the invention
It is intended to.
Specific implementation mode
Further to illustrate the technological means and its effect of the invention taken, below in conjunction with the preferred implementation of the present invention
Example and its attached drawing are described in detail.
Referring to Fig. 7, present invention firstly provides a kind of production method of TFT substrate, include the following steps：
Step 1, as shown in figure 8, providing a substrate 1, the substrate 1 is equipped with TFT zone and non-TFT zone；Described
The first metal layer is deposited on substrate 1, and the first metal layer is patterned by one of lithographic process, is formed and is located in TFT zone
The grid 3 in portion.
Specifically, which deposits the first metal layer, the material of the first metal layer using physical vaporous deposition
Material is copper, aluminium or molybdenum.
Step 2, as shown in figure 9, be sequentially depositing on the grid 3 and substrate 1 gate insulating layer 4, amorphous silicon layer 51,
And N-type heavily doped amorphous silicon layer 52.
Specifically, non-using gate insulating layer described in chemical vapor deposition 4, amorphous silicon layer 51 and N-type heavy doping
Crystal silicon layer 52.The material of the gate insulating layer 4 is silicon oxide or silicon nitride.
Step 3, as shown in Figure 10, coat photoresist layer on the N-type heavily doped amorphous silicon layer 52, pass through one of light shield system
Journey is exposed the photoresist layer, develops, and obtains covering the N-type heavily doped amorphous silicon layer 52 in 3 middle part top of the grid
Etch stop layer 6, then with the etch stop layer 6 be to block, it is heavily doped to the N-type simultaneously using first dry ecthing procedure
Miscellaneous amorphous silicon layer 52 and amorphous silicon layer 51 carry out patterned process, be fully etched the N-type heavily doped amorphous silicon layer 52 not by
The part that the etch stop layer 6 blocks, while the part that the amorphous silicon layer 51 is not blocked by the etch stop layer 6 is thinned
Thickness, form the corresponding island N-type heavily doped amorphous silicon layer 54 for being located at 3 middle part top of the grid, by the island N-type weight
Doped amorphous silicon layer 54 cover amorphous silicon layer 51 thick-layer region 511 and be distributed in the thin of 511 both sides of thick-layer region
Layer region 512.
It is noted that after first of dry ecthing procedure of the step 3, the amorphous silicon layer 51 is located at the non-areas TFT
The part in domain also remains with certain thickness, thus to 4 shape of gate insulating layer during raceway groove is carried on the back in 6 dry ecthing of subsequent step
At protection.
Step 4, as shown in figure 11, after removing the etch stop layer 6, the island N-type heavily doped amorphous silicon layer 54,
And depositing second metal layer 7 on amorphous silicon layer 51.
Specifically, which deposits the second metal layer 7 using physical vaporous deposition, the second metal layer 7
Material is copper, aluminium or molybdenum.
Step 5, as shown in figure 12, the first metal layer 7 is patterned using one of lithographic process, formation is located at
The source electrode 71 of TFT zone and drain electrode 72.
Specifically, the lithographic process in the step 5 includes applying photoresist, exposure, development, wet etching and removing photoresistance processing procedure.
Step 6, as shown in figure 13, with the source electrode 71 with drain electrode 72 be block, using second dry ecthing procedure to institute
It states island N-type heavily doped amorphous silicon layer 54 and amorphous silicon layer 51 is etched so that the island N-type heavily doped amorphous silicon layer
54 are not now completely etched away by the part that the source electrode 71 is blocked with drain electrode 72, and the thick-layer region 511 of the amorphous silicon layer 51 is not
It is thinned by the thickness for the part that the source electrode 71 is blocked with drain electrode 72, forms back of the body raceway groove 515.
At the same time, the coating region 512 of the amorphous silicon layer 51 is located at the part of non-TFT zone and is now completely etched away.
Amorphous silicon layer 51 after second dry ecthing collectively forms semiconductor layer with island N-type heavily doped amorphous silicon layer 54.
Due to during the second dry ecthing procedure, having non-crystalline silicon above the gate insulating layer 4 of non-TFT zone
The coating region 512 of layer 51 is protected, therefore will not cause to damage to gate insulating layer 4.Theoretically, the second in the step 6
The etch quantity of dry ecthing procedure should carry out the thin layer area of the amorphous silicon layer 51 after first of dry ecthing procedure with the step 3
The thickness in domain 512 is equal, but the problem of in view of etch process homogeneity, the erosion of the second dry ecthing procedure in the step 6
Quarter, amount should be slightly bigger than the thickness that the step 3 has carried out the coating region 512 of the amorphous silicon layer 51 after first of dry ecthing procedure
Degree, to ensure that second dry ecthing procedure can lose the coating region 512 of the amorphous silicon layer 51 in non-TFT zone completely
Quarter is fallen, and does not cause significantly to damage to gate insulating layer 4.
First of dry ecthing procedure of production method pair and the second dry ecthing procedure of above-mentioned TFT substrate are improved,
Part by the way that amorphous silicon layer 51 to be located to non-TFT zone in first of dry ecthing procedure retains certain thickness, second
While forming back of the body raceway groove 515 in road dry ecthing procedure, the amorphous silicon layer 51 remained in non-TFT zone is etched away, to
It prevents gate insulating layer 4 to be damaged in second dry ecthing procedure, improves the quality of TFT substrate, reduce quality problem
The risk of generation, and the etch quantity due to reducing first of dry ecthing procedure, to reduce the dry ecthing procedure time, contracting
The short production cycle, improve factory's production capacity.
3 are please referred to Fig.1, the present invention also provides a kind of TFT substrate structures prepared by above-mentioned production method, including：
Substrate 1, the substrate 1 are equipped with TFT zone and non-TFT zone；
Grid 3, the grid 3 are set in the middle part of the TFT zone on the substrate 1；
Gate insulating layer 4, the gate insulating layer 4 cover the grid 3 and substrate 1；
And it is cascadingly set on the non-crystalline silicon on the gate insulating layer 4 from top to bottom corresponding to the TFT zone
Layer 51, island N-type heavily doped amorphous silicon layer 54 and source electrode 71 and drain electrode 72.
The amorphous silicon layer 51 includes back of the body raceway groove 515, positioned at the thick-layer region 511 of back of the body raceway groove both sides and positioned at thick-layer area
Coating region 512 of the domain 511 far from 515 side of back of the body raceway groove；The island N-type heavily doped amorphous silicon layer 54 and thick-layer region 511
Overlapping, and the two corresponds to the top for being located at 3 middle part of the grid；The coating region 512 is located in the source electrode 71 and grid
Between insulating layer 4 and between the drain electrode 72 and gate insulating layer 4；The amorphous silicon layer 51 and island N-type heavily doped amorphous silicon
Layer 54 collectively forms semiconductor layer.
Preferably, the substrate 1 is glass substrate.
The material of the grid 3 is copper, aluminium or molybdenum.
The material of the gate insulating layer 4 is silicon oxide or silicon nitride.
The source, drain 71,72 material be copper, aluminium or molybdenum.
In conclusion the present invention TFT substrate production method, by first of dry ecthing procedure by the amorphous
The part that silicon layer is located at non-TFT zone retains certain thickness, while forming back of the body raceway groove in second dry ecthing procedure, erosion
Carve the amorphous silicon layer that is remained in non-TFT zone, to prevent gate insulating layer in second dry ecthing procedure by
Damage, improves the quality of TFT substrate, reduces the risk of quality problem generation, and due to reducing first of dry ecthing
The etch quantity of processing procedure shortens the production cycle to reduce the dry ecthing procedure time, improves factory's production capacity.The present invention carries
The TFT substrate structure of confession, simple in structure, the quality of liquid crystal display can be improved in wound that gate insulating layer is intact.
The above for those of ordinary skill in the art can according to the technique and scheme of the present invention and technology
Other various corresponding change and deformations are made in design, and all these change and distortions should all belong to the claims in the present invention
Protection domain.
Claims (5)
1. a kind of production method of TFT substrate, which is characterized in that include the following steps：
Step 1 provides a substrate (1), and the substrate (1) is equipped with TFT zone and non-TFT zone；It sinks on the substrate (1)
Product the first metal layer, and the first metal layer is patterned by one of lithographic process, form the grid being located in the middle part of TFT zone
(3)；
Step 2 is sequentially depositing gate insulating layer (4), amorphous silicon layer (51) and N-type weight on the grid (3) and substrate (1)
Doped amorphous silicon layer (52)；
Step 3 coats photoresist layer on the N-type heavily doped amorphous silicon layer (52), by one of optical cover process to the photoresist layer
It is exposed, develops, obtain the etching resistance that the top in the middle part of the grid (3) covers the N-type heavily doped amorphous silicon layer (52)
Barrier (6), then with the etch stop layer (6) to block, it is non-to the N-type heavy doping simultaneously using first of dry ecthing procedure
Crystal silicon layer (52) and amorphous silicon layer (51) carry out patterned process, are fully etched the N-type heavily doped amorphous silicon layer (52) not
The part blocked by the etch stop layer (6), while the amorphous silicon layer (51) is thinned and is not hidden by the etch stop layer (6)
The thickness of the part of gear forms the corresponding island N-type heavily doped amorphous silicon layer (54), quilt for being located at top in the middle part of the grid (3)
It the thick-layer region (511) of the amorphous silicon layer (51) of the island N-type heavily doped amorphous silicon layer (54) covering and is distributed in described
The coating region (512) of thick-layer region (511) both sides；
After step 4, the removal etch stop layer (6), in the island N-type heavily doped amorphous silicon layer (54) and amorphous silicon layer
(51) depositing second metal layer (7) on；
Step 5 patterns the second metal layer (7) using one of lithographic process, forms the source electrode positioned at TFT zone
(71) and (72) are drained；
Lithographic process in the step 5 includes applying photoresist, exposure, development, wet etching and removing photoresistance processing procedure；
Step 6 is blocked with the source electrode (71) with drain electrode (72), using second dry ecthing procedure to the island N-type weight
Doped amorphous silicon layer (54) and amorphous silicon layer (51) are etched so that the island N-type heavily doped amorphous silicon layer (54) not by
The part that the source electrode (71) is blocked with drain electrode (72) is now completely etched away, the thick-layer region (511) of the amorphous silicon layer (51)
The thickness for the part that do not blocked with drain electrode (72) by the source electrode (71) is thinned, and forms back of the body raceway groove (515)；
The part that the coating region (512) of the amorphous silicon layer (51) is located at non-TFT zone is now completely etched away；
Amorphous silicon layer (51) after second dry ecthing collectively forms semiconductor with island N-type heavily doped amorphous silicon layer (54)
Layer.
2. the production method of TFT substrate as described in claim 1, which is characterized in that in the step 1, using physical vapor
The material of the first metal layer described in deposition method, the first metal layer is copper, aluminium or molybdenum.
3. the production method of TFT substrate as described in claim 1, which is characterized in that in the step 2, using chemical gaseous phase
Gate insulating layer described in deposition method (4), amorphous silicon layer (51) and N-type heavily doped amorphous silicon layer (52), the gate insulator
The material of layer (4) is silicon oxide or silicon nitride.
4. the production method of TFT substrate as described in claim 1, which is characterized in that in the step 4, using physical vapor
The material of second metal layer described in deposition method (7), the second metal layer (7) is copper, aluminium or molybdenum.
5. the production method of TFT substrate as described in claim 1, which is characterized in that second dry corrosion is scribed in the step 6
The etch quantity of journey is more than the coating region that the step 3 has carried out the amorphous silicon layer (51) after first of dry ecthing procedure
(512) thickness.
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| US10651257B2 (en) | 2017-12-18 | 2020-05-12 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Array substrate and manufacturing method thereof |
| CN113972138B (en) * | 2021-10-09 | 2023-11-28 | Tcl华星光电技术有限公司 | Manufacturing method of thin film transistor and thin film transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1684273A (en) * | 2004-04-14 | 2005-10-19 | Nec液晶技术株式会社 | Thin film transistor and its producing method |
| CN1770409A (en) * | 2004-11-03 | 2006-05-10 | 中华映管股份有限公司 | Etching method and method for manufacturing thin film transistor employing the same |
| US8349630B1 (en) * | 2011-06-28 | 2013-01-08 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Methods for manufacturing thin film transistor array substrate and display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1684273A (en) * | 2004-04-14 | 2005-10-19 | Nec液晶技术株式会社 | Thin film transistor and its producing method |
| CN1770409A (en) * | 2004-11-03 | 2006-05-10 | 中华映管股份有限公司 | Etching method and method for manufacturing thin film transistor employing the same |
| US8349630B1 (en) * | 2011-06-28 | 2013-01-08 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Methods for manufacturing thin film transistor array substrate and display panel |
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