CN104934009B - Shift register cell and driving method, shift-register circuit and display device - Google Patents
Shift register cell and driving method, shift-register circuit and display device Download PDFInfo
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- CN104934009B CN104934009B CN201510401027.6A CN201510401027A CN104934009B CN 104934009 B CN104934009 B CN 104934009B CN 201510401027 A CN201510401027 A CN 201510401027A CN 104934009 B CN104934009 B CN 104934009B
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Abstract
Embodiments of the invention disclose a kind of shift register cell and driving method, shift-register circuit and display device, are related to art of display device manufacture, avoid the problem of multirow occurs while exports before the first frame is opened.The shift register cell includes：Input module, reseting module, control module, the first output control module, the second output control module and feedback module.The embodiment of the present invention is used for display manufacturing.
Description
Technical field
The present invention relates to art of display device manufacture, more particularly to a kind of shift register cell and driving method, displacement to post
Latch circuit and display device.
Background technology
The development of liquid crystal display in the last few years presents high integration, inexpensive development trend.One of which is non-
Often important technology is exactly GOA (English full name：Gate Driver on Array, Chinese：Array base palte row drive) technology
The realization of mass production.Gate switch circuit is integrated on the array base palte of liquid crystal display panel using GOA technologies, so as to
Save grid-driving integrated circuit part, to reduce product cost in terms of material cost and manufacture craft two.It is this to utilize GOA
Gate switch circuit of the Integration ofTechnology on array base palte is also referred to as GOA circuits or shift-register circuit.
Wherein, shift-register circuit includes several shift register cells, each shift register cell corresponding one
Bar grid line, the output end of specific each shift register cell connect a grid line；And one shift register cell output
End connects the input of next shift register cell.Each shift register cell in traditional shift-register circuit is
12TFT (English full name：Thin Film Transistor, Chinese：TFT) 1Cap (Chinese：Electric capacity) knot
Structure, inventor are had found in the structure, because TFT characteristics may change in pyroprocess, are caused before the 1st frame is opened
The problem of multirow occurs while exports.
The content of the invention
Embodiments of the invention provide a kind of shift register cell and driving method, shift-register circuit and display dress
Put, avoid the problem of multirow occurs while exports before the first frame is opened.
To reach above-mentioned purpose, embodiments of the invention adopt the following technical scheme that：
On the one hand, there is provided a kind of shift register cell, including：First input block, the second input block, pull-up are single
Member, drop-down unit, reset unit, output unit and reset cell；
Wherein, first input block connects the first frame start signal end and section point, for by first frame
The signal at initial signal end inputs the section point；
Second input block connection first input end, second clock signal end and first node, for described the
Under the control of one input and second clock signal end, the signal of the first input end is inputted into the first node；
The pull-up unit connects second clock signal end, the 3rd node and the section point, for described
The level of the second clock signal end is inputted into the section point or the 3rd node under the control of second clock signal end；
The drop-down unit connects the second clock signal end, the first node, the section point, the described 3rd
Node, the first level terminal and output end, under the control of the second clock signal end by the letter of first level terminal
Number the output end export；By the signal of first level terminal in the first node under the control of the first node
Exported with the section point；By the signal of first level terminal in the first node under the control of the section point
Exported with the output end；
Reset unit connection reset signal end, first node, the output end and first level terminal, for
The signal of first level terminal is exported in the first node and the output end under the control at the reset signal end；
The output unit connects first node, the first clock signal terminal and the output end；It is described for storing
The level signal of first node, and under the control of the first node by the signal of first clock signal terminal described defeated
Go out end output；
The reset cell connects the second frame start signal end, first level terminal and the output end, in institute
State and export the signal of first level terminal in the output end under the control at the second frame start signal end.
Optionally, first input block includes the 7th transistor；
The grid of 7th transistor connects the first frame start signal end, the first end connection institute of the 7th transistor
The grid of the 7th transistor is stated, the second end of the 7th transistor connects the section point.
Optionally, second input block includes：The first transistor and the 13rd transistor；
The grid of the first transistor connects the first input end, described in the first end connection of the first transistor
The grid of the first transistor, the second end of the first transistor connect the first node；
The grid of 13rd transistor connects the second clock signal end, the first end of the 13rd transistor
The first input end is connected, the second end of the 13rd transistor connects the first node.
Optionally, the pull-up unit includes：5th transistor and the 9th transistor；
The grid of 5th transistor connects the 3rd node, the first end connection of the 5th transistor described the
Two clock signal terminals, the second end of the 5th transistor connect the section point；
The grid of 9th transistor connects the second clock signal end, the first end connection of the 9th transistor
The second clock signal end, the second end of the 9th transistor connect the 3rd node.
Optionally, the drop-down unit includes：6th transistor, the 8th transistor, the tenth transistor, the 11st transistor
With the tenth two-transistor；
The grid of 6th transistor connects the first node, the first end connection of the 6th transistor described the
Two nodes, the second end of the 6th transistor connect first level terminal；
The grid of 8th transistor connects the first node, the first end connection of the 8th transistor described the
Three nodes, the second end of the 8th transistor connect first level terminal；
The grid of tenth transistor connects the section point, the first end connection of the tenth transistor described the
One node, the second end of the tenth transistor connect first level terminal；
The grid of 11st transistor connects the section point, the first end connection institute of the 11st transistor
Output end is stated, the second end of the 11st transistor connects first level terminal；
The grid of tenth two-transistor connects the second clock signal end, the first end of the tenth two-transistor
The output end is connected, the second end of the tenth two-transistor connects first level terminal.
Optionally, the reset unit includes second transistor and the 4th transistor；
The grid of the second transistor connects the reset signal end, described in the first end connection of the second transistor
First node, the second end of the second transistor connect first level terminal；
The grid of 4th transistor connects the reset signal end, described in the first end connection of the 4th transistor
Output end, the second end of the 4th transistor connect first level terminal.
Optionally, the output unit includes, the first electric capacity and third transistor；
First pole of first electric capacity connects the first node, and the second pole of first electric capacity connects the output
End；
The grid of the third transistor connects the first node, the first end connection of the third transistor described the
One clock signal terminal, the second end of the third transistor connect the output end.
Optionally, the reset cell, including：14th transistor；
Grid connection the second frame start signal end of 14th transistor, the first of the 14th transistor
End connects the output end, and the second end of the 14th transistor connects first level terminal.
Optionally, each transistor is the transistor of same type.
On the one hand, there is provided a kind of shift-register circuit, including：At least shift register cell of two-stage cascade, wherein
First order shift register cell is the shift register cell described in any one of above-mentioned offer.
On the one hand, there is provided a kind of display device, including：Above-mentioned shift-register circuit.
On the one hand, there is provided a kind of driving method of shift register cell, including：
First stage, reset cell is under the control at the second frame start signal end by the level of output end and the first level terminal
Pull together；Drop-down unit draws first node and the level of the output end with first level terminal under the control of section point
Together；
Second stage, the first input block is under the control at the first frame start signal end by the letter at the first frame start signal end
Number input section point；Drop-down unit is under the control of second clock signal end by the level of the output end and described the
One level terminal pulls together；Second input block inputs under the control of first input end and second clock signal end by described first
The signal at end inputs the first node；Reset cell described in the first preset period of time in the second stage is in second frame
The level of the output end and first level terminal are pulled together under the control at initial signal end；Output unit storage described first
The level signal of node；
Phase III, the output unit is under the control of the first node by the signal of the first clock signal terminal defeated
Go out end output；Drop-down unit is under the control of the first node by the level and institute of the first node and the section point
The first level terminal is stated to pull together；
Fourth stage, reset unit is under the control at reset signal end by the first node and the level of the output end
Pulled together with first level terminal.
Shift register cell and driving method provided in an embodiment of the present invention, shift-register circuit and display device,
Pass through the first input block, the second input block, pull-up unit, drop-down unit, reset unit, output unit and reset cell control
Make to grid line output drive signal, can be in initial period second compared to reset cell in the embodiment of prior art
The signal of the first level terminal is exported in output end under the control at frame start signal end, it is right before the unlatching of the 1st frame so as to realize
Grid line output drive signal resets, and avoids the problem of multirow occurs while exports before the first frame is opened.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is a kind of schematic diagram of shift register cell provided in an embodiment of the present invention；
Fig. 2 is a kind of schematic diagram for shift register cell that another embodiment of the present invention provides；
Fig. 3 is the driving method indicative flowchart of the real shift register cell for applying example offer of the present invention；
Fig. 4 provides a kind of shift-register circuit schematic diagram for the embodiment of the present invention；
Fig. 5 is the clock signal state signal of each signal end of shift register cell provided in an embodiment of the present invention
Figure.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
The transistor used in all embodiments of the invention can be thin film transistor (TFT) or FET or other characteristics
Identical device, it is mainly switching transistor according to transistor used by effect embodiments of the invention in circuit.By
Source electrode, drain electrode in the switching transistor used here are symmetrical, so its source electrode, drain electrode can exchange.In this hair
In bright embodiment, to distinguish the two poles of the earth of transistor in addition to grid, wherein it will be referred to as first end by source electrode, drain electrode is referred to as the second end.
Provide that the intermediate ends of transistor are grid, signal input part is source electrode, signal output part is drain electrode by the form in accompanying drawing.In addition
Switching transistor includes two kinds of p-type switching transistor and N-type switching transistor used by the embodiment of the present invention, wherein, p-type is opened
Close transistor to turn on when grid be low level, end when grid be high level, it in grid is that height is electric that N-type switching transistor, which is,
Conducts, end when grid is low level.
Shown in reference picture 1, embodiments of the invention provide a kind of shift register cell, including：First input block 11,
Second input block 12, pull-up unit 13, drop-down unit 14, reset unit 15, output unit 16 and reset cell 17；
Wherein, the first input block 11 connection the first frame start signal end STV1 and section point PD, for by the first frame
Initial signal end STV1 signal input section point PD；
Second input block 12 connection first input end INPUT1, second clock signal end CLKB and first node PU, are used
Under the control in first input end INPUT1 and second clock signal end CLKB, first input end INPUT1 signal is inputted
First node PU；
Pull-up unit 13 connects second clock signal end CLKB, the 3rd node PD_CN and section point PD, for second
Second clock signal end CLKB level is inputted into the section point PD or the 3rd node under clock signal terminal CLKB control
PD_CN；
Drop-down unit 14 connect second clock signal end CLKB, first node PU, section point PD, the 3rd node PD_CN,
First level terminal V1 and output end OUT, under second clock signal end CLKB control by the first level terminal V1 signal
Exported in output end OUT；The first level terminal V1 signal is saved in first node PU and second under first node PU control
Point PD is exported；The first level terminal V1 signal is exported in first node PU and output end OUT under section point PD control；
Reset unit 15 connects reset signal end RESET, first node PU, output end OUT and the first level terminal V1, is used for
The first level terminal V1 signal is exported in first node PU and output end OUT under reset signal end RESET control；
Output unit 16 connects first node PU, the first clock signal terminal CLK and output end OUT；For storing first segment
Point PU level signal, and it is under first node PU control that the first clock signal terminal CLK signal is defeated in output end OUT
Go out；
Reset cell 17 connects the second frame start signal end STV2, the first level terminal V1 and output end OUT, for second
The first level terminal V1 signal is exported in output end OUT under frame start signal end STV2 control.
Shift register cell provided in an embodiment of the present invention, it is single by the first input block, the second input block, pull-up
Member, drop-down unit, reset unit, output unit and reset cell are controlled to grid line output drive signal, compared to prior art
Reset cell can be under the control at the second frame start signal of initial period end by the first level terminal in embodiments of the invention
Signal is exported in output end, and grid line output drive signal is resetted before the unlatching of the 1st frame so as to realize, the first frame is avoided and opens
The problem of multirow occurs while exports before opening.
Shown in reference picture 2, the embodiment provides a kind of shift register cell, wherein the first input block 11
Including the 7th transistor M7；
7th transistor M7 grid connects the first frame start signal end STV1, the 7th transistor M7 first end connection the
Seven transistor M7 grid, the 7th transistor M7 the second end connection section point PD.
Second input block 12 includes：The first transistor M1 and the 13rd transistor M13；
The first transistor M1 grid connection first input end INPUT1, the first transistor M1 first end connection first are brilliant
Body pipe M1 grid, the first transistor M1 the second end connection first node PU；
13rd transistor M13 grid connection second clock signal end CLKB, the 13rd transistor M13 first end connect
Meet first input end INPUT1, the 13rd transistor M13 the second end connection first node PU.
Pull-up unit 13 includes：5th transistor M5 and the 9th transistor M9；
5th transistor M5 grid connects the 3rd node PD_CN, the 5th transistor M5 first end connection second clock
Signal end CLKB, the 5th transistor M5 the second end connection section point PD；
9th transistor M9 grid connection second clock signal end CLKB, the 9th transistor M9 first end connection second
Clock signal terminal CLKB, the 9th transistor M9 the second end connect the 3rd node PD_CN.
Drop-down unit 14 includes：6th transistor M6, the 8th transistor M8, the tenth transistor M10, the 11st transistor
M11 and the tenth two-transistor M12；
6th transistor M6 grid connection first node PU, the 6th transistor M6 first end connection section point PD,
6th transistor M6 the second end connects the first level terminal V1；
8th transistor M8 grid connection first node PU, the 8th transistor M8 first end connect the 3rd node PD_
CN, the 8th transistor M8 the second end connect the first level terminal V1；
Tenth transistor M10 grid connection section point PD, the tenth transistor M10 first end connection first node
PU, the tenth transistor M10 the second end connect the first level terminal V1；
11st transistor M11 grid connection section point PD, the 11st transistor M11 first end connection output end
OUT, the 11st transistor M11 the second end connect the first level terminal V1；
Tenth two-transistor M12 grid connection second clock signal end CLKB, the tenth two-transistor M12 first end connect
The second end for meeting output end OUT, the tenth two-transistor M12 connects the first level terminal V1.
Reset unit 15 includes second transistor M2 and the 4th transistor M4；
Second transistor M2 grid connection reset signal end RESET, second transistor M2 first end connection first segment
Point PU, second transistor M2 the second end connect the first level terminal V1；
4th transistor M4 grid connection reset signal end RESET, the 4th transistor M4 first end connection output end
OUT, the 4th transistor M4 the second end connect the first level terminal V1.
Output unit 16 includes, the first electric capacity C1 and third transistor M3；
First electric capacity C1 the first pole connection first node PU, the first electric capacity C1 the second pole connection output end OUT；
Third transistor M3 grid connection first node PU, third transistor M3 first end connect the first clock signal
Hold CLK, third transistor M3 the second end connection output end OUT.
Reset cell 17, including：14th transistor M14；
14th transistor M14 grid connects the second frame start signal end STV2, the 14th transistor M14 first end
The second end for connecting output end OUT, the 14th transistor M14 connects the first level terminal V1.
Optionally, each transistor is the transistor of same type as shown in Figure 2, can so be reduced with limit
The complexity of manufacture craft.
Shift register cell provided in an embodiment of the present invention, it is single by the first input block, the second input block, pull-up
Member, drop-down unit, reset unit, output unit and reset cell are controlled to grid line output drive signal, compared to prior art
Reset cell can be under the control at the second frame start signal of initial period end by the first level terminal in embodiments of the invention
Signal is exported in output end, and grid line output drive signal is resetted before the unlatching of the 1st frame so as to realize, the first frame is avoided and opens
The problem of multirow occurs while exports before opening.
Embodiments of the invention provide a kind of driving method applied to above-mentioned shift register cell, shown in reference picture 3,
Comprise the following steps：
101st, the first stage, reset cell is under the control at the second frame start signal end by the level of output end and the first electricity
Flush end pulls together；Drop-down unit pulls together first node and the level of output end with the first level terminal under the control of section point.
102nd, second stage, the first input block is under the control at the first frame start signal end by the first frame start signal end
Signal input the section point；Drop-down unit is under the control of second clock signal end by the level of output end and the first electricity
Flush end pulls together；Second input block is under the control of first input end and second clock signal end, by the signal of first input end
Input first node；Will output under the control at the second frame start signal end in the first preset period of time reset cell of second stage
The level at end pulls together with first level terminal；Output unit stores the level signal of first node.
103rd, the phase III, output unit is under the control of first node by the signal of the first clock signal terminal in output end
Output；Drop-down unit pulls together the level of first node and section point and the first level terminal under the control of first node.
104th, fourth stage, reset unit is under the control at reset signal end by first node and the level of output end and
One level terminal pulls together.
The driving method of shift register cell provided in an embodiment of the present invention, pass through the first input block, the second input
Unit, pull-up unit, drop-down unit, reset unit, output unit and reset cell are controlled to grid line output drive signal, are compared
Reset cell can be under the control at the second frame start signal of initial period end by the embodiment of prior art
The signal of one level terminal is exported in output end, and grid line output drive signal is resetted before the unlatching of the 1st frame so as to realize, avoided
The problem of first frame occurs multirow while exported before opening.
A kind of shift-register circuit provided in an embodiment of the present invention, at least shift register cell of two-stage cascade.Tool
Body is：Multiple shift register cells including series connection, except first shift register cell and last shift register
Outside unit, the output end of remaining each shift register cell connects the first of next shift register cell adjacent thereto
Input, the signal reset terminal of each shift register cell connect the output of next shift register cell adjacent thereto
End.
Specifically, shift-register circuit as shown in Figure 4, including several shift register cells, wherein shift LD
Device cell S R1 output end OUT1 connection shift register cells SR2 first input end INPUT1 simultaneously connects a grid line
OG1, shift register cell SR1 reset signal end RESET1 and shift register cell SR2 output end OUT2 are connected；Move
Bit register cell S R2 output end OUT2 connection shift register cells SR3 first input end INPUT3 and connection one
Grid line OG2, shift register cell SR2 reset signal end RESET2 and shift register cell SR3 output end OUT3 connect
Connect；Other shift register cells link according to the method, and each shift register cell has first clock in addition
Signal end CLK, a second clock signal end and the first level terminal V1 input, wherein CLK connects system clock with CLKB
Signal, the first level terminal V1 is low level vss or ground connection vdd.In the present embodiment, first shift register cell is displacement
Register cell SR1, then shift register cell SR1 first input end INPUT1 leaves unused, wherein the first frame start signal end
STV1 signal is a sensitizing pulse signal, optional such as frame start signal STV.Wherein SR1 also includes the second frame starting letter
Number end STV2, the signal at the second frame start signal end inputs in advance than the first frame start signal end STV1.
It should be noted that clock signal of system CLOCK is the driving clock of two or more shift register cells
Signal.Shift register cell connects corresponding clock signal as needed, such as first shift register cell first when
Clock signal end CLK connection first systematic clock signals, the second clock signal end CLKB of first shift register cell connect
Connect second clock signal of system；During first clock signal terminal CLK second system of connection of second shift register cell
Clock signal, the second clock signal end CLKB connection first systematic clock signals of second shift register cell；3rd
First clock signal terminal CLK connection first systematic clock signals of shift register cell, the 3rd shift register cell
Second clock signal end CLKB second clock signal of system of connection；First clock signal of the 4th shift register cell
Hold CLK second clock signal of system of connection, the second clock signal end CLKB connections first of the 4th shift register cell
Individual clock signal of system；So circulation later；Or other can cause the connected mode of shift register cell normal work.
Wherein, the clock signal state diagram of each signal end shown in reference picture 5, the shifting that Fig. 2 above-mentioned to the application is provided
The operation principle of bit register unit is described as follows：
First stage, STV1=0, STV2=1, INPUT=0, V1=0, CLK=1, CLKB=0, OUT=0, RESET=
0；M14 is turned on, other each transistor cutoffs, PU=0, PD=0, PD_CN=0.It should be noted that in following examples,
" 0 " represents low level；" 1 " represents high level.The stage because M14 is turned on, OUT and V1 level is pulled together, avoid first
The forward direction the first row grid line output signal of frame unlatching.
Second stage, STV1=1, the STV2 preset time in second stage o'clock are 0, INPUT=0, V1=by 1 saltus step
0, CLK=0, CLKB=1, OUT=0, RESET=0；The stage, M13 conductings are charged for PU nodes；M7 conductings are filled for PD nodes
Electricity；M3, M5, M6, M8, M9, M12 are turned on, and M1, M2, M4, M10, M11 cut-off, M14 turn in the first time period of second stage,
End in second time period., wherein it is desired to explanation be as first order shift register cell because first input end leaves unused,
Therefore INPUT=0；As the shift register cell after the second level, moved because first input end connects adjacent upper level
The output end of bit register unit, therefore its INPUT=1；Now M1 is turned on.
Phase III, STV1=0, STV2=0, INPUT=0, V1=0, CLK=1, CLKB=0, OUT=1, RESET=
0；The stage, M1, M2, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14 cut-off, M3 conductings.
Fourth stage, STV1=0, STV2=0, INPUT=0, V1=0, CLK=0, CLKB=1, OUT=0, RESET=
1；The stage, M1, M3, M6, M8, M14 cut-off, other each transistor turns.
One embodiment of the invention provides a kind of display device, including any shift-register circuit in above-described embodiment.
In addition, display device can be：Electronic Paper, mobile phone, tablet personal computer, television set, display, notebook computer, number
Any product or part with display function such as code-phase frame, navigator.
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, change or replacement can be readily occurred in, should all be contained
Cover within protection scope of the present invention.Therefore, protection scope of the present invention described should be defined by scope of the claims.
Claims (12)
- A kind of 1. shift register cell, it is characterised in that including：First input block, the second input block, pull-up unit, Drop-down unit, reset unit, output unit and reset cell；Wherein, first input block connects the first frame start signal end and section point, for first frame to be originated The signal of signal end inputs the section point；Second input block connection first input end, second clock signal end and the first node, for defeated described first Under the control for entering end and second clock signal end, the signal of the first input end is inputted into the first node；The pull-up unit connects second clock signal end, the 3rd node and the section point, for described second The level of the second clock signal end is inputted into the section point or the 3rd node under the control of clock signal terminal；The drop-down unit connects the second clock signal end, first node, the section point, described Section three Point, the first level terminal and output end, under the control of the second clock signal end by the signal of first level terminal Exported in the output end；Under the control of the first node by the signal of first level terminal in the first node and The section point output；Under the control of the section point by the signal of first level terminal in the first node and The output end output；Reset unit connection reset signal end, first node, the output end and first level terminal, for described The signal of first level terminal is exported in the first node and the output end under the control at reset signal end；The output unit connects first node, the first clock signal terminal and the output end；For storing described first The level signal of node, and under the control of the first node by the signal of first clock signal terminal in the output end Output；The reset cell connects the second frame start signal end, first level terminal and the output end, for being opened in the 1st frame The signal of first level terminal is exported in the output end under the control at the second frame start signal end before opening；Its In, when the shift register cell is as first order shift register cell in shift-register circuit, described first is defeated It is idle to enter end；The shift register cell is as the shift register list after the second level in the shift-register circuit When first, the first input end connects the output end of adjacent upper level shift register cell.
- 2. shift register cell according to claim 1, it is characterised in that it is brilliant that first input block includes the 7th Body pipe；The grid of 7th transistor connects the first frame start signal end, the first end connection of the 7th transistor described the The grid of seven transistors, the second end of the 7th transistor connect the section point.
- 3. shift register cell according to claim 1, it is characterised in that second input block includes：First Transistor and the 13rd transistor；The grid of the first transistor connects the first input end, the first end connection described first of the first transistor The grid of transistor, the second end of the first transistor connect the first node；The grid of 13rd transistor connects the second clock signal end, the first end connection of the 13rd transistor The first input end, the second end of the 13rd transistor connect the first node.
- 4. shift register cell according to claim 1, it is characterised in that the pull-up unit includes：5th crystal Pipe and the 9th transistor；The grid of 5th transistor connects the 3rd node, when the first end of the 5th transistor connects described second Clock signal end, the second end of the 5th transistor connect the section point；The grid of 9th transistor connects the second clock signal end, described in the first end connection of the 9th transistor Second clock signal end, the second end of the 9th transistor connect the 3rd node.
- 5. shift register cell according to claim 1, it is characterised in that the drop-down unit includes：6th crystal Pipe, the 8th transistor, the tenth transistor, the 11st transistor and the tenth two-transistor；The grid of 6th transistor connects the first node, first end connection second section of the 6th transistor Point, the second end of the 6th transistor connect first level terminal；The grid of 8th transistor connects the first node, described Section three of the first end connection of the 8th transistor Point, the second end of the 8th transistor connect first level terminal；The grid of tenth transistor connects the section point, and the first end of the tenth transistor connects the first segment Point, the second end of the tenth transistor connect first level terminal；The grid of 11st transistor connects the section point, and the first end connection of the 11st transistor is described defeated Go out end, the second end of the 11st transistor connects first level terminal；The grid of tenth two-transistor connects the second clock signal end, the first end connection of the tenth two-transistor The output end, the second end of the tenth two-transistor connect first level terminal.
- 6. shift register cell according to claim 1, it is characterised in that the reset unit includes second transistor With the 4th transistor；The grid of the second transistor connects the reset signal end, the first end connection described first of the second transistor Node, the second end of the second transistor connect first level terminal；The grid of 4th transistor connects the reset signal end, and the first end of the 4th transistor connects the output End, the second end of the 4th transistor connect first level terminal.
- 7. shift register cell according to claim 1, it is characterised in that the output unit includes, the first electric capacity And third transistor；First pole of first electric capacity connects the first node, and the second pole of first electric capacity connects the output end；The grid of the third transistor connects the first node, when the first end of the third transistor connects described first Clock signal end, the second end of the third transistor connect the output end.
- 8. shift register cell according to claim 1, it is characterised in that the reset cell, including：14th is brilliant Body pipe；The grid of 14th transistor connects the second frame start signal end, and the first end of the 14th transistor connects The output end is connect, the second end of the 14th transistor connects first level terminal.
- 9. according to the shift register cell described in claim any one of 2-8, it is characterised in that each transistor is mutually similar The transistor of type.
- A kind of 10. shift-register circuit, it is characterised in that including：At least shift register cell of two-stage cascade, wherein the One-level shift register cell is the shift register cell described in claim 1-9 any one.
- A kind of 11. display device, it is characterised in that including：Shift-register circuit described in claim 10.
- It is 12. a kind of such as the driving method of claim 1-9 any one shift register cells, it is characterised in that including：First stage, reset cell draw the level of output end and the first level terminal under the control at the second frame start signal end Together；Drop-down unit draws first node and the level of the output end with first level terminal under the control of section point Together；Second stage, the first input block are defeated by the signal at the first frame start signal end under the control at the first frame start signal end Enter the section point；Drop-down unit is under the control of second clock signal end by the level of the output end and the described first electricity Flush end pulls together；Second input block is under the control of first input end and second clock signal end, by the first input end Signal inputs the first node；Reset cell described in the first preset period of time in the second stage originates in second frame The level of the output end and first level terminal are pulled together under the control of signal end；Output unit stores the first node Level signal；Phase III, the output unit is under the control of the first node by the signal of the first clock signal terminal in output end Output；Drop-down unit is under the control of the first node by the level of the first node and the section point and described the One level terminal pulls together；Fourth stage, reset unit is under the control at reset signal end by the level and institute of the first node and the output end The first level terminal is stated to pull together.
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| CN201510401027.6A CN104934009B (en) | 2015-07-09 | 2015-07-09 | Shift register cell and driving method, shift-register circuit and display device |
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| CN105185339B (en) | 2015-10-08 | 2017-12-29 | 京东方科技集团股份有限公司 | Shift register cell, grid line drive device and driving method |
| CN105609040A (en) * | 2016-03-22 | 2016-05-25 | 京东方科技集团股份有限公司 | Shift register unit, shift register and method, driving circuit and display device |
| CN105761658A (en) * | 2016-05-12 | 2016-07-13 | 京东方科技集团股份有限公司 | Shifting register and drive method thereof, gate drive circuit and display device |
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| CN102654986A (en) * | 2011-11-25 | 2012-09-05 | 京东方科技集团股份有限公司 | Shift register electrode, grid electrode driver, array substrate and display device |
| CN102708778B (en) * | 2011-11-28 | 2014-04-23 | 京东方科技集团股份有限公司 | Shift register and drive method thereof, gate drive device and display device |
| CN102915698B (en) * | 2012-10-18 | 2016-02-17 | 京东方科技集团股份有限公司 | Shift register cell, gate driver circuit and display device |
| CN102956186A (en) * | 2012-11-02 | 2013-03-06 | 京东方科技集团股份有限公司 | Shift register, grid drive circuit and liquid crystal display |
| KR102003439B1 (en) * | 2012-12-18 | 2019-07-24 | 엘지디스플레이 주식회사 | Gate shift register and display device using the same |
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