CN104917592A - Error detection and error correction circuit for data with 10-bit wide - Google Patents
Error detection and error correction circuit for data with 10-bit wide Download PDFInfo
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- CN104917592A CN104917592A CN201510320976.1A CN201510320976A CN104917592A CN 104917592 A CN104917592 A CN 104917592A CN 201510320976 A CN201510320976 A CN 201510320976A CN 104917592 A CN104917592 A CN 104917592A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
- H04L1/009—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location arrangements specific to transmitters
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
- H04L1/0091—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location arrangements specific to receivers, e.g. format detection
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Error Detection And Correction (AREA)
Abstract
The invention discloses an error detection and error correction circuit for data with 10-bit wide. The circuit comprises 4 six-input exclusive-OR gates for coding original 10-bit data and generating 4 data coding bits; 4 seven-bit exclusive-OR gates for detecting error of the wrong data so as to determine whether the original data is wrong and determine the position of the wrong data bit; 10 four-input AND gates for generating the data with 10-bit wide; 10 two-input exclusive-OR gates for placing the wrong data bit at 1 and placing the correct data bit at 0, and performing XOR to the 10-bit data generated by the 10 four-input AND gates and 10 bits in the wrong data so as to negate after performing XOR to the wrong data bit and 1 and hold the original value after performing the XOR to the correct data and 0. The circuit is simple in principle, and compact in structure. The circuit of the invention has significant advantages of error detection and error correction.
Description
Technical field
The present invention relates to electronic information technical field, particularly relate to a kind of circuit structure that can carry out EDC error detection and correction for the data after transmission.
Background technology
Along with the development of science and technology, people have been in the information data epoch, at every moment all will come into contacts with data, and this just be unable to do without the transmission of data.And in the process of transfer of data, owing to there is various interference in channel, mistake can occur data, namely the data of receiving terminal reception are different with the data that transmitting terminal sends, and this can bring extremely bad impact to the reliability of data and authenticity.For this reason, data error detection becomes the focus of research, many error detection circuits are had in prior art, such as based on the circuit structure of parity check principle, whether this circuit can only detect data and make a mistake, once initial data makes a mistake, then this circuit can determine the position that data make a mistake, but can not carry out error correction to the data made a mistake, can only require that transmitting terminal resends an initial data again, this will reduce data transmission efficiency and Information Security.
Summary of the invention
For problems of the prior art, the present invention proposes the circuit that a kind of data that are 10 to bit wide carry out EDC error detection and correction, once initial data makes a mistake, then this circuit can be determined the position that data make a mistake and be corrected, this circuit theory is simple, structure is simplified, and possesses the function of EDC error detection and correction simultaneously, has great advantage.
In order to solve the problems of the technologies described above, a kind of data that are 10 to bit wide that the present invention proposes carry out the circuit of EDC error detection and correction, comprise coding circuit and error correction circuit; Described coding circuit comprises the XOR gate of 4 six inputs, is used for realizing the coding to original 10 bit data, produces 4 data bits of coded; Described error correction circuit comprise 4 seven input XOR gate, 10 four input with door and 10 two XOR gate inputted; The XOR gate of described 4 seven inputs is used for realizing carrying out error detection to the data bit made a mistake, thus determines whether initial data makes a mistake, and the position of the data bit made a mistake; Described 10 four input be used for producing the data that bit wide is 10 with door, the Data Position 1 that it will make a mistake, the Data Position 0 do not made a mistake; The XOR gate of described 10 two inputs 10 of being used in 10 bit data produced with door that input above-mentioned 10 four and the present data made a mistake carry out XOR, negate after making the data bit that makes a mistake and 1 XOR, keeps initial value after the data bit do not made a mistake and 0 XOR.
Compared with prior art, the invention has the beneficial effects as follows:
To the circuit that the data that bit wide is 10 carry out EDC error detection and correction, the present invention not only can judge whether data make mistakes, and can correct the data of makeing mistakes, to return to initial data.This circuit can be realized by gate circuit, only needs 18 XOR gate, and 10 just can realize the function of EDC error detection and correction with door.Method is simple, convenient operation.
Accompanying drawing explanation
Fig. 1 is the circuit frame figure that the present invention has error detecting and error correcting function;
Fig. 2 is to the coding circuit that initial data is encoded in circuit of the present invention;
Fig. 3 is the error correction circuit in the present invention with error detecting and error correcting function;
Fig. 4 is the circuit had misdata positioning function in left side in Fig. 3;
Fig. 5 is the circuit with error correction on right side in Fig. 3.
Embodiment
Be described in further detail technical solution of the present invention below in conjunction with the drawings and specific embodiments, described specific embodiment only explains the present invention, not in order to limit the present invention.
As shown in Figure 1, the mentality of designing that the data that the present invention is a kind of is 10 to bit wide carry out the circuit of EDC error detection and correction is: input is a bit wide is the initial data of 10, the function of coding circuit is that initial data coding extension is become 14 bit data, it is the transmission channel-channel of data between coding circuit and error correction circuit, data may make a mistake when transmitting, the function of error correction circuit positions and error correction misdata position, and output is 10 initial data after error correction completes.
The circuit that the data that the present invention is a kind of is 10 to bit wide carry out EDC error detection and correction comprises coding circuit and error correction circuit; Described coding circuit comprises the XOR gate of 4 six inputs; Described error correction circuit comprise 4 seven input XOR gate, 10 four input with door and 10 two XOR gate inputted.
As shown in Figure 2, the XOR gate of described 4 six inputs is used for realizing the coding to original 10 bit data, produce 4 data bits of coded, wherein original [1:10] represents 10 initial data, after bianma [1:14] presentation code, bit wide is the data of 14, and Xor1, Xor2, Xor3 and Xor4 are the XOR gate of 4 six inputs.
Fig. 3 corresponds to the error correction circuit in Fig. 1, wherein Vin [1:14] represents 14 bit data of having made mistakes, Xor5, Xor6, Xor7 and Xor8 are the XOR gate of 4 seven inputs, be used for realizing the error detection function to the data bit made a mistake, it can determine whether initial data makes a mistake, and the position of the data bit made a mistake.In Fig. 3, left side has the circuit of misdata positioning function is locate the data bit made a mistake, and generate 10 bit data, as shown in Figure 4, what adopt 10 four to input is used for producing the data that bit wide is 10 with door, the Data Position 1 that it will make a mistake, the Data Position 0 do not made a mistake.In Fig. 3, the circuit with error correction on right side is that 10 bit data just produced and the data made a mistake are done 10 XOR process, as shown in Figure 5,10 in 10 bit data produced with door adopting 10 two XOR gate inputted to be used for above-mentioned 10 four to input and the present data made a mistake are carried out XOR, will negate after the data bit made a mistake like this and 1 XOR, and keep initial value after the data bit do not made a mistake and 0 XOR, so just achieve the function of data being carried out to EDC error detection and correction.
Circuit of the present invention can carry out error detection and correction to data, by inserting 4 data bit in initial data, and the information in initial data is deposited in these 4 data bit, such initial data has just been extended to 14, once data change, just can be judged the position that error data occurs by 4 newly-increased data bit, and be returned to primary data.
In bit wide be the initial data of 10 basis on (D1_D2_D3_D4_D5_D6_D7_D8_D9_D10), newly-increased 4 data bit (H1_H2_H3_H4), the information in initial data is stored with it, and this 14 bit data is resequenced---newly-increased 4 lay respectively at the 1st, 2,4,8, and 10 initial data sort (H1_H2_D1_H3_D2_D3_D4_H4_D5_D6_D7_D8_D9_D10) successively.The XOR (D1^D2^D4^D5^D7^D9) of initial data the 1st, 2,4,5,7,9 that what the 1st newly-increased bit data (H1) stored is; The XOR (D1^D3^D4^D6^D7^D10) of initial data the 1st, 3,4,6,7,10 that what the 2nd newly-increased bit data (H2) stored is; The XOR (D2^D3^D4^D8^D9^D10) of initial data the 2nd, 3,4,8,9,10 that what the 3rd newly-increased bit data (H3) stored is; The XOR (D5^D6^D7^D8^D9^D10) of initial data the 5th, 6,7,8,9,10 that what the 4th newly-increased bit data (H4) stored is.
When this bit wide is the transfer of data of 14, due to the impact of channel noise, cause a certain position in data may change (becoming h1_h2_d1_h3_d2_d3_d4_h4_d5_d6_d7_d8_d9_d10), at this moment can do 4 XOR process to present data, first time is treated to the 1st of present data, 3,5,7,9, the XOR (C1=h1^d1^d2^d4^d5^d7^d9) of 11,13; Second time is treated to the XOR (C2=h2^d1^d3^d4^d6^d7^d10) of the 2nd, 3,6,7,10,11,14 of present data; Be treated to the XOR (C3=h3^d2^d3^d4^d8^d9^d10) of the 4th, 5,6,7,12,13,14 of present data for the third time; Be treated to the 8th, 9,10 of present data for 4th time, the XOR (C4=h4^d5^d6^d7^d8^d9^d10) of 11,12,13,14.Now can pass through to judge that the size (C4_C3_C2_C1) of 4 bits be made up of C4, C3, C2 and C1 determines the data bit whether initial data makes a mistake and make a mistake---when its size is 0, represent that initial data does not make a mistake; When its size non-zero, its value indicates the data bit made a mistake, such as size is 6 (C4_C3_C2_C1=0110), then represent the 6th d3 (the 3rd of namely initial data of present data, D3) make a mistake, size is 8 (C4_C3_C2_C1=1000), then represent that the 8th bit data h4 (H4) makes a mistake, but 10 original bit data do not make a mistake.
When detecting that initial data makes a mistake, the data that another bit wide is 10 can be set, the data bit made a mistake is set to 1, remainder data position is set to 0,6th make mistakes (i.e. initial data the 3rd) of such as present data, can arrange this 10 bit data is 00_1000_0000, then itself and existing 10 valid data positions (d1_d2_d3_d4_d5_d6_d7_d8_d9_d10) are in the data carried out XOR process.Just initial data can be obtained, namely to error correction success.
Although invention has been described by reference to the accompanying drawings above; but the present invention is not limited to above-mentioned embodiment; above-mentioned embodiment is only schematic; instead of it is restrictive; those of ordinary skill in the art is under enlightenment of the present invention; when not departing from present inventive concept, can also make a lot of distortion, these all belong within protection of the present invention.
Claims (1)
1. the data being 10 to bit wide carry out a circuit for EDC error detection and correction, it is characterized in that:
Comprise coding circuit and error correction circuit;
Described coding circuit comprises the XOR gate of 4 six inputs, is used for realizing the coding to original 10 bit data, produces 4 data bits of coded;
Described error correction circuit comprise 4 seven input XOR gate, 10 four input with door and 10 two XOR gate inputted;
The XOR gate of described 4 seven inputs is used for realizing carrying out error detection to the data bit made a mistake, thus determines whether initial data makes a mistake, and the position of the data bit made a mistake;
Described 10 four input be used for producing the data that bit wide is 10 with door, by the Data Position 1 made a mistake, the Data Position 0 do not made a mistake;
The XOR gate of described 10 two inputs 10 of being used in 10 bit data produced with door that input above-mentioned 10 four and the present data made a mistake carry out XOR, negate after making the data bit that makes a mistake and 1 XOR, keeps initial value after the data bit do not made a mistake and 0 XOR.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510320976.1A CN104917592A (en) | 2015-06-11 | 2015-06-11 | Error detection and error correction circuit for data with 10-bit wide |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510320976.1A CN104917592A (en) | 2015-06-11 | 2015-06-11 | Error detection and error correction circuit for data with 10-bit wide |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108242973A (en) * | 2016-12-26 | 2018-07-03 | 北京邮电大学 | A kind of data error-correcting method and device |
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| CN101366183A (en) * | 2005-09-28 | 2009-02-11 | Ati技术公司 | Method and apparatus for error management |
| CN103309766A (en) * | 2013-06-20 | 2013-09-18 | 中国科学院微电子研究所 | Error correction method of cyclic hamming code based on parallel coding and decoding |
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| CN101366183A (en) * | 2005-09-28 | 2009-02-11 | Ati技术公司 | Method and apparatus for error management |
| CN103309766A (en) * | 2013-06-20 | 2013-09-18 | 中国科学院微电子研究所 | Error correction method of cyclic hamming code based on parallel coding and decoding |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108242973A (en) * | 2016-12-26 | 2018-07-03 | 北京邮电大学 | A kind of data error-correcting method and device |
| CN108242973B (en) * | 2016-12-26 | 2020-10-27 | 北京邮电大学 | Data error correction method and device |
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Application publication date: 20150916 |
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