CN104916624A - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
CN104916624A
CN104916624A CN201410448445.6A CN201410448445A CN104916624A CN 104916624 A CN104916624 A CN 104916624A CN 201410448445 A CN201410448445 A CN 201410448445A CN 104916624 A CN104916624 A CN 104916624A
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CN
China
Prior art keywords
mentioned
chip
wiring layer
resin bed
layer
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Granted
Application number
CN201410448445.6A
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Chinese (zh)
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CN104916624B (en
Inventor
栗田洋一郎
江泽弘和
河崎一茂
筑山慧至
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japanese Businessman Panjaya Co ltd
Kioxia Corp
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Toshiba Corp
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Priority to CN201811248184.8A priority Critical patent/CN109390326B/en
Publication of CN104916624A publication Critical patent/CN104916624A/en
Application granted granted Critical
Publication of CN104916624B publication Critical patent/CN104916624B/en
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    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention provides a semiconductor device which has the characteristics of low cost and high reliability, and a method for manufacturing same. A first resin layer is provided on the first face of an upper layer chip. A first wiring layer is arranged in the first resin layer, and is electrically connected to the upper layer chip. A second resin layer is arranged on a surface side of the first resin layer, and extends into a chip outside region closer to the outside compared with the side surface of the upper layer chip. A second wiring layer is arranged in the second resin layer, is connected to the first wiring layer, and extends to the chip outside region. A lower layer is mounted on the surface side of the first resin layer, and is connected to the first wiring layer.

Description

Semiconductor device and manufacture method thereof
The application advocates the priority of application based on No. 2014-51235, Japanese patent application (applying date: on March 14th, 2014).The application comprises the full content of basis application by referring to the application of this basis.
Technical field
The present invention relates to semiconductor device and manufacture method thereof.
Background technology
The duplexer of known multiple chips that will be connected by TSV (Through-Silicon Via, silicon through hole) carries out to circuit board the packaging structure that salient point (bump) connects.In addition, in such configuration, the structure connected by TSV by interface chip (interface chip) for multiple memory chip is also proposed.
Summary of the invention
Embodiments of the present invention provide a kind of low cost and the high semiconductor device of reliability and manufacture method thereof.
According to execution mode, semiconductor device possesses upper strata chip, the 1st resin bed, the 1st wiring layer, the 2nd resin bed, the 2nd wiring layer, lower layer chip and sealing resin.Above-mentioned upper strata chip has the 2nd of the opposition side of the 1st and above-mentioned 1st.Above-mentioned 1st resin bed is arranged on above-mentioned 1st of above-mentioned upper strata chip.Above-mentioned 1st wiring layer is arranged in above-mentioned 1st resin bed, connects with above-mentioned upper strata chip electrical.Above-mentioned 2nd resin bed is arranged on the face side of above-mentioned 1st resin bed, and expands to the side chip exterior domain in the outer part than above-mentioned upper strata chip.Above-mentioned 2nd wiring layer is arranged in above-mentioned 2nd resin bed, is connected, extends to said chip exterior domain with above-mentioned 1st wiring layer.Above-mentioned lower layer chip is arranged on the above-mentioned face side of above-mentioned 1st resin bed, is connected with above-mentioned 1st wiring layer.Above-mentioned upper strata chip covers by above-mentioned sealing resin.
Accompanying drawing explanation
Fig. 1 is the constructed profile of the semiconductor device of execution mode.
Fig. 2 is the constructed profile of the semiconductor device of execution mode.
(a) and (b) of Fig. 3 is the constructed profile of the semiconductor device of execution mode.
Fig. 4 is the constructed profile of the semiconductor device of execution mode.
(a) and (b) of Fig. 5 is the constructed profile of the semiconductor device of execution mode.
(a) ~ (c) of Fig. 6 is the constructed profile of the manufacture method of the semiconductor device representing execution mode.
(a) ~ (c) of Fig. 7 is the constructed profile of the manufacture method of the semiconductor device representing execution mode.
(a) ~ (c) of Fig. 8 is the constructed profile of the manufacture method of the semiconductor device representing execution mode.
Fig. 9 is the constructed profile of the manufacture method of the semiconductor device representing execution mode.
Figure 10 is the constructed profile of the manufacture method of the semiconductor device representing execution mode.
Figure 11 is the constructed profile of the manufacture method of the semiconductor device representing execution mode.
Figure 12 is the constructed profile of the manufacture method of the semiconductor device representing execution mode.
Figure 13 is the constructed profile of the manufacture method of the semiconductor device representing execution mode.
Figure 14 is the constructed profile of the manufacture method of the semiconductor device representing execution mode.
(a) and (b) of Figure 15 is the schematic diagram of the annexation of the multiple chips represented in the semiconductor device of execution mode.
Figure 16 is the constructed profile of the semiconductor device of execution mode.
(a) and (b) of Figure 17 is the constructed profile of the semiconductor device of execution mode.
Embodiment
Below, with reference to accompanying drawing, execution mode is described.In addition, in each accompanying drawing, give identical label to identical key element.
Fig. 1 is the constructed profile of the semiconductor device of execution mode.
The semiconductor device of execution mode has upper strata chip and the Wiring structure portion for making upper strata chip be connected with external circuit.Upper strata chip comprises such as memory chip.
In the example depicted in figure 1, upper strata chip has 1 memory chip 11.Memory chip 11 has semiconductor layer 12.
Semiconductor layer 12 is such as silicon substrates.Or semiconductor layer 12 is the silicon layers in SOI (Silicon On Insulator: silicon-on-insulator) structure.In addition, semiconductor layer 12 also can be the layer (substrate) of such as SiC, GaN etc. beyond silicon.In the following description, semiconductor layer 12 is set to silicon substrate and is described.
Silicon substrate 12 has the 2nd 12b of the 1st (circuit face) 12a and its opposition side.The semiconductor integrated circuit comprising not shown transistor etc. is formed at the 1st 12a.1st 12a is formed with charge accumulation layer, control electrode etc.In addition, on the 1st 12a, (on chip) wiring layer 13 on the sheet that is connected with semiconductor integrated circuit, control electrode is provided with.
Such as, as shown in (b) of Fig. 3 described later, on sheet between wiring layer 13 and the 1st 12a, on sheet, wiring layer 13 is each other and on the sheet of the superiors on wiring layer 13, is provided with interlayer insulating film 14.
Interlayer insulating film 14 is the dielectric films using silicon as basic comprising, such as, what comprise in silica (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon-carbon nitrogen (SiCN), silicon oxide carbide (SiOC) is at least a certain.
The 1st resin bed 30 is provided with in the 1st 12a side of memory chip 11.1st resin bed 30 is to arrange the mode of the surface coverage of wiring layer 13 on the sheet of memory chip 11.
In the 1st resin bed 30 and the face side of the 1st resin bed 30, be provided with the 1st wiring layer 32.1st wiring layer 32 by through for the 1st resin bed 30, and is connected with wiring layer 13 on the sheet of memory chip 11.Thus, the 1st wiring layer 32 is electrically connected with memory chip 11.1st resin bed 30 insulate between the 1st wiring layer 32.1st wiring portion comprises the 1st resin bed 30 and the 1st wiring layer 32.
1st resin bed 30 and the 1st wiring layer 32 are located at and the 1st of memory chip 11 the region that 12a is opposed, and are not formed in chip exterior domain (region in the outer part, side than memory chip 11).1st wiring layer 32 is by winding so-called fan-in (fan-in in the region overlapping with chip; Japanese: Off ァ Application イ Application) wiring layer (RDL:Redistribution Layer) again.
The 2nd resin bed 41 is provided with in the face side of the 1st resin bed 30.2nd resin bed 41 from the 1st region that 12a is opposed of memory chip 11, expand to the side chip exterior domain in the outer part than memory chip 11 and formed.
In the 2nd resin bed 41 and the face side of the 2nd resin bed 41 be provided with the 2nd wiring layer 42.2nd wiring layer 42 is connected with the 1st wiring layer 32 and expands to chip exterior domain and formed.2nd wiring layer 42 is so-called fan-out (fan-out; Japanese: Off ァ Application ア ウ ト) wiring layer (RDL:Redistribution Layer) again.2nd resin bed 41 insulate between the 2nd wiring layer 42.2nd wiring portion comprises the 2nd resin bed 41 and the 2nd wiring layer 42.
1st wiring layer 32 and the 2nd wiring layer 42 are such as formed by containing the metal material of copper as principal component.
1st resin bed 30 and the 2nd resin bed 41 are formed primarily of the high-molecular organic material taking carbon as basic comprising, such as, comprise polyimide resin, PBO (polybenzoxazoles: polybenzoxazole) resin, epoxy resin, silicones, BCB (benzocyclobutene: benzocyclobutene) resin as principal component.
Multiple outside terminal 52 is configured with in the face side of the 2nd resin bed 41.Outside terminal 52 is such as the conductivity such as solder ball, metal salient point salient point.Outside terminal 52 is connected with the 2nd wiring layer 42.
Be formed at the semiconductor integrated circuit of memory chip 11, memory component is electrically connected with the 2nd wiring layer 42 via wiring layer on sheet 13 and the 1st wiring layer 32.Further, via the outside terminal 52 be connected with the 2nd wiring layer 42, memory chip 11 can be connected with external circuit.
The side of memory chip 11 and the 2nd (upper surface) 12b are covered by sealing resin 80.Sealing resin 80 is expanding on the 2nd resin bed 41 of chip exterior domain, is covered the side of the side of memory chip 11 and the 1st resin bed 30.
In addition, according to execution mode, except memory chip 11, logic chip 70 is possessed as lower layer chip.Logic chip (logic chip) 70 is installed in surface (face of the opposition side in the face be connected with wiring layer on the sheet 13) side of the 1st resin bed 30, is connected with the 1st wiring layer 32.That is, in a face of the 1st resin bed 30, the memory chip 11 as upper strata chip is installed, in another face of the 1st resin bed 30, the logic chip 70 as lower layer chip is installed.Here, " upper strata " " lower floor " represents the relative position relationship clamped by the 1st resin bed 30, instead of represents the upper and lower meaning for gravity direction.
Logic chip 70 is IF (interface, interface)/controller chips of control storage chip 11.
Be provided with wiring layer 71 on sheet in a face of logic chip 70, on this sheet, wiring layer 71 engages with the weld zone 32a of the 1st wiring layer 32 via conductivity salient point (such as solder ball, metal salient point etc.) 72.
2nd resin bed 41 is not formed in whole of the 1st resin bed 30.The side, face of the opposition side in the face be connected with memory chip 11 in the 1st resin bed 30, have the region (peristome) not forming the 2nd resin bed 41 and the 2nd wiring layer 42, in this region, (peristome) is configured with logic chip 70.At this peristome, be filled with sealing resin 73 in the mode covered at the junction surface between salient point 72 and the weld zone 32a of the 1st wiring layer 32.
Multiple weld zone 32a of the 1st wiring layer 32, with the spacing roughly the same with the spacing at the junction surface between wiring layer on sheet 13 and the 1st wiring layer 32, are configured in the installed surface of the logic chip 70 in the 1st resin bed 30.
The minimum spacing (spacing of salient point 72) of the connecting portion between the weld zone 32a of logic chip 70 and the 1st wiring layer 32 is less than the minimum spacing of the connecting portion between the outside weldings district 42a of the 2nd wiring layer 42 and outside terminal 52.In addition, the minimum spacing of the connecting portion between logic chip 70 and the 1st wiring layer 32 is less than the minimum spacing of the connecting portion between the 1st wiring layer 32 and the 2nd wiring layer 42.
1st wiring layer 32 has: the thin space weld zone corresponding with the fine wires design of wiring layer 13,71 on the sheet of memory chip 11 and logic chip 70; And the weld zone (and the junction surface between the 2nd wiring layer 42) to arrange accordingly with the spacing of outside terminal 52.
That is, the minuteness space electrode pad of the chip-scale of memory chip 11 and logic chip 70 is via the 1st wiring layer 32 and the 2nd wiring layer 42, expands to and is suitable for carrying out the spacing of installing to printed wiring board etc.
Logic chip 70 is configured in the region immediately below memory chip 11, connects via the 1st wiring layer 32 pairs of memory chip 11 salient points.In addition, logic chip 70 is electrically connected with outside terminal 52 via the 1st wiring layer 32 and the 2nd wiring layer 42.At the same face of the 1st resin bed 30, be provided with logic chip 70 and the 2nd wiring layer 42 for the connection with outside.
It not the structure clamping logic chip between printed circuit board (plug-in type (interposer) substrate) and memory chip.Thus, when logic chip 70 being connected to memory chip 11 and these both sides of external circuit, TSV (through electrode) can not be used.Thus, according to execution mode, low cost can be provided and the high semiconductor device of reliability.
Fig. 2 is the constructed profile of other examples of the semiconductor device representing execution mode.
In the example shown in Fig. 2, memory chip portion has the duplexer of multiple memory chip 11.Exemplified with by structure stacked for such as 4 memory chips 11 in Fig. 2, but the stacked number of memory chip 11 is arbitrary.Multiple memory chip 11 is chips that thickness, planar dimension, the layer structure of thickness direction and material etc. are identical.
At the 1st 12a of each memory chip 11, be provided with wiring layer 13 on sheet in the same manner as above-mentioned execution mode.
Each memory chip 11 is electrically connected via through electrode 18 and salient point (such as solder ball, metal salient point) 31 each other.
Wiring layer 13 on the sheet being formed in the 1st 12a, by through for silicon substrate 12, is connected with the backplate being formed in the 2nd 12b by through electrode 18.
Except by the memory chip 11 except (undermost) memory chip 11 of resin bed 30 side, make wiring layer 13 on its sheet opposed with the 2nd 12b of the memory chip 11 of below and be laminated on the memory chip 11 of below.
Salient point 31 on the sheet of the backplate (through electrode 18) of the memory chip 11 of below and the memory chip 11 of top between wiring layer 13, and engages with wiring layer 13 on the sheet of the backplate of the memory chip 11 of below and the memory chip 11 of top.
Be filled with sealing resin 85 between memory chip 11 and memory chip 11, the periphery of salient point 31 covers by sealing resin 85.
Apart from resin bed 30 farthest, be provided with metallic plate 82 on the memory chip 11 of the superiors.As described later, metallic plate 82 as by multiple memory chip 11 and the 1st resin bed 30 stacked time supporter use.Finally, metallic plate 82 can remove.In addition, when retaining metallic plate 82, metallic plate 82 plays function as heating panel.
Wiring layer 13 side on the sheet of undermost memory chip 11, is provided with the 1st resin bed 30, the 1st wiring layer 32, the 2nd resin bed 41, the 2nd wiring layer 42, logic chip 70 and outside terminal 52 in the same manner as above-mentioned execution mode.
Be formed at the semiconductor integrated circuit of each memory chip 11, memory component via wiring layer on sheet 13, the 1st wiring layer 32 and being electrically connected with the 2nd wiring layer 42.Further, via the outside terminal 52 be connected with the 2nd wiring layer 42, each memory chip 11 can be connected with external circuit.
Side and the upper surface of the duplexer of multiple memory chip 11 are covered by sealing resin 80.In addition, metallic plate 82 is also covered by sealing resin 80.
In the configuration in figure 2, the minuteness space electrode pad of the chip-scale in memory chip 11 and logic chip 70, also via the 1st wiring layer 32 and the 2nd wiring layer 42, expands to and is suitable for carrying out the spacing of installing to printed wiring board etc.
In addition, logic chip 70 is configured in the region immediately below the duplexer of memory chip 11, relative to the duplexer of memory chip 11, is connected by salient point via the 1st wiring layer 32.In addition, logic chip 70 is electrically connected with outside terminal 52 via the 1st wiring layer 32 and the 2nd wiring layer 42.At the same face of the 1st resin bed 30, be provided with logic chip 70 and the 2nd wiring layer 42 for the connection with outside.
Thus, in the configuration in figure 2, when making logic chip 70 be connected with memory chip 11 and these both sides of external circuit, TSV (through electrode) can not also be used.Therefore, it is possible to provide low cost and the high semiconductor device of reliability.
(a) of Fig. 3 is the constructed profile of other examples another of the semiconductor device representing execution mode.
In the example shown in (a) of Fig. 3, memory chip portion also has the duplexer of multiple memory chip 11.In addition, be laminated with multiple 2 die-stacks 10, this 2 die-stacks 10 is by facing each other opposed and bonding and forming by the circuit face 12a of 2 memory chips 11.
1 pair of memory chip 11 in 2 die-stacks 10 is engaged by wafer to wafer bonding (wafer to wafer bonding) as described later.Multiple 2 die-stacks 10 carry out salient point connection each other.
(b) of Fig. 3 is the amplification constructed profile in the A portion in Fig. 3 (a), represents the important part section of 2 die-stacks 10.
Each memory chip 11 has wiring layer 13 on silicon substrate (semiconductor layer) 12, sheet, through electrode 18 and jointing metal (target) 21.
Circuit face 12a is provided with wiring layer 13 on the sheet that is connected with semiconductor integrated circuit, control electrode.Exemplified with multilayer wiring in (b) of Fig. 3, but on sheet, wiring layer 13 also can be individual layer.On sheet, between wiring layer 13 and circuit face 12a, on sheet, wiring layer 13 is provided with interlayer insulating film 14 on wiring layer 13 each other and on the sheet of the superiors.
The surface of interlayer insulating film 14 is provided with resin bed 15.Resin bed 15 is such as benzocyclobutene (BCB) resins.Or resin bed 15 is polyimide resin or epoxy resin.
Silicon substrate 12 is provided with through electrode 18.Further, backplate 19 is provided with at the back side 12b of silicon substrate 12.Backplate 19, defining the position of backplate 19 by through for silicon substrate 12, is connected with wiring layer on sheet 13 by through electrode 18.Through electrode 18 is such as formed by comprising the metal of copper as principal component.
Between through electrode 18 and silicon substrate 12, be provided with the dielectric film 17 preventing the direct conducting of through electrode 18 and silicon substrate 12.Dielectric film 17 is such as silicon oxide layer, silicon nitride film or silicon nitrogen oxidation film.
Jointing metal (or target) 21 has been imbedded in resin bed 15.Jointing metal 21, by through for a part for resin bed 15 and interlayer insulating film 14, is connected with wiring layer on sheet 13.Jointing metal 21 is such as formed by comprising the metal of copper as principal component.
Such memory chip 11 makes circuit face 12a (on sheet wiring layer 13) opposed each other and engages, and defines 2 die-stacks 10.The jointing metal 21 of mutual memory chip 11 is engaged each other, and resin bed 15 each other engaged (bonding).
In (a) of Fig. 3, between the backplate 19 of memory chip 11 of upside of 2 die-stacks 10 in 2 group of 2 adjacent in the stacking direction die-stacks 10, below and the backplate 19 of the memory chip 11 of the downside of 2 die-stacks 10 above it, be provided with salient point 31.Salient point 31 is such as solder ball or metal salient point, the backplate 19 of upper and lower memory chip 11 is connected to each other.
In the 12b side, the back side of the memory chip 11 of the downside of undermost 2 die-stacks 10, be provided with the 1st resin bed 30, the 1st wiring layer 32, the 2nd resin bed 41, the 2nd wiring layer 42, logic chip 70 and outside terminal 52 in the same manner as above-mentioned execution mode.
Be formed at the semiconductor integrated circuit of each memory chip 11, memory component via wiring layer on sheet 13, the 1st wiring layer 32 and being electrically connected with the 2nd wiring layer 42.Further, via the outside terminal 52 be connected with the 2nd wiring layer 42, each memory chip 11 can be connected with external circuit.
Side and the upper surface of the duplexer of multiple memory chip 11 are covered by sealing resin 80.In addition, metallic plate 82 is also covered by sealing resin 80.
In the structure of (a) of Fig. 3, the minuteness space electrode pad of the chip-scale in memory chip 11 and logic chip 70 also expands to via the 1st wiring layer 32 and the 2nd wiring layer 42 and is suitable for carrying out the spacing of installing to printed wiring board etc.
In addition, logic chip 70 is configured in the region immediately below the duplexer of memory chip 11, relative to the duplexer of memory chip 11, is connected by salient point via the 1st wiring layer 32.In addition, logic chip 70 is electrically connected with outside terminal 52 via the 1st wiring layer 32 and the 2nd wiring layer 42.At the same face of the 1st resin bed 30, be provided with logic chip 70 and the 2nd wiring layer 42 for the connection with outside.
Thus, in the structure of (a) of Fig. 3, when making logic chip 70 be connected with memory chip 11 and these both sides of external circuit, TSV (through electrode) also can not be used.Therefore, it is possible to provide low cost and the high semiconductor device of reliability.
Then, with reference to Fig. 9 ~ Figure 14, the manufacture method of 2 die-stacks 10 is described.Operation shown in Fig. 9 ~ Figure 14 is carried out under wafer (wafer) state, and a part of section of wafer W 1, W2 has been shown in Fig. 9 ~ Figure 14.
First, in wafer technique, silicon substrate 12 forms above-mentioned key element (on semiconductor integrated circuit, memory component, sheet wiring layer 13, interlayer insulating film 14, resin bed 15, jointing metal 21).Then, make the circuit face 12a side of 2 pieces of wafer W 1, W2 opposed and fit.
In Fig. 9, the 1st wafer W 1 before laminating and the 2nd wafer W 2 are shown.1st wafer W 1 and the 2nd wafer W 2 construct identical, and each key element becomes specular by binding face clamping.
Jointing metal 21 contraposition of mutual correspondence is also fitted by the 1st wafer W 1 and the 2nd wafer W 2 as shown in Figure 10.Under pressurization and heating, 2 pieces of wafer W 1, W2 are fitted, and jointing metal 21 is engaged each other and resin bed 15 is bonding each other.
After bonding chip, as shown in figure 11, make it thinning from the grinding of 12b side, the back side silicon substrate 12 of the 1st wafer W 1.Even if the silicon substrate 12 of the 1st wafer W 1 is thinning, the silicon substrate 12 of the 2nd wafer W 2 is also as supporter.Or, the silicon substrate 12 of the 1st wafer W 1 also can be made first to be ground to make it thinning by the silicon substrate 12 of the 2nd wafer W 2 as supporter.
Silicon substrate 12 before grinding is such as more than 700 μm, and by grinding, when forming through electrode, silicon substrate 12 is such as about 30 ~ 50 μm by thinning, is such as about 100 ~ 500 μm when not forming through electrode by thinning.
After thinning has been carried out to the silicon substrate 12 of the 1st wafer W 1, as shown in figure 11, formed through for silicon substrate 12 and arrive the through hole 16 of the wiring layer 13 of the 1st wafer W 1.Such as, through hole 16 is formed by etchings such as RIE (Reactive Ion Etching, reactive ion etching).
As shown in figure 12, the back side 12b of the silicon substrate 12 around the inwall and through hole 16 of through hole 16 forms dielectric film 17.Further, in through hole 16, through electrode 18 is imbedded across dielectric film 17.In addition, form at the back side 12b of silicon substrate 12 backplate 19 be connected with through electrode 18.Also dielectric film 17 is clipped between the back side 12b of electrode 19 and silicon substrate 12 overleaf.
Then, as shown in figure 13, to be formed through electrode 18 the 1st wafer W 1 silicon substrate 12 12b side, the back side paste supporter 100.In fig. 13, the 1st wafer W 1 and the 2nd wafer W 2 is represented by reversing up and down compared with Figure 12.
Supporter 100 is the rigid bodies such as such as glass substrate.Supporter 100 is adhered to the silicon substrate 12 of the 1st wafer W 1 via adhesive linkage 101.
Under the state supporting the 1st wafer W 1 and the 2nd wafer W 2 by supporter 100, make it thinning from the grinding of 12b side, the back side silicon substrate 12 of the 2nd wafer W 2.
After thinning has been carried out to the silicon substrate 12 of the 2nd wafer W 2, in the same manner as the technique to the 1st wafer W 1, formed through for silicon substrate 12 and arrive the through hole of the wiring layer 13 of the 2nd wafer W 2.
Further, as shown in figure 14, the back side 12b of the silicon substrate 12 around the inwall and through hole 16 of the through hole 16 of the 2nd wafer W 2 forms dielectric film 17.In addition, in through hole 16, through electrode 18 is imbedded across dielectric film 17.In addition, form at the back side 12b of silicon substrate 12 backplate 19 be connected with through electrode 18.Also dielectric film 17 is clipped between the back side 12b of electrode 19 and silicon substrate 12 overleaf.In addition, as required, overleaf electrode 19 forms salient point 31.
Afterwards, the conjugant of the 1st wafer W 1 and the 2nd wafer W 2 is cut, supporter 100 is removed (stripping), thus obtains 2 die-stacks 10 of singualtion.
Such as, be secured at the state in cutting belt with supporter 100, the 2nd wafer W 2 and the 1st wafer W 1 are cut.Or, also after supporter 100 is peeled off, the 1st wafer W 1 and the 2nd wafer W 2 can be cut.
2 die-stacks 10 of execution mode be not the chip of 2 chips of singualtion to chip bonding (chip to chip bonding), but by wafer, the cutting after bonding chip to be obtained.Thus, 2 die-stacks 10 are formed as the rectangular shape with continuous print side.
Multiple 2 die-stacks 10 of singualtion are laminated on metallic plate 82 as described above, filling sealing resin 80 between multiple 2 die-stacks 10.
Or, also multiple 2 die-stacks 10 can be fitted via the resin bonding layer be pre-formed from the teeth outwards and stacked.
In TSV structure, if make substrate thin, the surface area of through electrode diminishes, and can reduce the parasitic capacitance between opposed through electrode and substrate by dielectric film clamping.But, if substrate is thinning, then produces and process the problem becoming difficulty in the packaging technology such as bonding of chip bonding each other, chip and installation base plate.
Therefore, according to execution mode described above, carried out making the circuit face 12a side of 2 pieces of wafer W 1, W2 opposed wafer to bonding chip after, using the silicon substrate 12 of the wafer W 2 of a side as supporter, silicon substrate 12 thinning of the wafer W 1 of the opposing party is formed through electrode 18.Afterwards, after supporter (rigid body) 100 has been pasted in silicon substrate 12 side of the wafer W 1 of a side, by silicon substrate 12 thinning of the wafer W 2 of the opposing party, and also through electrode 18 is formed to wafer W 2.
Therefore, it is possible to do not forming TSV structure by the basis of substrate 12 thinning respective for 2 die-stacks 10 with bringing the difficulty of process.As reference example, with chip to the mode of chip by compared with the structure of 2 chip laminates, according to 2 die-stacks 10 of execution mode, the thickness of substrate 12 can be made to be about 1/2.
Thus, compared with reference example, clamping dielectric film 17 can be made and the surface area of the through electrode 18 opposed with silicon substrate 12 is about 1/2, the parasitic capacitance between through electrode 18 and substrate 12 can be reduced to about 1/2.
Particularly, if the stacked number of memory chip 11 increases along with the high capacity of storage capacitance, then the quantity of TSV also increases, the impact that there is its parasitic capacitance also becomes large tendency, but according to execution mode, by the thinning of substrate 12, the parasitic capacitance of TSV is reduced, thus the minimizing of power consumption can be realized.
In addition, 2 die-stacks 10 structure that profile construction is in specular, identical memory chip 11 bonds together and obtains by clamping composition surface, therefore the warpage that each memory chip 11 occurs is cancelled, and can obtain little warpage as 2 die-stacks 10.
Fig. 4 is the constructed profile of other examples another of the semiconductor device representing execution mode.
In the structure of Fig. 4, different from the structure of Fig. 1 in the 2nd resin bed 41 covering logic chip 70 this point.
The upper surface of logic chip 70 face of the opposition side of wiring layer 71 (on the sheet) is covered by the 2nd resin bed 41.Also the outside weldings district 42a of the 2nd wiring layer 42 is provided with in the 2nd resin bed 41 covered by the upper surface of logic chip 70.Outside terminal 52 is bonded to this outside weldings district 42a.That is, outside terminal 52 is also configured with in the region of having installed logic chip 70.
By the area extension by configurable outside terminal 52, the spacing that can realize between outside terminal 52 expands, and reliably prevent short circuit between terminal, installation improves.
(a) and (b) of Fig. 5 is the constructed profile of other examples another of the semiconductor device representing execution mode.(b) of Fig. 5 is the amplification constructed profile in the B portion in Fig. 5 (a).The formation of the 1st resin bed 30, the 1st wiring layer 32, the 2nd resin bed 41, the 2nd wiring layer 42 etc. is identical with above-mentioned execution mode.
Semiconductor device according to (a) and (b) of Fig. 5, logic chip 70 is large-scale multi-pipe pin chips that such as SoC (System on a Chip: SOC (system on a chip)) constructs, and a part for logic chip 70 is overlapping with the 2nd resin bed 41 and the 2nd wiring layer 42 when overlooking.That is, compared with the area of the installation region (peristome of the 2nd resin bed 41) of logic chip 70, the planar dimension of logic chip 70 is larger.Sealing resin 73 is clipped between logic chip 70 and the 2nd resin bed 41.
(a) of Fig. 2, Fig. 3, Fig. 5 (a) and (b) shown in execution mode in, multiple memory chip 11, as shown in (a) of Figure 15, is connected in parallel (bus connection) common data input and output terminal 90.That is, by through electrode and salient point etc., to the common data/address bus 91 be formed on chip laminate direction, multiple chip 11 is connected in parallel.
In addition, as shown in (b) of Figure 15, to the bus 93 of terminal 92 being connected to logic chip 70, multiple memory chip 11 is connected in parallel.
Then, (c) of (a) ~ Fig. 8 of reference Fig. 6 illustrates the manufacture method of the semiconductor device of execution mode.In (c) of (a) ~ Fig. 8 of Fig. 6, illustrate the duplexer of multiple memory chip 11 as memory chip portion, but also can only have 1 memory chip 11.
Multiple memory chip 11 is laminated on metallic plate 82.On the memory chip 11 of the superiors in the multiple memory chips 11 on metallic plate 82, form the 1st resin bed 30 and the 1st wiring layer 32.
The duplexer 100 comprising these metallic plates 82, multiple memory chip 11, the 1st resin bed 30 and the 1st wiring layer 32, as shown in (a) and (b) of Fig. 6, is mounted on supporter 95.Multiple duplexer 100 is mounted on supporter 95 separated from each other.Make the 1st resin bed 30 (towards supporter 95 side) and be mounted on supporter 95 by duplexer 100 down.
Then, as shown in (c) of Fig. 6, after the duplexer 100 on supporter 95 is molded and shaped with resin 80, supporter 95 is removed.
Then, as shown in (a) of Fig. 7, on the 1st resin bed 30 and on the resin 80 of chip exterior domain (region between adjacent duplexer 100), the 2nd resin bed 41 and the 2nd wiring layer 42 is formed.In addition, form peristome 41a at the 2nd resin bed 41 of chip area just above, the weld zone 32a (as shown in Figure 1) of the 1st resin bed 30 and the 1st wiring layer 32 is exposed from this peristome 41a.
Further, on the 1st resin bed 30 of peristome 41a, as shown in (b) of Fig. 7, logic chip 70 is installed.Logic chip 70 engages with the weld zone 32a of the 1st wiring layer 32 through salient point 72 as shown in Figure 1.
After logic chip 70 has been installed, the 2nd resin bed 41 forms multiple outside terminal 52.Multiple outside terminal 52 is such as configured to grid (grid) shape on the 2nd resin bed 41.Outside terminal 52 engages with the outside weldings district 42a (as shown in Figure 1) of the 2nd wiring layer 42.
Afterwards, the 2nd resin bed 41 in adjacent duplexer 100 regions and sealing resin 80 are cut off, monolithic turns to multiple semiconductor device.
In addition, to be formed before the 2nd resin bed 41 after the operation of (c) of Fig. 6, as shown in (a) of Fig. 8, logic chip 70 can be carried on the 1st resin bed 30.
Afterwards, as shown in (b) of Fig. 8, in the mode of covering logic chip 70, on the 1st resin bed 30 and on the resin 80 of chip exterior domain (region between adjacent duplexer 100), form the 2nd resin bed 41.
For the 2nd resin bed 41, use such as laser to form through hole, the 2nd wiring layer 42 is imbedded.
Afterwards, as shown in (c) of Fig. 8, the 2nd resin bed 41 forms multiple outside terminal 52.Outside terminal 52 also can be configured in the region overlapping with logic chip 70.Thus, compared with the structure shown in (c) of Fig. 7, the configurable area extension of multiple outside terminal 52, the configuration degree of freedom of outside terminal 52 uprises.
Afterwards, the 2nd resin bed 41 in adjacent duplexer 100 regions and sealing resin 80 are cut off, monolithic turns to multiple semiconductor device.
According to the semiconductor device of execution mode, multiple memory chip is connected in parallel common data input and output terminal.In addition, multiple memory chip connects the bus parallel connection being connected to logic chip.
In addition, according to the manufacture method of the semiconductor device of execution mode, after the 1st resin bed defines the 2nd resin bed, in the 2nd resin bed, the peristome that the 1st resin bed is exposed is formed, in peristome configuration the 2nd chip section.In addition, according to the manufacture method of the semiconductor device of execution mode, after the 1st resin bed has installed the 2nd chip section, on the 1st resin bed, the 2nd resin bed is formed in the mode covering the 2nd chip section.
Figure 16 is the constructed profile of other examples another of the semiconductor device representing execution mode.
The upper strata chip of the execution mode shown in Figure 16, has the lit-par-lit structure of multiple memory chip 11 in the same manner as the execution mode such as shown in Fig. 2.In the section shown in Figure 16, this upper strata chip is ground warpage as the bow raised up.
For the direction, face of upper strata chip, the 1st resin bed 30 has peripheral part 30b and central portion 30a.Distance (beeline) between the peripheral part 30b of the 1st resin bed 30 and the bottom surface of the 2nd resin bed 41 is less than the distance (beeline) between the central portion 30a of the 1st resin bed 30 and the bottom surface of the 2nd resin bed 41.
Distance (beeline) between the lower end of the 1st wiring layer 32 arranged in the outer region (the peripheral part 30b of the 1st resin bed 30) in the direction, face of upper strata chip and the bottom surface of the 2nd resin bed 41, the distance (beeline) between the lower end of the 1st wiring layer 32 that the middle section (the central portion 30a of the 1st resin bed 30) being less than the direction, face at upper strata chip is arranged and the bottom surface of the 2nd resin bed 41.
The peripheral part 30b comprising the side of the 1st resin bed 30 is embedded in the 2nd resin bed 41, is covered by the 2nd resin bed 41.Therefore, the connection reliability (adhesion) between the 1st resin bed 30 and the 2nd resin bed 41 improves.
Be not limited to the whole of the side of the 1st resin bed 30 to be covered by the 2nd resin bed 41.Even if a part for the side of the 1st resin bed 30 is covered by the 2nd resin bed 41, connection reliability also improves.
Semiconductor device according to (a) and (b) of Figure 17, a part for the side of the peripheral part 30b of the 1st resin bed 30 is embedded in the 2nd resin bed 41, is covered by the 2nd resin bed 41.
In the operation of (b) of above-mentioned Fig. 6, upper strata chip is installed on supporter 95 via not shown temporary bond oxidant layer.Now, the 1st resin bed 30 is pressed against temporary bond oxidant layer, and is absorbed in temporary bond oxidant layer a little.If resin 80 molded and shaped after supporter 95 is peeled off, then the 1st resin bed 30 is outstanding a little from resin 80.If herein formed the 2nd resin bed 41, then the 1st resin bed 30 be embedded in the 2nd resin bed 41 at least partially.
Execution mode is as shown in figure 16 such, if make upper strata chip warpage, then the 1st resin bed 30 reliably can be imbedded the 2nd resin bed 41.
Some execution modes of the present invention are illustrated, but these execution modes are pointed out as an example, and be not intended to limit scope of invention.These new execution modes can be implemented with other various forms, within a range not departing from the gist of the invention, can carry out various omission, replacement, change.These execution modes and distortion thereof are included in scope of invention and purport, and in the scope of the invention be included in described in claim and equivalence thereof.
Description of reference numerals
11 ... memory chip, 12 ... silicon substrate (semiconductor layer), 13 ... wiring layer on sheet, 30 ... 1st resin bed, 32 ... 1st wiring layer, 41 ... 2nd resin bed, 42 ... 2nd wiring layer, 52 ... outside terminal, 70 ... logic chip

Claims (14)

1. a semiconductor device, possesses:
Upper strata chip, has the 2nd of the opposition side of the 1st and above-mentioned 1st;
1st resin bed, is arranged on above-mentioned 1st of above-mentioned upper strata chip;
1st wiring layer, is arranged in above-mentioned 1st resin bed, connects with above-mentioned upper strata chip electrical;
2nd resin bed, is arranged on the face side of above-mentioned 1st resin bed, and expands to the side chip exterior domain in the outer part than above-mentioned upper strata chip;
2nd wiring layer, is arranged in above-mentioned 2nd resin bed, is connected, and extends to said chip exterior domain with above-mentioned 1st wiring layer;
Lower layer chip, is arranged on the above-mentioned face side of above-mentioned 1st resin bed, is connected with above-mentioned 1st wiring layer; And
Sealing resin, covers above-mentioned upper strata chip.
2. semiconductor device as claimed in claim 1,
Above-mentioned lower layer chip is configured in the peristome being formed at above-mentioned 2nd resin bed.
3. semiconductor device as claimed in claim 1,
Above-mentioned lower layer chip covers by above-mentioned 2nd resin bed.
4. semiconductor device as claimed in claim 1,
Also possess the face side being arranged on above-mentioned 2nd resin bed and the outside terminal be connected with above-mentioned 2nd wiring layer,
The minimum spacing of the connecting portion between above-mentioned lower layer chip and above-mentioned 1st wiring layer is less than the minimum spacing of said external terminal.
5. semiconductor device as claimed in claim 4,
The minimum spacing of the connecting portion between above-mentioned lower layer chip and above-mentioned 1st wiring layer is less than the minimum spacing of the connecting portion between above-mentioned 1st wiring layer and above-mentioned 2nd wiring layer.
6. semiconductor device as claimed in claim 4,
Above-mentioned lower layer chip covers by above-mentioned 2nd resin bed,
Said external terminal is also arranged on the region that above-mentioned lower layer chip covers by above-mentioned 2nd resin bed.
7. semiconductor device as claimed in claim 1,
Above-mentioned lower layer chip overlook overlapping with above-mentioned 2nd wiring layer.
8. semiconductor device as claimed in claim 1,
Above-mentioned upper strata chip comprises memory chip, and above-mentioned lower layer chip comprises logic chip.
9. semiconductor device as claimed in claim 8,
Above-mentioned upper strata chip has the duplexer of multiple above-mentioned memory chip.
10. semiconductor device as claimed in claim 9,
Above-mentioned multiple memory chip has the 1st chip and the 2nd chip,
Above-mentioned 1st chip has:
1st semiconductor layer, has the 1st back side of the opposition side of the 1st circuit face and above-mentioned 1st circuit face;
1st upper wiring layer, is arranged on above-mentioned 1st circuit face; And
1st through electrode, through above-mentioned 1st semiconductor layer and arranging, and be connected with above-mentioned 1st upper wiring layer,
Above-mentioned 2nd chip laminate is wiring layer side on above-mentioned 1st of above-mentioned 1st chip, has:
2nd semiconductor layer, has the 2nd back side of the opposition side of 2nd circuit face opposed with above-mentioned 1st upper wiring layer and above-mentioned 2nd circuit face;
2nd upper wiring layer, is arranged on above-mentioned 2nd circuit face, is connected with the above-mentioned 1st upper wiring layer of above-mentioned 1st chip; And
2nd through electrode, through above-mentioned 2nd semiconductor layer and arranging, is connected with above-mentioned 2nd upper wiring layer.
11. semiconductor devices as claimed in claim 10,
Above-mentioned multiple memory chip also has the 3rd chip of above-mentioned 2nd rear side being layered in above-mentioned 2nd chip,
Above-mentioned 3rd chip has:
3rd semiconductor layer, has the 3rd circuit face and is positioned at the opposition side of above-mentioned 3rd circuit face and 3rd back side opposed with above-mentioned 2nd chip;
3rd wiring layer, is arranged on above-mentioned 3rd circuit face; And
3rd through electrode, through above-mentioned 3rd semiconductor layer and arranging, is connected with above-mentioned 3rd wiring layer, and is connected with above-mentioned 2nd through electrode of above-mentioned 2nd chip via salient point.
12. semiconductor devices as claimed in claim 1,
Distance between the lower end of above-mentioned 1st wiring layer arranged in the outer region of above-mentioned upper strata chip and the bottom surface of above-mentioned 2nd resin bed, is less than the distance between the lower end of above-mentioned 1st wiring layer arranged at the middle section of above-mentioned upper strata chip and the bottom surface of above-mentioned 2nd resin bed.
13. semiconductor devices according to any one of claim 1 ~ 12,
A part at least peripheral part of above-mentioned 1st resin bed is covered by above-mentioned 2nd resin bed.
The manufacture method of 14. 1 kinds of semiconductor devices, possesses following operation:
There is above-mentioned 1st of the upper strata chip of the 2nd of opposition side of the 1st and above-mentioned 1st, forming the 1st resin bed and be arranged on the operation of the 1st wiring layer connect with above-mentioned upper strata chip electrical in above-mentioned 1st resin bed;
By the operation that above-mentioned 2nd side of above-mentioned upper strata chip and side resin cover;
On above-mentioned resin on above-mentioned 1st resin bed and than the side chip exterior domain in the outer part of above-mentioned upper strata chip, form the 2nd resin bed and be arranged on being connected with above-mentioned 1st wiring layer and extending to the operation of the 2nd wiring layer of said chip exterior domain in above-mentioned 2nd resin bed; And
Above-mentioned 1st resin bed is installed the operation of the lower layer chip be connected with above-mentioned 1st wiring layer.
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