CN104916309B - Sub-threshold SRAM memory cell - Google Patents
Sub-threshold SRAM memory cell Download PDFInfo
- Publication number
- CN104916309B CN104916309B CN201410093326.3A CN201410093326A CN104916309B CN 104916309 B CN104916309 B CN 104916309B CN 201410093326 A CN201410093326 A CN 201410093326A CN 104916309 B CN104916309 B CN 104916309B
- Authority
- CN
- China
- Prior art keywords
- tube
- nmos tube
- source
- drain terminal
- phase inverter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000005540 biological transmission Effects 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 230000003068 static effect Effects 0.000 abstract description 2
- 230000003321 amplification Effects 0.000 abstract 1
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 238000003199 nucleic acid amplification method Methods 0.000 abstract 1
- 230000006870 function Effects 0.000 description 14
- 230000009467 reduction Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000000342 Monte Carlo simulation Methods 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 240000005373 Panax quinquefolius Species 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
Landscapes
- Static Random-Access Memory (AREA)
Abstract
The invention provides a sub-threshold SRAM memory cell, comprising: the circuit comprises a basic circuit, a unit data reading circuit, a pre-amplifier tube circuit and an improved Schmitt inverter; the output end (QB) of the basic circuit is connected with the input end of the unit data reading circuit, and the output end of the unit data reading circuit is connected with the output end of the pre-amplifier tube circuit and is connected with the input end of the improved Schmitt phase inverter; the pre-amplifier circuit comprises a third NMOS (N-channel metal oxide semiconductor) tube (MN3), the source end of the third NMOS tube is grounded, the grid end of the third NMOS tube is connected with a pre-amplifier control signal PREDIS, and the drain end of the third NMOS tube is connected with a read bit line RBL. The SRAM unit provided by the invention adopts a pre-amplification reading mode to reduce the power consumption; due to threshold loss of NMOS transmission high level, dynamic power consumption is reduced remarkably, and static power consumption is reduced to a certain extent; meanwhile, the swing of the read data can be identified without reaching the full swing, and the performance of the SRAM is obviously improved.
Description
Technical field
The present invention relates to memory area more particularly to a kind of 8 pipe SRAM of nearly subthreshold value with completely new playback mode are mono-
Member.
Background technique
With the rise of the application fields such as Internet of Things, medical electronics, RFID, large batch of wireless sensing node is answered extensively
With.The typical feature of this kind of node is that quantity required is big, system bulk is small, performance requirement is low, power consumption requirements are high.In this kind of section
In point, memory has accounted for the power consumption of significant proportion, therefore the power consumption for reducing memory has very big side to the reduction of Overall Power Consumption
It helps.SRAM is extensively studied as common memory.In order to farthest reduce power consumption, the design of nearly subthreshold value is opened
Begin to flourish Sheng.
Any pipe operates the power consumption of consumption every time are as follows:
Wherein Ptransistor, Pdyn, Pshort, PleakRespectively correspond the overall power that each pipe operates every time, dynamic function
Consumption, short-circuit dissipation and electricity leakage power dissipation.Assuming that including N number of pipe in integrated circuit, then the power consumption of integrated circuit is N Ptotal.It is dynamic
At quadratic relationship, quiescent dissipation is linear with voltage for state power consumption and voltage.The case where integrated circuit voltage remains unchanged
Under, certain pipes in N number of pipe can be made to be not operate at the voltage V of full swingDDUnder, it with this method can be original
Power consumption is reduced on the basis of low-power consumption again.Assuming that being not operate at VDDUnder pipe have M, then the power consumption of integrated circuit are as follows:
Ptotal=MPtransistor1+(N-M)Ptransistor2,
Wherein Ptransistor1It is to be not operate at full swing VDDThe power consumption of lower pipe, Ptransistor2It is work in VDDLower pipe
Power consumption, compared with original, lower power consumption.Wherein due to dynamic power consumption and VDDAt quadratic relationship, accounted in reducing part main
Ratio, but the reduction that quiescent dissipation and short-circuit dissipation also can be certain.
For 6 conventional transistor memory units, it will appear various problems under nearly subthreshold region, solve the problems, such as to compare
Effective method first is that again plus 2 pipes, read operation being isolated, 8 transistor memory units are formed.This element is in nearly subthreshold value
Under can be operated, power consumption can be effectively reduced.But with the development of technology, there is higher requirement again to power consumption, so
Needing one kind can be on the basis of original low-power consumption, then reduces the memory device of power consumption while assurance function correctness.
Summary of the invention
The present invention provides a kind of subthreshold value SRAM memory cell, which reduces power consumption using the reading mode put in advance,
Its power consumption is significantly reduced.Specifically, the circuit includes:
Basic circuit, puts pipe circuit and improved Schmitt phase inverter at cell data reading circuit in advance；It is described substantially electric
The input terminal of the output end connection unit data reading circuit on road, the output end of cell data reading circuit and puts pipe circuit in advance
Output is connected, the input terminal of the Schmitt phase inverter of Innovation of Connection；Wherein, the pre- pipe circuit of putting includes third NMOS tube group
At source ground connection, grid end connects pre- put and controls signal PREDIS, and drain terminal meets readout bit line RBL.
Wherein, the basic circuit includes the first phase inverter, the second phase inverter, the first write-in pipe, the second write-in pipe；Its
In, the output end of the first phase inverter is separately connected the input terminal of the second phase inverter and the output end of the first write-in pipe；Second reverse phase
The output end of device is separately connected the input terminal of the first phase inverter and the output end of the second write-in pipe；First, second is written the defeated of pipe
Enter end and is separately connected external bit line signal.
Wherein, first phase inverter includes the first PMOS tube, the 4th NMOS tube, and the source of the first PMOS tube connects power supply
Voltage, the source ground connection of the 4th NMOS tube；The drain terminal of first PMOS tube and the drain terminal of the 4th NMOS tube, which are connected, is used as the first reverse phase
The output of device, the first PMOS tube, the grid end of the 4th NMOS tube connect the output of the second phase inverter.
Wherein, second phase inverter includes the second PMOS tube, the 5th NMOS tube, and the source of the second PMOS tube connects power supply
Voltage, the source ground connection of the 5th NMOS tube；The drain terminal of second PMOS tube and the drain terminal of the 5th NMOS tube, which are connected, is used as the second reverse phase
The output of device, the second PMOS tube, the grid end of the 5th NMOS tube connect the output of the first phase inverter.
Wherein, the first write-in pipe includes the 6th NMOS tube, and drain terminal connects write bit line, and grid end connects write control signal
WWL, source connect the data in SRAM.
Wherein, the second write-in pipe includes the 7th NMOS tube, and drain terminal connection write bit line is non-, and grid end connects write control signal
WWL, source connect the data in SRAM.
Wherein, the cell data reading circuit includes the first, second NMOS tube, wherein the drain terminal of the first NMOS tube connects electricity
Source voltage, grid end meet the output data QB of basic circuit, and source connects the second draining end of NMOS tube；Second draining end of NMOS tube connects first
NMOS tube source, grid end, which connects, reads selection signal RWL, and source meets sense bit line RBL.
Wherein, the improved Schmitt phase inverter group includes third, the four, the 5th PMOS tube and the 8th NMOS tube,
Wherein third PMOS source end connects supply voltage, and drain terminal connects the source of the 4th PMOS tube and the 5th PMOS tube；4th PMOS tube source
End and drain terminal connect the source of third PMOS tube and the drain terminal of the 8th NMOS tube respectively；The source of 8th NMOS tube is grounded；5th
The source of PMOS tube connects the drain terminal of third PMOS tube, and grid end connects the drain terminal of the 4th PMOS tube and the 8th NMOS tube, drain terminal ground connection；The
The grid end of three PMOS tube, the 4th PMOS tube and the 8th NMOS tube meets readout bit line RBL.
Wherein, the 5th PMOS tube is feedback pipe, to reinforce the NMOS tube in phase inverter；Third NMOS tube be it is pre- put pipe,
To make readout bit line keep low level in idle.
Sram cell provided by the invention is in the storage unit being currently known, only one using the reading mode put in advance come
Power consumption is reduced, and this mode can be transplanted；Due to the threshold value loss of NMOS transmission high level, dynamic function
Depletion is small significant, while quiescent dissipation also decrease to some degree；Meanwhile this makes the amplitude of oscillation for reading data not have to reach entirely
The amplitude of oscillation can also be identified.Significantly improve SRAM performance.
Detailed description of the invention
By reading a detailed description of non-restrictive embodiments in the light of the attached drawings below, of the invention other
Feature, objects and advantages will become more apparent upon:
Fig. 1 is the structure and its functional simulation for the single storage unit implemented according to present example；
Fig. 2 is 32 storage units implemented according to present example and block reading circuit；
Fig. 3 is 32 units, 1000 Monte Carlo simulation figures；
Fig. 4 is single traditional 8 pipe sub-threshold memory cells；
Fig. 5 is improved Schmitt phase inverter；
Fig. 6 is the voltage-transfer characteristic curve of phase inverter in Fig. 5；
The same or similar appended drawing reference represents the same or similar component in attached drawing.
Specific embodiment
With reference to the accompanying drawing and specific embodiments of the present invention present invention is further described in detail.It is understood that
It is that, the invention is not limited to following particular implementations, those skilled in the art can be within the scope of the appended claims
Make various deformations or amendments.
As shown in Figure 1, the structure includes: basic circuit, cell data the present invention provides a kind of subthreshold value storage circuit
Reading circuit puts pipe circuit and improved Schmitt phase inverter in advance；
The circuit includes: basic circuit, cell data reading circuit, puts pipe circuit and improved Schmitt reverse phase in advance
Device；Wherein, the input terminal of the output end connection unit data reading circuit of basic circuit, the output end of cell data reading circuit
It is connected with the output for putting pipe circuit in advance, the input terminal of the Schmitt phase inverter of Innovation of Connection；Wherein, the pre- pipe circuit of putting includes
Third NMOS tube MN3, source ground connection, grid end connect pre- put and control signal PREDIS, and drain terminal meets readout bit line RBL.
Wherein, the basic circuit includes the first phase inverter, the second phase inverter, the first write-in pipe, the second write-in pipe；Its
In, the output end of the first phase inverter is separately connected the input terminal of the second phase inverter and the output end of the first write-in pipe；Second reverse phase
The output end of device is separately connected the input terminal of the first phase inverter and the output end of the second write-in pipe；First, second is written the defeated of pipe
Enter end and is separately connected external bit line signal.
Wherein, first phase inverter includes the first PMOS tube MP1, the 4th NMOS tube MN4, the source of the first PMOS tube MP1
End connection supply voltage, the source ground connection of the 4th NMOS tube MN4；The leakage of the drain terminal and the 4th NMOS tube MN4 of first PMOS tube MP1
End is connected output as the first phase inverter, grid end the second phase inverter of connection of the first PMOS tube MP1, the 4th NMOS tube MN4
Output.
Wherein, second phase inverter includes the second PMOS tube MP2, the 5th NMOS tube MP5, the source of the second PMOS tube MP2
End connection supply voltage, the source ground connection of the 5th NMOS tube MN5；The leakage of the drain terminal and the 5th NMOS tube MN5 of second PMOS tube MP2
End is connected output as the second phase inverter, grid end the first phase inverter of connection of the second PMOS tube MP2, the 5th NMOS tube MN5
Output.
Wherein, the first write-in pipe includes the 6th NMOS tube MN6, and drain terminal connects write bit line, and control letter is write in grid end connection
Number WWL, source connect the data in SRAM.
Wherein, the second write-in pipe includes the 7th NMOS tube MN7, and drain terminal connection write bit line is non-, and control is write in grid end connection
Signal WWL, source connect the data in SRAM.
Wherein, the cell data reading circuit includes the first, second NMOS tube MN1, MN2, wherein the first NMOS tube MN1
Drain terminal connect supply voltage, grid end meets the output data QB of basic circuit, and source connects the second NMOS tube MN2 drain terminal；2nd NMOS
Pipe MN2 drain terminal connects the first NMOS tube MN1 source, and grid end, which connects, reads selection signal RWL, and source meets sense bit line RBL.
Wherein, the improved Schmitt phase inverter group include third, the four, the 5th PMOS tube MP3, MP4, MP5 and
8th NMOS tube MN8, wherein third PMOS tube MP3 source connects supply voltage, and drain terminal connects the 4th PMOS tube MP4 and the 5th PMOS tube
The source of MP5；4th PMOS tube MP4 source and drain terminal connect the source of third PMOS tube MP3 and the leakage of the 8th NMOS tube MN8 respectively
End；The source of 8th NMOS tube MN8 is grounded；The source of 5th PMOS tube MP5 connects the drain terminal of third PMOS tube MP3, and grid end connects
The drain terminal of four PMOS tube MP4 and the 8th NMOS tube MN8, drain terminal ground connection；Third PMOS tube MP3, the 4th PMOS tube MP4 and the 8th
The grid end of NMOS tube MN8 meets readout bit line RBL.
Wherein, the 5th PMOS tube MP5 is feedback pipe, to reinforce the NMOS tube in phase inverter；Third NMOS tube MN3 is pre-
Pipe is put, to make readout bit line keep low level in idle.
By change control signal RWL, the input of WWL, can control the storage unit realize keep function, read function or
Write function.
In the present embodiment, the initial output value Q of the first phase inverter is low level 0, the initial output value of the second phase inverter
QB is high level 1.
A. function is kept
As control signal RWL, when WWL is low level, MN2 is turned off, and circuit, which is realized, keeps function.First, second reverse phase
Device forms feedback loop and carries out data preservation, forms holding circuit.QB is " 1 ", then MN1 is opened, and QBB voltage rises, but due to
MN1 transmits high level there are threshold value loss, cause QBB voltage be not full swing supply voltage, so the voltage of MN2 drain terminal
It is not the high level of full swing.The pre- pipe of putting on sense bit line is open at this time, and sense bit line is low level, i.e., MN2 source connects low
Level, so that the pressure difference at the both ends MN2 is less than the pressure difference of supply voltage, so MN2 compares traditional structure leakage reduction.
Bring conducting electric current is smaller than traditional structure bring power consumption in the present invention by MN1, this to reduce for individual unit,
It is not particularly evident on absolute value, but when 32 units (such as Fig. 2) of composition, the reduction of power consumption is clearly.It is known from Table 1 that
Quiescent dissipation of the invention lower than traditional structure 7.56%.
8 traditional pipe sram cells, as shown in figure 4, QB=" 1 ", MN1 is opened, and makes MN2 source low level, and because
For this preliminary filling pipe of MP3 opening, i.e., MN2 drain terminal is full swing supply voltage, and the voltage for so acting on the both ends MN2 is full swing
Supply voltage, electricity leakage power dissipation are bigger than the electric leakage in the present invention.
Under table 1.500mV, 32 storage units of the present invention are compared with conventional memory cell power consumption
| Read Q=0, QB=1 | Electric leakage | |
| The power consumption of traditional preliminary filling | 3.30e-08 | 7.80e-09 |
| Power consumption of the invention | 2.19e-08 | 7.21e-09 |
| Improve percentage | 33.63% | 7.564% |
B. function is read
When control signal WWL is low level, when RWL is high level, metal-oxide-semiconductor MN2 conducting, circuit, which is realized, reads function.QB=
" 1 ", MN1 conducting.The level on sense bit line is low level at this time, then which forms the conductings from supply voltage to sense bit line
Access, this access can consume power consumption.Also due to there are threshold value losses for NMOS tube transmission high level, i.e., so that on sense bit line
Level does not reach the supply voltage of full swing, according to formulaKnow the lower power consumption that single is read.
In table 1, the reduction that power consumption is read when QB=" 1 " clearly, has reached 33.63%.But at this time due to read bit
High level on line is not the level of full swing, can lead to the problem of unstable, is not correctly validated in traditional circuit.And this
Invention has well solved this problem.
The solution that the present invention takes is that the conductive capability in nearly subthreshold region NMOS is utilized much stronger than PMOS's
Characteristic so that the voltage-transfer characteristic curve of phase inverter is biased to low level, while having reused improved Schmitt phase inverter, added
Strong this offset.Fig. 5 is the improved Schmitt phase inverter used in the present invention, and Fig. 6 is this phase inverter in different works
Voltage-transfer characteristic curve under skill angle.Know from Fig. 6, though under the process corner of SNFP, voltage-transfer characteristic curve also to
Low level offset, it is not that the high level of full swing also can be identified correctly on sense bit line that this characteristic, which ensure that,.Fig. 3 is to use
After Fig. 5 phase inverter, 32 units read the Monte Carlo functional simulation of data function.Seen from the simulation results uses such anti-
Phase device ensure that the correctness for reading data.Based on the above emulation, the present invention is right under the premise of guaranteeing that read operation function is correct
It is huge for reading the reduction of power consumption.
C. function is write
When control signal RWL is low level, when WWL is high level, MN6 and MN7 are opened, and circuit realizes write operation function.
Because Q is low level, outer bit line WBL is high level, and WBLB is low level, and MN6 and MN7 are opened, corresponding external number
According to Q and QB will be transmitted to, to change the original level of Q and QB.
Sram cell provided by the invention is in the storage unit being currently known, only one using the reading mode put in advance come
Power consumption is reduced, and this mode can be transplanted；In the worst case, due to the threshold of NMOS transmission high level
Value loss, dynamic power consumption are substantially reduced, and static leakage has a degree of reduction；Meanwhile this makes the amplitude of oscillation of reading data
It can also be identified without reaching full swing.Significantly improve SRAM performance.
Specific embodiments of the present invention are described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, those skilled in the art can make various deformations or amendments within the scope of the appended claims.
Claims (2)
1. a kind of subthreshold value SRAM memory cell, comprising: basic circuit, is put pipe circuit and changed cell data reading circuit in advance
Into Schmitt phase inverter；The input terminal of output end (QB) connection unit data reading circuit of the basic circuit, unit number
It is connected according to the output end of reading circuit with the output for putting pipe circuit in advance, the input terminal of the Schmitt phase inverter of Innovation of Connection；
Wherein, the pre- pipe circuit of putting includes third NMOS tube (MN3), source ground connection, and grid end, which connects, pre- puts control signal
PREDIS, drain terminal meet readout bit line RBL, and the basic circuit includes the first phase inverter, the second phase inverter, the first write-in pipe, the
Two write-in pipes；
Wherein, the output end of the first phase inverter is separately connected the input terminal of the second phase inverter and the output end of the first write-in pipe；The
The output end of two phase inverters is separately connected the input terminal of the first phase inverter and the output end of the second write-in pipe；First, second write-in
The input terminal of pipe is separately connected external bit line signal；
First phase inverter includes the first PMOS tube (MP1), the 4th NMOS tube (MN4), and the source of the first PMOS tube (MP1) connects
Connect supply voltage, the source ground connection of the 4th NMOS tube (MN4)；The drain terminal of first PMOS tube (MP1) and the 4th NMOS tube (MN4)
The connected output as the first phase inverter of drain terminal, the first PMOS tube (MP1), the grid end of the 4th NMOS tube (MN4) connection second are anti-
The output of phase device；
Second phase inverter includes the second PMOS tube (MP2), the 5th NMOS tube (MP5), and the source of the second PMOS tube (MP2) connects
Connect supply voltage, the source ground connection of the 5th NMOS tube (MN5)；The drain terminal of second PMOS tube (MP2) and the 5th NMOS tube (MN5)
The connected output as the second phase inverter of drain terminal, the second PMOS tube (MP2), the grid end of the 5th NMOS tube (MN5) connection first are anti-
The output of phase device；
The first write-in pipe includes the 6th NMOS tube (MN6), and drain terminal connects write bit line, and grid end connects write control signal WWL, source
Data in end connection SRAM；
The second write-in pipe includes that the 7th NMOS tube (MN7) includes, and drain terminal connection write bit line is non-, and grid end connects write control signal
WWL, source connect the data in SRAM；
The cell data reading circuit includes that the first, second NMOS tube (MN1, MN2) includes, wherein the first NMOS tube (MN1)
Drain terminal connect supply voltage, grid end meets the output data QB of basic circuit, and source connects the second NMOS tube (MN2) drain terminal；Second
NMOS tube (MN2) drain terminal connects the first NMOS tube (MN1) source, and grid end, which connects, reads selection signal RWL, and source meets sense bit line RBL；
The improved Schmitt phase inverter group includes third, the four, the 5th PMOS tube (MP3, MP4, MP5) and the 8th NMOS
Managing (MN8) includes that wherein third PMOS tube (MP3) source connects supply voltage, and drain terminal meets the 4th PMOS tube (MP4) and the 5th PMOS
Manage the source of (MP5)；4th PMOS tube (MP4) source and drain terminal connect the source and the 8th NMOS of third PMOS tube (MP3) respectively
Manage the drain terminal of (MN8)；The source of 8th NMOS tube (MN8) is grounded；The source of 5th PMOS tube (MP5) connects third PMOS tube
(MP3) drain terminal, grid end connect the drain terminal of the 4th PMOS tube (MP4) and the 8th NMOS tube (MN8), drain terminal ground connection；Third PMOS tube
(MP3), the grid end of the 4th PMOS tube (MP4) and the 8th NMOS tube (MN8) meets readout bit line RBL.
2. sram cell according to claim 1, which is characterized in that wherein the 5th PMOS tube (MP5) is feedback pipe, to
Reinforce the NMOS tube in phase inverter；Third NMOS tube (MN3) be it is pre- put pipe, to make readout bit line idle keep low level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410093326.3A CN104916309B (en) | 2014-03-13 | 2014-03-13 | Sub-threshold SRAM memory cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410093326.3A CN104916309B (en) | 2014-03-13 | 2014-03-13 | Sub-threshold SRAM memory cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104916309A CN104916309A (en) | 2015-09-16 |
| CN104916309B true CN104916309B (en) | 2019-04-23 |
Family
ID=54085329
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410093326.3A Active CN104916309B (en) | 2014-03-13 | 2014-03-13 | Sub-threshold SRAM memory cell |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104916309B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101227184A (en) * | 2008-02-19 | 2008-07-23 | 东南大学 | High speed duty ratio correcting circuit |
| CN102034525A (en) * | 2010-12-31 | 2011-04-27 | 东南大学 | Sub-threshold storage circuit interface circuit with high density and robustness |
| CN102098037A (en) * | 2009-12-15 | 2011-06-15 | 旺宏电子股份有限公司 | Clock circuit of integrated circuit |
| CN202067564U (en) * | 2010-12-31 | 2011-12-07 | 东南大学 | Interface circuit of subthreshold storage circuit with high density and high robustness |
| CN102592662A (en) * | 2011-01-11 | 2012-07-18 | 中国科学院声学研究所 | Storage unit and single-end low-swing bit line writing circuit |
| CN102890955A (en) * | 2011-07-21 | 2013-01-23 | 中国科学院微电子研究所 | Sensitive amplifier for large-scale flash memory |
| CN103544986A (en) * | 2013-10-09 | 2014-01-29 | 上海交通大学 | Design method of low-power-consumption 8-pipe SRAM (static random access memory) chip based on electric charge recycle and bit line classification |
-
2014
- 2014-03-13 CN CN201410093326.3A patent/CN104916309B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101227184A (en) * | 2008-02-19 | 2008-07-23 | 东南大学 | High speed duty ratio correcting circuit |
| CN102098037A (en) * | 2009-12-15 | 2011-06-15 | 旺宏电子股份有限公司 | Clock circuit of integrated circuit |
| CN102034525A (en) * | 2010-12-31 | 2011-04-27 | 东南大学 | Sub-threshold storage circuit interface circuit with high density and robustness |
| CN202067564U (en) * | 2010-12-31 | 2011-12-07 | 东南大学 | Interface circuit of subthreshold storage circuit with high density and high robustness |
| CN102592662A (en) * | 2011-01-11 | 2012-07-18 | 中国科学院声学研究所 | Storage unit and single-end low-swing bit line writing circuit |
| CN102890955A (en) * | 2011-07-21 | 2013-01-23 | 中国科学院微电子研究所 | Sensitive amplifier for large-scale flash memory |
| CN103544986A (en) * | 2013-10-09 | 2014-01-29 | 上海交通大学 | Design method of low-power-consumption 8-pipe SRAM (static random access memory) chip based on electric charge recycle and bit line classification |
Non-Patent Citations (2)
| Title |
|---|
| A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy;Verma N;《IEEE Journal of Solid-State Circuits》;20080128;141-149 * |
| An 8T Subthreshold SRAM Cell Utilizing Reverse Short Channel Effect for Write Margin and Read Performance Improvement;Kim T H;《Custom Integrated Circuits Conference》;20080121;241-244 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104916309A (en) | 2015-09-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8773895B2 (en) | Ultra low power memory cell with a supply feedback loop configured for minimal leakage operation | |
| CN102097123A (en) | Anti-single event effect static random access memory unit | |
| CN103578529B (en) | A kind of basis is write data and is changed the sub-threshold memory cell that power supply is powered | |
| CN104183269A (en) | Low-voltage single-end read-write SRAM (Static Random Access Memory) storage unit and control method | |
| CN104183268A (en) | Static random access memory structure | |
| CN103650052B (en) | Circuit and method for memorizer | |
| CN102034533A (en) | Static random storage unit with resetting function | |
| Wen et al. | Differential-read 8T SRAM cell with tunable access and pull-down transistors | |
| CN101625891B (en) | Sub-threshold storing unit circuit with high density and high robustness | |
| US9224455B1 (en) | Method and apparatus for bit-line sensing gates on an SRAM cell | |
| CN102592660B (en) | Single-ended operation subthreshold memory cell circuit | |
| CN103903645A (en) | Static random access memory unit with radiation reinforcement design | |
| CN107294516B (en) | Power-on reset circuit without static power consumption | |
| Yadav et al. | Analysis of leakage reduction technique on different SRAM cells | |
| CN112687308A (en) | Low-power consumption static random access memory unit and memory | |
| CN104916309B (en) | Sub-threshold SRAM memory cell | |
| Reddy et al. | Designing of schmitt trigger-based architecture 8T SRAM of 256 bit cells under 45 NM technology for low power applications | |
| CN104637531A (en) | SRAM (Static Random Access Memory) module and sensitivity amplifier circuit thereof | |
| Makosiej et al. | Ultra‐low leakage SRAM design with sub‐32 nm tunnel FETs for low standby power applications | |
| CN209880162U (en) | Hybrid 10T TFET-MOSFET SRAM cell circuit with low power consumption and write enhancement | |
| Akashe et al. | Simulation and stability analysis of 6T and 9T SRAM cell in 45 nm era | |
| CN103093809A (en) | Static random access memory unit resisting single event upset | |
| CN203456097U (en) | Static random access memory unit | |
| CN103500583B (en) | For the anti-sense bit line electric leakage memory cell of writing reinforcement of low-voltage register file | |
| Singh et al. | Simulation and analysis of sram cell structures at 90nm technology |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20201225 Address after: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee after: AoXin integrated circuit technology (Guangdong) Co.,Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220506 Address after: 510000 room 710, Jianshe building, No. 348, Kaifa Avenue, Huangpu District, Guangzhou, Guangdong Patentee after: Ruili flat core Microelectronics (Guangzhou) Co.,Ltd. Address before: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee before: AoXin integrated circuit technology (Guangdong) Co.,Ltd. |
|
| TR01 | Transfer of patent right |