CN104900542B - A kind of method for packing and structure of the semiconductor devices of characteristic size shrinkage - Google Patents
A kind of method for packing and structure of the semiconductor devices of characteristic size shrinkage Download PDFInfo
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- CN104900542B CN104900542B CN201410081016.XA CN201410081016A CN104900542B CN 104900542 B CN104900542 B CN 104900542B CN 201410081016 A CN201410081016 A CN 201410081016A CN 104900542 B CN104900542 B CN 104900542B
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Abstract
The present invention provides a kind of method for packing and structure of the semiconductor devices of characteristic size shrinkage, including provides the semiconductor base for being used for making the first product；The second product of the dimensional contraction according to the first product is made on a semiconductor substrate, and the second product has the first top layer metallic layer；Dielectric layer deposited；Copper metal is formed in connecting hole and is planarized and makes the first pad；Form the second top layer metallic layer aluminium；Insulating barrier is covered, makes the second pad；It is directed at the second pad and carries out wafer-level packaging test technology.The present invention is used as transition zone by increasing by the second pad in the second product and connecting the second top layer metallic layer of the first pad and the second pad, pad locations after dimensional contraction are converted to the pad locations of existing product, make it to be packaged using original packaging technology, in addition, by filling copper metal and making to flush with dielectric layer by copper metal polishing, both copper metallic face can have been made flat, it can also be ensured that there is good bonding quality in follow-up bonding technology.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, more particularly to a kind of semiconductor devices of characteristic size shrinkage
Method for packing and structure.
Background technology
With the continuous progress of semiconductor technology, the process node of characteristic size is less and less, and properties of product exponentially carry
Height, but manufacturing cost also exponentially rises substantially simultaneously.In the market competition of fierceness, it is desirable to which practitioner should constantly reform work
Skill node, keeps up with the step in market, while is also required to fully excavate the potentiality of existing process, is more preferably produced with obtaining cost performance
Product.
Therefore, industry is attempted to carry out certain proportion often on original Process ba- sis（Typically 80%~95% it
Between）Dimensional contraction（Shrink）, thus can be in the case where not increasing or increasing few cost, increasing can make on a wafer
The quantity of chip is made, further improves the performance of product.
So-called wafer-level packaging（WLP）Technique refers to not cut wafer, implements encapsulation directly on full wafer wafer,
Therefore have the advantages that cost is lower, packaging time is shorter.As shown in Figure 1a, original technique productions the first product top layer
Set and the technologic PAD of WLP in metal level（Pad）The technologic PAD of corresponding pattern P AD-1, WLP passes through described first
Pattern P AD-1 on product carries out contraposition encapsulation to the first product.However, as shown in Figure 1 b, using WLP techniques to original
The second product that dimensional contraction is carried out on Process ba- sis is packaged, because the technologic PAD of WLP can not after the contraction of the second product
Corresponded with the second product after contraction, cause the technologic PAD positions of WLP with being set in the top layer metallic layer of the second product
Pattern P AD-2 change, therefore the technologic PAD of WLP can not be by the pattern P AD-2 on second product to second
Product carries out contraposition encapsulation.The usual way of industry is to debug whole WLP techniques again to the second product after contraction, carries out performance
Test, this undoubtedly adds the destabilizing factor in performance test, and wastes the substantial amounts of time, extends the week of new product development
Phase.
Therefore, the present invention provides a kind of method, a transition zone is made on second product, makes the product after contraction complete
It can be packaged entirely using original packaging technology.Be included in the transition zone formed on the second product dielectric layer,
The second top-level metallic for make connecting hole in dielectric layer, filling out the metal in connecting hole and being produced on dielectric layer and connecting hole
Layer 6A.It is to deposit out redistributing layer in Kong Zhongyi steps according to the method in general filling hole（Metal and the second top layer metallic layer in hole
6A）, but this kind of method can cause difference in height and embedded angle, as shown in Fig. 2 being unfavorable for the progress of follow-up encapsulation procedure.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of partly leading for characteristic size shrinkage
The method for packing and structure of body device, for solving in the prior art, semiconductor devices can not be with existing after characteristic size shrinkage
Packaging technology carries out the problem of device encapsulation.
In order to achieve the above objects and other related objects, the present invention provides a kind of semiconductor devices of characteristic size shrinkage
Method for packing, the method for packing of the semiconductor devices of the characteristic size shrinkage comprise at least step：
Semiconductor base for making the first product is provided, made on the semiconductor base according to the described first production
The second product that the characteristic size of product is shunk, second product have the first top layer metallic layer positioned at top；
The dielectric layer deposited on first top layer metallic layer, and exposure first top layer is made in the dielectric layer
The connecting hole of metal level；
Copper metal is filled in the connecting hole, and planarizing the copper metal makes copper metallic face neat with dielectric layer surface
It is flat, the copper metal of filling forms the first pad；
Aluminum metal is deposited on first pad and dielectric layer surface and forms the second top layer metallic layer, using photoetching work
Skill is preserved for connecting the first pad of second product to second top in region between the second pad of first product
Layer metal level；
In second top layer metallic layer and the dielectric layer surface of exposure covering insulating barrier, and made in the insulating barrier
Make the second pad of exposure second top layer metallic layer；
Second pad is directed at using the wafer-level packaging test technology of first product, to including the semiconductor
Substrate and each several part on the semiconductor base are packaged test.
Preferably, the characteristic size shrinkage of second product is the 85%~97% of the first product feature size.
Preferably, the characteristic size shrinkage of second product is the 95% of the first product feature size.
Preferably, the characteristic size of first pad and the second pad is 30~100 μm.
Preferably, the semiconductor base comprises at least semiconductor device layer and formed in the semiconductor device layer
Metal interconnecting layer.
Preferably, first product is one kind in LDMOS, CMOS, MS, LG, CIS, EEPROM or FLASH.
Preferably, after the dielectric layer step is formed, in addition to ARC is formed on the dielectric layer, in institute
State the connecting hole that exposure first top layer metallic layer is made in dielectric layer and ARC.
Preferably, the thickness range of second top layer metallic layer is 0.5~2 μm.
The present invention also provides a kind of encapsulating structure of the semiconductor devices of characteristic size shrinkage, the characteristic size shrinkage
The encapsulating structure of semiconductor devices comprises at least：
For making the semiconductor base of the first product；
According to the second product of the characteristic size shrinkage of first product, second product is positioned at described semiconductor-based
On bottom and second product has the first top layer metallic layer positioned at top；
Dielectric layer, it is deposited on first top layer metallic layer；
First pad, it is made in the dielectric layer, first pad is copper metal；
Second top layer metallic layer, it is formed on the surface of first pad and dielectric layer and for connecting first weldering
Disk to region between the second pad of first product, second top layer metallic layer be aluminum metal layer；
Insulating barrier, it is covered in second top layer metallic layer and the dielectric layer surface of exposure；
Second pad, it is made in the insulating barrier；
Packaging body, second pad is directed at using the wafer-level packaging test technology of first product and partly led described
Body substrate and each several part on the semiconductor base carry out plastic packaging.
Preferably, the encapsulating structure also includes the anti-reflective coating positioned at the dielectric layer and the second top-level metallic interlayer
Layer, first pad are also located in the ARC.
Preferably, the thickness range of second top layer metallic layer is 0.5~2 μm.
As described above, the method for packing and structure of the semiconductor devices of the characteristic size shrinkage of the present invention, including step：Carry
For the semiconductor base for making the first product, the feature chi according to first product is made on the semiconductor base
The second product that little progress row shrinks, the product, which has, is located at top the first metal layer；Medium is deposited on second product
Layer, and the connecting hole for exposing first top layer metallic layer is made in the dielectric layer；Copper gold is filled in the connecting hole
Category, and polishing the copper metallic face makes copper metallic face be flushed with dielectric layer surface, the copper metal of filling forms the first pad；
Aluminum metal is deposited on first pad and dielectric layer surface and forms the second top layer metallic layer, is retained using photoetching process and used
In connecting the first pad of second product to second top layer metallic layer in region between the second pad of first product；
In second top layer metallic layer and the dielectric layer surface of exposure covering insulating barrier, and exposure institute is made in the insulating barrier
State the second pad of the second top layer metallic layer；Using the wafer-level packaging test technology alignment of first product second weldering
Disk, test is packaged to each several part including the semiconductor base and on the semiconductor base.Therefore the present invention
By increasing the first pad in the second product and second in the first pad and the first product for connecting the second product
Second top layer metallic layer of pad is converted to the pad locations after dimensional contraction the pad of existing product as transition zone again
Position, the product after dimensional contraction is packaged completely using original packaging technology, save used in encapsulation debugging
Time, can significantly shorten product development cycle.In addition, the present invention fills copper metal again by connecting hole by elder generation in connecting hole
In copper metal polishing make to flush with dielectric layer, so can both make copper metallic face flat, it can also be ensured that follow-up bonding etc.
Polymeric layer need not be made in technique in addition with regard to good bonding quality can be reached.
Brief description of the drawings
Fig. 1 a are that signal is overlooked in the pad contraposition that wafer-level packaging technique of the prior art is packaged to the first product
Figure.
Fig. 1 b are the pad that wafer-level packaging technique of the prior art is packaged to the second product after dimensional contraction
The schematic top plan view that position and size change during contraposition.
Fig. 2 is the structural representation that embedded angle occurs in the second top-level metallic layer surface of semiconductor devices in the prior art.
Fig. 3 is the schematic flow sheet of the method for packing of the semiconductor devices of the characteristic size shrinkage of the present invention；
Fig. 4 a to Fig. 4 d are presented by each step in the semiconductor packages method of the characteristic size shrinkage of the present invention
Structural representation.
Component label instructions
1 semiconductor base
11 semiconductor device layers
12 metal interconnecting layers
2 first top layer metallic layers
3 dielectric layers
4 ARCs
5 first pads
6,6A second top layer metallic layers
7 insulating barriers
8 second pads
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Refer to accompanying drawing.It should be noted that only explanation is of the invention in a schematic way for the diagram provided in the present embodiment
Basic conception, then in schema only display with relevant component in the present invention rather than according to component count during actual implement, shape
Shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its component cloth
Office's kenel may also be increasingly complex.
The present invention provides a kind of method of the encapsulation of the semiconductor devices of characteristic size shrinkage, as shown in figure 3, the feature
The method for packing of the semiconductor devices of dimensional contraction comprises at least following steps：
S1, there is provided for making the semiconductor base of the first product, made on the semiconductor base according to described the
The second product that the characteristic size of one product is shunk, second product, which has, is located at the top layer metallic layer of top first；
S2, the dielectric layer deposited on first top layer metallic layer, and exposure described first is made in the dielectric layer
The connecting hole of top layer metallic layer；
S3, copper metal is filled in the connecting hole, and planarize the copper metal to make copper metallic face and dielectric layer table
Face flushes, and the copper metal of filling forms the first pad；
S4, aluminum metal the second top layer metallic layer of formation is deposited on first pad and dielectric layer surface, using light
Carving technology is preserved for connecting the first pad of second product to of region between the second pad of first product
Two top layer metallic layers；
S5, in second top layer metallic layer and the dielectric layer surface of exposure covering insulating barrier, and in the insulating barrier
Middle the second pad for making exposure second top layer metallic layer；
S6, second pad is directed at using the wafer-level packaging test technology of first product, to including described half
Conductor substrate and each several part on the semiconductor base are packaged test.
The method for packing of the semiconductor devices contraction size of the present invention is described in detail below in conjunction with the accompanying drawings.
Step S1 is first carried out, referring to Fig. 4 a, there is provided for making the semiconductor base 1 of the first product, partly led described
The second product shunk according to the characteristic size of first product is made in body substrate 1, second product has position
In the first top layer metallic layer of top 2.
Wherein, the first described product can be LDMOS (Laterally Diffused
Metal Oxide SEMI conductor, LDMOS), in the various manufacturing process such as CMOS, MS, LG, CIS, EEPROM, FLASH
Any one.Also, the semiconductor base 1 comprises at least semiconductor device layer 11 and in the semiconductor device layer 11
The metal interconnecting layer 12 of middle formation.
Second product comprises at least the first top layer metallic layer 2 positioned at top, and second product need to be according to described
The characteristic size shrinkage of first product is to 85%~97%, in highly preferred embodiment of the present invention, the feature chi of second product
It is very little to be punctured into the 95% of the first product feature size.
Then step S2 is performed, referring to Fig. 4 b, the dielectric layer deposited 3 on first top layer metallic layer 2, and given an account of
The connecting hole of exposure first top layer metallic layer 2 is made in matter layer 3.
Then step S3 is performed, with continued reference to Fig. 4 b, copper metal is filled in the connecting hole, and planarizes the copper gold
Category makes copper metallic face be flushed with dielectric layer surface, and the copper metal of filling forms the first pad 5.
Further, in highly preferred embodiment of the present invention, it can also be coated with the surface of the dielectric layer 3 and substitute light
The ARC of photoresist（DRC）4, the ARC 4 is then opened using photoetching process, with the ARC 4
For mask, the connecting hole for exposing first top layer metallic layer 2 is formed in the dielectric layer 3.Then, in the dielectric layer 3
And with depositing copper metal in the connecting hole of ARC 4 disposed thereon；It is flat using CMP process afterwards
Changing copper metal makes the surface of copper metal be flushed with the surface of ARC 4, and the copper metal being polished in connecting hole forms described
First pad 5.Coating photoresist on the surface of the usual dielectric layer 3, causes because metal level can permeate the photoresist
Device contamination, there is performance deficiency.
Step S4 is performed again, refers to Fig. 4 c, and aluminum metal shape is deposited on first pad 5 and the surface of dielectric layer 3
Into the second top layer metallic layer 6, the first pad 5 for being preserved for connecting second product using photoetching process is produced to described first
Second top layer metallic layer 6 in region between second pad 8 of product.
Further, in highly preferred embodiment of the present invention, in first pad 5 and the ARC 4
Surface deposition aluminum metal, second top layer metallic layer 6 is formed, and be preserved for connecting first pad using photoetching process
5 to region between the second pad 8 of first product the second top layer metallic layer 6.Due to depositing for the ARC 4
It can prevent the second top layer metallic layer 6 disposed thereon during photoetching from the problems such as diffraction of light, interference occur.
First pad 5 is used for the metal interconnecting layer 12 in the semiconductor base 1 and second top-level metallic
Layer 6 is electrically connected.
It should be noted that the method deposited in traditional handicraft using a step aluminium, full connection is being filled by aluminum metal
Continuing deposit aluminum metal behind hole makes aluminum metal be covered on dielectric layer, forms the second top layer metallic layer, now, the aluminium in connecting hole
Metal（That is the first pad）It is integrated with the second top layer metallic layer, the second top layer metallic layer that this technique is formed is easily in generation
Fall into, produce difference in height and embedded angle, cause the second top layer metallic layer uneven surface, extra system is needed when follow-up gold thread is bonded
Make one layer of polymeric layer planarization to improve bonding quality.And the fill process of the connecting hole of the present invention is with forming the second top
The technique of layer metal level 5 is the two-step process of separation, wherein, filling connecting hole technique is first to deposit metal, is polished afterwards
Technique is allowed to flat, and this second top layer metallic layer 6 for allowing for being subsequently formed will not form embedded angle, improve the reliable of bonding
Property；And be filled in connecting hole is that the first pad 5 is the easy copper metal for carrying out flatening process, and the second top layer formed
Metal level 6 is aluminum metal, because copper metal has excellent electric conductivity, the aluminium of the second top layer metallic layer 6 can be fabricated to compared with
Thin thickness, so as to further reduce the overall dimensions of device.
The thickness of second top layer metallic layer 6 can select between 0.5~2 μm, in the present embodiment, second top
The thickness of layer metal level 6 is 1 μm.
Then perform in step S5, refer to Fig. 4 c and 4d, in second top layer metallic layer 6 and the dielectric layer of exposure
3 surfaces cover insulating barrier 7, and the second pad 8 of exposure second top layer metallic layer 6 is made in the insulating barrier 7.
The method for making second pad 8 is preferably served only for the explanation of effect of the present invention using dry etching, but not
For limiting the making of second pad.
Step S6 is finally performed, second pad 8 is directed at using the wafer-level packaging test technology of first product,
The semiconductor base 1, the second product, dielectric layer 3, the first pad 5, the second top layer metallic layer 6, insulating barrier 7 and second are welded
Disk 8 is packaged, and is formed a packaging body, is then tested.
Further, the ARC 4 as described in the top layer metallic layer 6 of dielectric layer 3 and second being also present, then using institute
The wafer-level packaging test technology of the first product is stated, to the semiconductor base 1, the second product, dielectric layer 3, ARC
4th, the first pad 5, the second top layer metallic layer 6, the pad 8 of insulating barrier 7 and second are packaged, and form the packaging body, Ran Houjin
Row test.
The present invention also provides a kind of encapsulating structure of the semiconductor devices of characteristic size shrinkage, as Fig. 4 d are shown as the present invention
The encapsulating structure schematic cross-section of the semiconductor devices of characteristic size shrinkage in preferred embodiment.As shown in figure 4d, the feature
The encapsulating structure of the semiconductor devices of dimensional contraction comprises at least：
For making the semiconductor base 1 of the first product；The semiconductor base 1 comprise at least semiconductor device layer 11 with
And the metal interconnecting layer 12 formed in the semiconductor device layer 11.
The second product that characteristic size according to first product is shunk, second product are partly led positioned at described
In body substrate 1, and second product has the first top layer metallic layer 2 positioned at top；
Dielectric layer 3, the dielectric layer 3 are deposited on first top layer metallic layer 2；
First pad 5, first pad 5 are made in the dielectric layer 3, and first pad 5 is copper metal；
Second top layer metallic layer 6, second top layer metallic layer 6 are formed at the surface of first pad 5 and dielectric layer 3
Region between the second pad 8 upper and that first product is arrived for connecting first pad 5, second top-level metallic
Layer 6 is aluminum metal；And the thickness of the aluminum metal can select in 0.5~2 μm.
Insulating barrier 7, the insulating barrier 7 are covered in the table of second top layer metallic layer 6 and the dielectric layer 3 exposed
Face；
Second pad 8, second pad 8 are made in the insulating barrier 7；
Packaging body, the packaging body use the wafer-level packaging test technology of first product, alignment second weldering
The semiconductor base 1 and each several part on the semiconductor base 1 are carried out plastic packaging by disk 8.
Each several part on the semiconductor base is respectively second product, dielectric layer 3, the first pad 5, second
Top layer metallic layer 6, the pad 8 of insulating barrier 7 and second.
Further, the encapsulating structure of the semiconductor devices of the characteristic size shrinkage also includes an ARC 4, institute
ARC 4 is stated between the top layer metallic layer 6 of dielectric layer 3 and second, and first pad 5 is also located at the anti-reflective
Penetrate in coating 4, then each several part on the semiconductor base 1 be respectively with the first top layer metallic layer 2 the second product,
Dielectric layer 3, ARC 4, the first pad 5, the second top layer metallic layer 6, the pad 8 of insulating barrier 7 and second.
In summary, the present invention provides a kind of method for packing and structure of the semiconductor devices of characteristic size shrinkage, passes through
Increase by first pad and for connecting the second top layer metallic layer of first pad and the second pad as transition zone,
Pad locations after dimensional contraction are converted to the pad locations of existing product again, make the product after dimensional contraction completely can be with
It is packaged using original packaging technology, saves the encapsulation debugging time used, can significantly shorten product development cycle.
Further, since need not testing and measuring technology again, but use unified original packaging technology, accordingly reduce new production
Uncertain factor in product development process, the product after size reduction and existing product preferably can be subjected to performance comparison.
Make and medium in addition, the present invention fill in connecting hole copper metal by elder generation and again polishes the copper metal in connecting hole
Layer flushes, and so can both make copper metallic face flat, it can also be ensured that need not be made in addition in the technique such as follow-up bonding poly-
Compound layer is with regard to that can reach good bonding quality.And because the first pad is copper metal, it has excellent electric conductivity, because
This, the second top layer metallic layer aluminium lamination can be fabricated to relatively thin thickness, so as to further reduce the overall dimensions of device.
So the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (11)
- A kind of 1. method for packing of the semiconductor devices of characteristic size shrinkage, it is characterised in that the half of the characteristic size shrinkage The method for packing of conductor device comprises at least step：Semiconductor base for making the first product is provided, made on the semiconductor base according to first product The second product that characteristic size is shunk, second product have the first top layer metallic layer positioned at top；The dielectric layer deposited on first top layer metallic layer, and exposure first top-level metallic is made in the dielectric layer The connecting hole of layer；Copper metal is filled in the connecting hole, and planarizing the copper metal makes copper metallic face be flushed with dielectric layer surface, The copper metal of filling forms the first pad；Aluminum metal is deposited on first pad and dielectric layer surface and forms the second top layer metallic layer, the second top layer gold It from first pad is different structured metal layers to belong to layer, is preserved for connecting the of second product using photoetching process Second top layer metallic layer of one pad to region between the second pad of first product；In second top layer metallic layer and the dielectric layer surface of exposure covering insulating barrier, and made cruelly in the insulating barrier Reveal the second pad of second top layer metallic layer, second pad is connected directly to institute by second top layer metallic layer State the first pad；Second pad is directed at using the wafer-level packaging test technology of first product, to including the semiconductor base And each several part on the semiconductor base is packaged test.
- 2. the method for packing of the semiconductor devices of characteristic size shrinkage according to claim 1, it is characterised in that：Described The characteristic size shrinkage of two products is the 85%~97% of the first product feature size.
- 3. the method for packing of the semiconductor devices of characteristic size shrinkage according to claim 2, it is characterised in that：Described The characteristic size shrinkage of two products is the 95% of the first product feature size.
- 4. the method for packing of the semiconductor devices of characteristic size shrinkage according to claim 1, it is characterised in that：Described The characteristic size of one pad and the second pad is 30~100 μm.
- 5. the method for packing of the semiconductor devices of characteristic size shrinkage according to claim 1, it is characterised in that：Described half Conductor substrate comprises at least semiconductor device layer and the metal interconnecting layer formed in the semiconductor device layer.
- 6. the method for packing of the semiconductor devices of characteristic size shrinkage according to claim 1, it is characterised in that：Described One product is one kind in LDMOS, CMOS, MS, LG, CIS, EEPROM or FLASH.
- 7. the method for packing of the semiconductor devices of characteristic size shrinkage according to claim 1, it is characterised in that：Formed After the dielectric layer step, in addition to ARC is formed on the dielectric layer, in the dielectric layer and ARC The middle connecting hole for making exposure first top layer metallic layer.
- 8. the method for packing of the semiconductor devices of characteristic size shrinkage according to claim 1, it is characterised in that：Described The thickness range of two top layer metallic layers is 0.5~2 μm.
- A kind of 9. encapsulating structure of the semiconductor devices of characteristic size shrinkage, it is characterised in that the half of the characteristic size shrinkage The encapsulating structure of conductor device comprises at least：For making the semiconductor base of the first product；According to the second product of the characteristic size shrinkage of first product, second product is located on the semiconductor base And second product has the first top layer metallic layer positioned at top；Dielectric layer, it is deposited on first top layer metallic layer；First pad, it is made in the dielectric layer, first pad is copper metal；Second top layer metallic layer, it is formed on the surface of first pad and dielectric layer and is arrived for connecting first pad Region between second pad of first product, second top layer metallic layer are aluminum metal layer；Insulating barrier, it is covered in second top layer metallic layer and the dielectric layer surface of exposure；Second pad, it is made in the insulating barrier；Packaging body, being directed at second pad using the wafer-level packaging test technology of first product will be described semiconductor-based Bottom and each several part on the semiconductor base carry out plastic packaging.
- 10. the encapsulating structure of the semiconductor devices of characteristic size shrinkage according to claim 9, it is characterised in that：It is described Encapsulating structure also includes the ARC positioned at the dielectric layer and the second top-level metallic interlayer, and first pad is also located at In the ARC.
- 11. the encapsulating structure of the semiconductor devices of characteristic size shrinkage according to claim 9, it is characterised in that：It is described The thickness range of second top layer metallic layer is 0.5~2 μm.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1638102A (en) * | 2003-12-24 | 2005-07-13 | 富士通株式会社 | High-frequency device |
| CN102832181A (en) * | 2011-06-13 | 2012-12-19 | 矽品精密工业股份有限公司 | Chip Scale Package |
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| JP2004079716A (en) * | 2002-08-14 | 2004-03-11 | Nec Electronics Corp | Chip size package type package for semiconductor and its manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1638102A (en) * | 2003-12-24 | 2005-07-13 | 富士通株式会社 | High-frequency device |
| CN102832181A (en) * | 2011-06-13 | 2012-12-19 | 矽品精密工业股份有限公司 | Chip Scale Package |
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