CN104900526A - VDMOS and manufacture method for the same - Google Patents
VDMOS and manufacture method for the same Download PDFInfo
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- CN104900526A CN104900526A CN201410083225.8A CN201410083225A CN104900526A CN 104900526 A CN104900526 A CN 104900526A CN 201410083225 A CN201410083225 A CN 201410083225A CN 104900526 A CN104900526 A CN 104900526A
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Abstract
The invention discloses a VDMOS and a manufacture method for the same. The manufacture method comprises steps of successively generating a gate oxide layer, a polysilicon layer and a P- body area, injecting N type impurities in the P- body area to form an N type source area, wherein the N type source area comprises an N- source area and an N+ source area and the N+ source area is positioned between the gate oxide layer and the N-source area, successively forming an gate oxide layer, a P+ area, an intermediate layer, a contact hole and a metal layer on the polysilicon layer and grid oxidization layer the gate oxide layer in order to enable the metal layer to connect with the side of each of the N- source area, the N+ source area, the gate oxide layer, the oxide layer, and the intermediate layer and the P+ area. The embodiment of the invention effectively solves the technical problems in the prior art that the unclamped inductive switch is low in the capability.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of vertical DMOS transistor (Vertical Double-diffused MOSFET; Be called for short: manufacture method VDMOS) and VDMOS.
Background technology
Fig. 1 is the structure principle chart of prior art planar-type VDMOS, as shown in Figure 1, in order to improve non-clamp perception switch (UIS) ability, namely prevent the triode ON that source region, tagma and N-type epitaxy layer three are formed, the method that prior art adopts is for get up source region and tagma by metal short circuit.
But know from Fig. 1, its non-clamp perception switch UIS ability of existing VDMOS is low, still exists and improves space.Such as: usual existing VDMOS, its source region doping content is higher, and source region contacts with P+ district as N+P contacts, and this contact can increase above-mentioned triode ON ability; Said circumstances all causes non-clamp perception switch (UIS) ability of VDMOS to decline.
Summary of the invention
The invention provides manufacture method and the VDMOS of a kind of VDMOS, for reducing the ducting capacity of the triode ON formed with source region, tagma and N-type epitaxy layer three, and then improve UIS ability.
On the one hand, the embodiment of the present invention provides the manufacture method of a kind of VDMOS, comprising:
N-type epitaxy layer generates gate oxide, polysilicon layer, P-tagma successively;
Inject N-type impurity in described P-tagma and form N-type source region, described N-type source region comprises N-source region and N+ source region; Described N+ source region is between described gate oxide and N-source region;
Described polysilicon layer and described gate oxide are formed oxide layer, P+ district, dielectric layer, contact hole and metal level successively, is connected with the side of every layer in described N-source region, N+ source region, gate oxide, oxide layer, dielectric layer and described P+ district respectively to make described metal level.
On the other hand, the embodiment of the present invention provides a kind of VDMOS, comprise: N-type substrate, in the N-type epitaxy layer that described N-type substrate upper surface is formed, at the gate oxide that described N-type epitaxy layer upper surface is formed, at the polysilicon layer that described gate oxide upper surface is formed, the P-tagma that described N-type substrate is formed, by the N-type source region injected N-type impurity in described P-tagma and formed, described N-type source region comprises N-source region and N+ source region; Described N+ source region is between described gate oxide and N-source region; The P+ tagma formed in described P-tagma, the contact hole formed above described P+ tagma, and in the upper surface, described contact hole of described dielectric layer and described N-type substrate lower surface formed metal level;
Wherein, described metal level is connected with the side of every layer in described N-source region, described N+ source region, described gate oxide, described oxide layer and described dielectric layer and described P+ district respectively.
The manufacture method of VDMOS provided by the invention and VDMOS, be divided into two parts by N-type source region; Namely in N-type source region, in the subregion of the first oxide layer, form N+ source region, in N-type source region, form N-source region away from the subregion of the first oxide layer.This N-type source structure is under the prerequisite ensureing its required impurity concentration that normally works, N-type source region and tagma contact-making surface is made to be that low-doped N-source region contacts with P type tagma, effectively reduce the emitter injection efficiency of the parasitic triode formed with source-body-epitaxial loayer, thus reduce the possibility of parasitic triode conducting, enhance the UIS ability of VDMOS.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of VDMOS of the prior art;
The flow chart of a manufacture method embodiment of the VDMOS that Fig. 2 provides for the embodiment of the present invention;
Fig. 3 a is the schematic diagram of the formation method of gate oxide and polysilicon layer in the embodiment of the present invention;
Fig. 3 b is the schematic diagram of the formation method in P-tagma in the embodiment of the present invention
Fig. 3 c is the schematic diagram of the formation method in N-type source region in the embodiment of the present invention;
Fig. 3 d is the schematic diagram of the formation method in oxide layer and P+ tagma in the embodiment of the present invention;
Fig. 3 e is the schematic diagram of the generation type of embodiment of the present invention dielectric layer and contact hole;
Fig. 3 f is the schematic diagram of the generation type of metal level in the embodiment of the present invention;
Fig. 3 g is the schematic diagram of contact hole inner convex platform structure forming manner in the embodiment of the present invention;
Fig. 3 h is the schematic diagram of a P+ type district generation type in the embodiment of the present invention
Fig. 3 i is contact hole and a simultaneous formation schematic diagram in P+ type district in the embodiment of the present invention.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described.For convenience of description, zoomed in or out the size of different layers and region, so size shown in figure and ratio might not represent actual size, also do not reflect the proportionate relationship of size.
The flow chart of a manufacture method embodiment of the VDMOS that Fig. 2 provides for the embodiment of the present invention, as shown in Figure 2, the method specifically comprises:
S201, N-type epitaxy layer generates gate oxide, polysilicon layer, P-tagma successively;
In the present embodiment, Fig. 3 a is the schematic diagram of the formation method of gate oxide and polysilicon layer in the embodiment of the present invention, as shown in Figure 3 a, this gate oxide is formed in the upper surface of N-type epitaxy layer, and forms polysilicon layer at the upper surface of this gate oxide.Wherein, N-type epitaxy layer is formed in the upper surface of N-type substrate.This growth of gate oxide layer temperature is more than or equal to 900 DEG C, and is less than or equal to 1100 DEG C; Its thickness is more than or equal to 0.05um, and is less than or equal to 0.20um.This polysilicon layer growth temperature is more than or equal to 500 DEG C, and is less than or equal to 700 DEG C; Its thickness is more than or equal to 0.3um, and is less than or equal to 0.8um.
In addition, Fig. 3 b is the schematic diagram of the formation method in P-tagma in the embodiment of the present invention, and as shown in Figure 3 b, the generation type in P-tagma is specially: inject boron ion to form P-tagma, and wherein, the dosage of boron ion is more than or equal to 1.0E13/cm
2, and be less than or equal to 1.0E15/cm
2; Its energy is more than or equal to 100KEV, and is less than or equal to 150KEV.Then adopt to preset to drive in temperature and preset and drive in the time and drive in this P-tagma, wherein, this is preset and drives in temperature and be more than or equal to 1100 DEG C, and is less than or equal to 1200 DEG C; Preset and drive in the time and be more than or equal to 50 minutes, and be less than or equal to 200 minutes.
S202, inject N-type impurity in P-tagma and form N-type source region, this N-type source region comprises N-source region and N+ source region; This N+ source region is between gate oxide and N-source region;
Fig. 3 c is the schematic diagram of the formation method in N-type source region in the embodiment of the present invention, and as shown in Figure 3 c, the generation type in N-type source region is specially: inject N-type impurity in P-tagma and form N-type source region, this N-type source region comprises N-source region and N+ source region; Wherein, N+ source region is between gate oxide and N-source region.
Show in particular a kind of specific implementation injecting N-type impurity in the present embodiment: injection process is divided into twice injection, first inject phosphonium ion in P-tagma to form the N-region portions in N-type source region, the dosage of this phosphonium ion is more than or equal to 1.0E13/cm
2, and be less than or equal to 1.0E14/cm
2; Its energy for being more than or equal to 100KEV, and is less than or equal to 150KEV; Secondly, re-inject arsenic ion in P-tagma and form N+ region portions, the dosage of this arsenic ion is more than or equal to 1.0E15/cm
2, and be less than or equal to 1.0E16/cm
2; Its energy for being more than or equal to 100KEV, and is less than or equal to 150KEV.Before injection arsenic ion, if the thickness of above-mentioned gate oxide is more than 0.05um, then need the etching of carrying out gate oxide, to make the thickness of gate oxide be less than or equal to 0.05um, otherwise the injection of arsenic ion can be affected.
S203 forms oxide layer, P+ district, dielectric layer, contact hole and metal level successively on described polysilicon layer and described gate oxide, is connected respectively to make metal level with the side of every layer in N-source region, N+ source region, gate oxide, oxide layer, dielectric layer and P+ district;
In the present embodiment, Fig. 3 d is the schematic diagram of the formation method in oxide layer and P+ tagma in the embodiment of the present invention, as shown in Figure 3 d, the generation type in this oxide layer and P+ tagma is specially: adopt the method for low-pressure chemical vapor phase deposition to form oxide layer at the upper surface of polysilicon layer and gate oxide, wherein, the growth temperature of this oxide layer is more than or equal to 600 DEG C, and is less than or equal to 800 DEG C; Its thickness is more than or equal to 0.1um, and is less than or equal to 0.3um.Then inject boron ion (the P type ion namely shown in Fig. 3 d) to form this P+ tagma, wherein, this boron ion dose is more than or equal to 1.0E15/cm
2, and be less than or equal to 1.0E16/cm
2; Its energy for being more than or equal to 100KEV, and is less than or equal to 150KEV.
In addition, Fig. 3 e is the schematic diagram of the generation type of embodiment of the present invention dielectric layer and contact hole, and as shown in Figure 3 e, dielectric layer is made up of undope silicon dioxide and phosphorosilicate glass, and wherein, the thickness of plain silicon dioxide is 0.2um; The thickness of phosphorosilicate glass is 0.8um.
Fig. 3 f is the schematic diagram of the generation type of metal level in the embodiment of the present invention, and as illustrated in figure 3f, the metal level in dielectric layer side can be referred to as front metal layer.Metal layer on back (or titanium nickeline composite bed) is referred to as at the metal level of N-type substrate side.From Fig. 3 f, front metal layer is connected with the side of N-source region, N+ source region, gate oxide, oxide layer, dielectric layer and described P+ district respectively.
The manufacture method of VDMOS provided by the invention, N-type epitaxy layer generates gate oxide, polysilicon layer, P-tagma successively; Inject N-type impurity in P-tagma and form N-type source region, this N-type source region comprises N-source region and N+ source region; This N+ source region is between described gate oxide and N-source region; Form oxide layer, P+ district, dielectric layer, contact hole and metal level more successively, be connected with the side of N-source region, N+ source region, gate oxide, oxide layer, dielectric layer and described P+ district respectively to make metal level.N-type source region is divided into two parts by the program; Namely in N-type source region, in the subregion of the first oxide layer, form N+ source region, in N-type source region, form N-source region away from the subregion of the first oxide layer.This N-type source structure is under the prerequisite ensureing its required impurity concentration that normally works, N-type source region and tagma contact-making surface is made to be that low-doped N-source region contacts with P type tagma, effectively reduce the emitter injection efficiency of the parasitic triode formed with source-body-epitaxial loayer, thus reduce the possibility of parasitic triode conducting, enhance the UIS ability of VDMOS.
Further, on above-mentioned basis embodiment illustrated in fig. 2, a kind of specific implementation forming contact hole is in step 203:
Preset technological process is adopted to form the original contact hole structure of contact hole; This original contact hole structure is the structure of contact hole as shown in figure 3e.The sidewall of its contact hole is a smooth surface.
Adopt hydrofluoric acid to carry out wet etching to the sidewall of original contact hole, remove part gate oxide, oxide layer and dielectric layer that N+ area surface covers, form boss structure with position, N+ source region on the sidewall of contact hole.Fig. 3 g is the schematic diagram of contact hole inner convex platform structure forming manner in the embodiment of the present invention.Finally using the original contact hole structure that comprises this boss structure structure as contact hole final in embodiment illustrated in fig. 2, the filling of metal level can be proceeded subsequently, got up in source region and P-tagma short circuit.This boss structure makes the contact area in metal level and source region increase, and short circuit effect improves, and that can reduce the parasitic triode conducting formed with source-body-epitaxial loayer further may.Thus further improve the UIS ability of VDMOS device.
Further, on above-mentioned basis embodiment illustrated in fig. 2, after formation contact hole, and before forming metal level, also comprise:
Implanting p-type impurity in the contact hole, to form a P+ type district in P-tagma.Fig. 3 h is the schematic diagram of a P+ type district generation type in the embodiment of the present invention.As illustrated in figure 3h, in contact hole, implanting p-type impurity is as boron ion, and to form a P+ type district, wherein, the dosage injecting boron ion is more than or equal to 1.0E15/cm
2, and be less than or equal to 1.0E16/cm
2; Its energy for being more than or equal to 100KEV, and is less than or equal to 150KEV.One P+ type district can reduce the resistance in P-tagma further, increases the short circuit effect in source region and P-tagma, thus further improves the UIS ability of VDMOS device.
Further, on above-mentioned basis embodiment illustrated in fig. 2, also the boss structure of the formation of above-mentioned contact hole can be combined with a P+ type plot structure, namely form contact hole as shown in figure 3i and a simultaneous formation schematic diagram in P+ type district.
In the present embodiment, form by area surface in contact hole the contact area that above-mentioned boss structure increases source region and metal level; And in P-tagma, form the overall electrical resistance that a P+ type district reduces P-tagma, increase the short circuit effect in source region and P-tagma, thus further improve the UIS ability of VDMOS device.
Present invention also offers a kind of VDMOS, comprise: N-type substrate, in the N-type epitaxy layer that N-type substrate upper surface is formed, at the gate oxide that N-type epitaxy layer upper surface is formed, at the polysilicon layer that gate oxide upper surface is formed, N-type substrate the P-tagma formed, inject the N-type source region that formed of N-type impurity by P-tagma, and described N-type source region comprises N-source region and N+ source region; This N+ source region is between gate oxide and N-source region; The P+ tagma formed in P-tagma, the contact hole formed above P+ tagma, and in the upper surface, described contact hole of dielectric layer and N-type substrate lower surface formed metal level;
Wherein, metal level is connected with the side of every layer in N-source region, N+ source region, gate oxide, oxide layer, dielectric layer and P+ district respectively.
Further, also comprise: the subregion contacted with the sidewall of gate oxide, oxide layer and dielectric layer in above-mentioned metal level, it extends to N+ area surface in the horizontal direction, forms boss structure with the surface making metal level contact with N+ source region.
Further, also comprise: the P+ type district formed in P-tagma, a P+ type district contacts with P+ district.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (9)
1. a manufacture method of VDMOS, is characterized in that, comprising:
N-type epitaxy layer generates gate oxide, polysilicon layer, P-tagma successively;
Inject N-type impurity in described P-tagma and form N-type source region, described N-type source region comprises N-source region and N+ source region; Described N+ source region is between described gate oxide and N-source region;
Described polysilicon layer and described gate oxide are formed oxide layer, P+ district, dielectric layer, contact hole and metal level successively, is connected with the side of every layer in described N-source region, N+ source region, gate oxide, oxide layer, dielectric layer and described P+ district respectively to make described metal level.
2. method according to claim 1, is characterized in that, described in described P-tagma injection N-type impurity formation N-source region and N+ source region, comprising:
Inject phosphonium ion in described P-tagma and form N-source region;
In described P-tagma, inject arsenic ion form N+ source region.
3. method according to claim 2, is characterized in that, described when described P-tagma injection N-type impurity forms N-source region, the N-type impurity of injection is phosphonium ion, and implantation dosage is 1.0E13 ~ 1.0E14/cm
2, Implantation Energy is 100kEV ~ 150KEV.
4. method according to claim 2, is characterized in that, the described N-type impurity that re-injects in described N-source region is when forming N+ source region, and the N-type impurity of injection is arsenic ion, and implantation dosage is 1.0E15 ~ 1.0E16/cm
2, Implantation Energy is 100kEV ~ 150KEV.
5. the method according to any one of claim 1-4, is characterized in that, forms the process of described contact hole, comprising:
Preset technological process is adopted to form the original contact hole structure of described contact hole;
The sidewall of hydrofluoric acid to described original contact hole is adopted to carry out wet etching, remove the described gate oxide of part, described oxide layer and described dielectric layer that described N+ area surface covers, form boss structure with position, described N+ source region on the sidewall of described contact hole;
To the described original contact hole structure of described boss structure be comprised as final described contact hole.
6. the method according to any one of claim 1-4, is characterized in that, after the described contact hole of formation, and before forming described metal level, also comprises:
Implanting p-type impurity in described contact hole, to form a P+ type district in described P-tagma.
7. a VDMOS, it is characterized in that, comprise: N-type substrate, in the N-type epitaxy layer that described N-type substrate upper surface is formed, at the gate oxide that described N-type epitaxy layer upper surface is formed, at the polysilicon layer that described gate oxide upper surface is formed, the P-tagma that described N-type substrate is formed, by the N-type source region injected N-type impurity in described P-tagma and formed, described N-type source region comprises N-source region and N+ source region; Described N+ source region is between described gate oxide and N-source region; The P+ tagma formed in described P-tagma, the contact hole formed above described P+ tagma, and in the upper surface, described contact hole of described dielectric layer and described N-type substrate lower surface formed metal level;
Wherein, described metal level is connected with the side of every layer in described N-source region, described N+ source region, described gate oxide, described oxide layer and described dielectric layer and described P+ district respectively.
8. VDMOS according to claim 7, it is characterized in that, the subregion contacted with the sidewall of described gate oxide, described oxide layer and described dielectric layer in described metal level, it extends to described N+ area surface in the horizontal direction, forms boss structure with the surface making described metal level contact with described N+ source region.
9. the VDMOS according to claim 7 or 8, is characterized in that, also comprises:
The P+ type district formed in described P-tagma, a described P+ type district contacts with described P+ district.
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| CN201410083225.8A CN104900526B (en) | 2014-03-07 | 2014-03-07 | The manufacturing method and VDMOS of VDMOS |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105931970A (en) * | 2016-06-30 | 2016-09-07 | 杭州士兰集成电路有限公司 | Planar gate power device structure and formation method therefor |
| CN107331621A (en) * | 2017-07-14 | 2017-11-07 | 欧阳慧琳 | A kind of vertical bilateral diffusion field-effect tranisistor and preparation method thereof |
| CN107342224A (en) * | 2016-05-03 | 2017-11-10 | 北大方正集团有限公司 | The preparation method of VDMOS device |
| WO2020057425A1 (en) * | 2018-09-21 | 2020-03-26 | 无锡华润上华科技有限公司 | Vertical double-diffusion semiconductor component and manufacturing method therefor |
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| CN1937176A (en) * | 2005-09-23 | 2007-03-28 | 半导体元件工业有限责任公司 | Method of forming a low resistance semiconductor contact and structure therefor |
| US20100090273A1 (en) * | 2008-10-09 | 2010-04-15 | Robert Bruce Davies | Transistor structure having dual shield layers |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1937176A (en) * | 2005-09-23 | 2007-03-28 | 半导体元件工业有限责任公司 | Method of forming a low resistance semiconductor contact and structure therefor |
| US20100090273A1 (en) * | 2008-10-09 | 2010-04-15 | Robert Bruce Davies | Transistor structure having dual shield layers |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107342224A (en) * | 2016-05-03 | 2017-11-10 | 北大方正集团有限公司 | The preparation method of VDMOS device |
| CN105931970A (en) * | 2016-06-30 | 2016-09-07 | 杭州士兰集成电路有限公司 | Planar gate power device structure and formation method therefor |
| CN107331621A (en) * | 2017-07-14 | 2017-11-07 | 欧阳慧琳 | A kind of vertical bilateral diffusion field-effect tranisistor and preparation method thereof |
| WO2020057425A1 (en) * | 2018-09-21 | 2020-03-26 | 无锡华润上华科技有限公司 | Vertical double-diffusion semiconductor component and manufacturing method therefor |
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