CN104899398A - Signal delay compensation method and system in hardware-in-loop simulation system - Google Patents

Abstract

The invention provides a signal delay compensation method and system in a hardware-in-loop simulation system. The method comprises the steps of: establishing a hardware simulation circuit, outputting detection quantity, calculating the whole delay time of the hardware, calculating required delay compensation angle, compiling a delay compensation module according to the required delay compensation angle, performing delay compensation conversion on the detection quantity by the delay compensation module to obtain the delay compensated detection quantity, and performing a hardware-in-loop detection test according to the delay compensated detection quantity. During the whole process, the required delay compensation angle is calculated by calculating the whole delay time of the hardware, and delay compensation module is compiled according to the required delay compensation angle, so that the precision of the final delay compensation conversion is ensured, namely, the signal delay high precision compensation in the hardware-in-loop simulation system ca be achieved, in addition, the whole scheme does not need additional equipment with high costs such as high speed A/D conversion chip and microprocessor, and is low in implementation costs.

Description

Signal lag compensation method and system in hardware-in-loop simulation system

Technical field

The present invention relates to Simulating technique in Electric Power System field, particularly relate to signal lag compensation method and system in hardware-in-loop simulation system.

Background technology

The real-time simulation of numeral physical mixed is also called hardware-in-loop simulation, and the physics of reality is placed in by test system the virtual electric power system set up by real time data display and carries out closed-loop simulation by this method.

In the middle of the process of emulation, latency issue is inevitable problem, and system, from the reception being issued to feedback signal of signal, must have a mistiming to be a key factor of the unstable and system accuracy of influential system therebetween, hardware based latency issue.

Traditional removing method is selected high-speed a/d conversion chip and microprocessor and is had the mutual inductor of phase compensation function, reduces the time delay that the link such as systematic sampling and data calculating causes, but, substantially increase emulation cost.

Summary of the invention

Based on this, be necessary low cost to realize the problem of high precision compensation of delay for signal lag compensation method in current hardware-in-loop simulation system, a kind of realize with low cost and signal lag compensation method and system in the hardware-in-loop simulation system that compensation precision is high are provided.

Signal lag compensation method in a kind of hardware-in-loop simulation system, comprises step:

Build the simulation hardware circuit in hardware-in-loop simulation system, output detections amount, the overall delay time of computing hardware;

Required compensation of delay angle is calculated, according to delay compensation module in required compensation of delay angle compiling hardware-in-loop simulation system according to the overall delay time of hardware;

By delay compensation module, compensation of delay conversion is carried out to detection limit, obtain the detection limit after compensation of delay;

According to the detection limit after compensation of delay, carry out hardware in loop detection experiment.

Signal lag bucking-out system in a kind of hardware-in-loop simulation system, comprising:

Delay time computing module, for building the simulation hardware circuit in hardware-in-loop simulation system, output detections amount, the overall delay time of computing hardware;

Collector, for calculating required compensation of delay angle according to the overall delay time of hardware, according to delay compensation module in required compensation of delay angle compiling hardware-in-loop simulation system;

Conversion module, for by delay compensation module, carries out compensation of delay conversion to detection limit, obtains the detection limit after compensation of delay;

Tentative module, for according to the detection limit after compensation of delay, carries out hardware in loop detection experiment.

Signal lag compensation method and system in hardware-in-loop simulation system of the present invention, build simulation hardware circuit, output detections amount, the overall delay time of computing hardware, calculates required compensation of delay angle, according to required compensation of delay angle compiling delay compensation module, by delay compensation module, compensation of delay conversion is carried out to detection limit, obtain the detection limit after compensation of delay, according to the detection limit after compensation of delay, carry out hardware in loop detection experiment.In whole process, required compensation of delay angle is accurately calculated by the overall delay time of computing hardware, and according to required compensation of delay angle, delay compensation module is compiled, guarantee that final compensation of delay converts accurate, namely signal lag high-accuracy compensation in hardware-in-loop simulation system can be realized, in addition, the equipment that whole scheme does not need extra high-speed a/d conversion chip and microprocessor etc. with high costs, implementation cost is cheap.

Accompanying drawing explanation

Fig. 1 is the simulation hardware circuit diagram in hardware-in-loop simulation system;

Fig. 2 is the schematic flow sheet of signal lag compensation method first embodiment in hardware-in-loop simulation system of the present invention;

Fig. 3 is the schematic flow sheet of signal lag compensation method second embodiment in hardware-in-loop simulation system of the present invention;

Fig. 4 is the structural representation of signal lag bucking-out system first embodiment in hardware-in-loop simulation system of the present invention;

Fig. 5 is the structural representation of signal lag bucking-out system second embodiment in hardware-in-loop simulation system of the present invention.

Embodiment

As shown in Figure 1, Figure 2 and shown in Fig. 3, signal lag compensation method in a kind of hardware-in-loop simulation system, comprises step:

S100: build the simulation hardware circuit in hardware-in-loop simulation system, output detections amount, the overall delay time of computing hardware.

The emulation of numeral physical mixed is also called hardware in loop (hardware-in-the-loop, HIL) emulation, and the physics of reality is placed in by test system the virtual electric power system set up by real time data display and carries out closed-loop simulation by this method.HIL system is divided into signal type hardware-in-loop simulation and power connecting-type hardware-in-loop simulation.Compare other emulation technology, HIL emulation has a lot of advantages, it can carry out accurate, stable experimental study by real-time simulation device repeatedly to real electrical equipment, it is minimized in the emulation cost and risk under various extreme condition, the defect of the simulated electrical equipment of maximized detection, avoids the loss being difficult to bear.Fig. 1 is the simulation hardware circuit diagram in hardware-in-loop simulation system, and we can have a clear understanding of the simulation hardware circuit structure in hardware-in-loop simulation system according to Fig. 1, and build the simulation hardware circuit in hardware-in-loop simulation system based on this.Detection limit can be three-phase current or three-phase voltage, and the overall delay time of hardware comprises the time delay that sampling, data communication and calculating link produce.

S200: calculate required compensation of delay angle according to the overall delay time of hardware, according to delay compensation module in required compensation of delay angle compiling hardware-in-loop simulation system.

Required compensation of delay angle specifically can utilize formula △ θ=n ω △ T to calculate required compensation of delay angle, and in formula, n is overtone order, and ω is first-harmonic angular frequency, and △ T is the overall delay time of hardware.Delay compensation module is built-in with in hardware-in-loop simulation system, delay compensation module is used for carrying out compensation of delay to the signal of transmission, compiling delay compensation module can be understood as and is written in delay compensation module by special compensation of delay algorithm, follow-up compensation of delay calculates and calculates according to this special compensation of delay algorithm, obtains rational compensation of delay.

S300: by delay compensation module, carries out compensation of delay conversion to detection limit, obtains the detection limit after compensation of delay.

Just as described above, delay compensation module, after compiling, stores special compensation of delay algorithm, utilizes this algorithm to carry out compensation of delay conversion to detection limit, obtains the detection limit after compensation of delay.

Wherein in an embodiment, described detection limit is three-phase current, and step S300 specifically comprises:

S320: by delay compensation module, obtains the special transformation matrix adding required compensation of delay angle.

Delay compensation module after compiled, upgrades and has special compensation of delay algorithm, can obtain the special transformation matrix adding required compensation of delay angle based on this algorithm.

S340; According to the special transformation matrix adding required compensation of delay angle, three-phase static coordinate system/two-phase rotating coordinate system conversion is carried out to detection limit, according to instantaneous reactive power theory, calculates the DC component of harmonic wave active current and reactive current.

S360: by the special transformation matrix at required for the write of the DC component of harmonic wave active current and reactive current compensation of delay angle, carries out two-phase rotating coordinate system/three-phase static coordinate system conversion, obtains the detection limit after compensation of delay.

Utilize and add required compensation of delay angle when two-phase rotates to three phase static coordinate transform, can be good at compensating the amount of delay in hardware in loop hybrid real-time simulation.

Wherein in an instantiation, detection limit is three-phase current i _a, i _b, i _cabove-mentioned processing procedure is specifically as follows:

Detection electric current is passed through delay compensation module, first, the instantaneous value e of a phase voltage after n frequency multiplication by phase-locked loop pll and just, cosine circuit for generating obtains and this instantaneous value e synchronous sinusoidal signal sin nwt and corresponding cosine signal cos nwt, thus obtains transformation matrix C _n:

$C_n=\left[\begin{array}{cc}-\sin nwt& \cos nwt\\ \cos nwt& \sin nwt\end{array}\right];$

Three-phase current i _a, i _b, i _cthrough known 3S/2R (three-phase static coordinate system/two-phase rotating coordinate system) transformation matrix C ₃₂, be transformed into the current i of static α, β two phase coordinate system _α, i _β:

$\left[\begin{array}{c}{i}_{\mathrm{\α}}\\ i_{\mathrm{\β}}\end{array}\right]=C_{32}\left[\begin{array}{c}{i}_a\\ i_b\\ i_c\end{array}\right]$

$C_{32}=\sqrt{\frac{2}{3}}\left[\begin{array}{ccc}1& \frac{1}{2}& \frac{1}{2}\\ 0& \frac{\sqrt{3}}{2}& \frac{\sqrt{3}}{2}\end{array}\right];$

Biphase current i _α, i _βthrough transformation matrix C _nobtain active current and the reactive current component of this nth harmonic electric current under two phase coordinate systems:

$\left[\begin{array}{c}{i}_{pn}\\ i_{qn}\end{array}\right]=C_n\left[\begin{array}{c}{i}_{\mathrm{\α}}\\ i_{\mathrm{\β}}\end{array}\right]=C_n.C_{32}.\left[\begin{array}{c}{i}_a\\ i_b\\ i_c\end{array}\right];$

This i _pn, i _qnthe DC component of nth harmonic active current and reactive current is drawn again through low-pass filtering

${\stackrel{\‾}{i}}_{\left(k\right)\mathrm{pn}}=\frac{\mathrm{\Δ}s}{T+\mathrm{\Δ}s}{i}_{\left(k\right)pn}+\frac{T}{T+\mathrm{\Δ}s}{\stackrel{\‾}{i}}_{(k-1)\mathrm{pn}}$

${\stackrel{\‾}{i}}_{\left(k\right)\mathrm{qn}}=\frac{\mathrm{\Δ}s}{T+\mathrm{\Δ}s}{i}_{\left(k\right)\mathrm{qn}}+\frac{T}{T+\mathrm{\Δ}s}{\stackrel{\‾}{i}}_{(k-1)\mathrm{qn}};$

T is time constant filter, and △ s is the sampling time, and k is the moment;

Should through adding the special transformation Matrix C of offset angle △ θ _{△ θ}obtain two phase coordinate system i _{α n}, $i_{\mathrm{\β}n}:\left[\begin{array}{c}{i}_{\mathrm{\α}n}\\ i_{\mathrm{\β}n}\end{array}\right]=C_{\mathrm{\Δ}\mathrm{\θ}}\left[\begin{array}{c}\stackrel{\‾}{i_{pn}}\\ \stackrel{\‾}{i_{qn}}\end{array}\right]={\left[\begin{array}{cc}-\sin (nwt+\mathrm{\Δ}\mathrm{\θ})& \cos (nwt+\mathrm{\Δ}\mathrm{\θ})\\ \cos (nwt+\mathrm{\Δ}\mathrm{\θ})& \sin (nwt+\mathrm{\Δ}\mathrm{\θ})\end{array}\right]}^{-1}\·\left[\begin{array}{c}\stackrel{\‾}{i_{pn}}\\ \stackrel{\‾}{i_{qn}}\end{array}\right]$

Wherein △ θ=n ω △ T;

As required, i _{α n}, i _{β n}through known 2R/3S (two-phase rotating coordinate system/three-phase static coordinate system) transformation matrix C ₂₃finally obtain the n-th subharmonic current $\left[\begin{array}{c}{i}_{an}\\ i_{bn}\\ i_{cn}\end{array}\right]=C_{23}\left[\begin{array}{c}{i}_{\mathrm{\α}n}\\ i_{\mathrm{\β}n}\end{array}\right].$ Wherein C ₂₃c ₃₂inverse matrix.After transformed, superposition after the combination of each periodic signal is exported the three-phase current after compensating.

S400: according to the detection limit after compensation of delay, carries out hardware in loop detection experiment.

Detection limit after compensation of delay is transferred to master control set or power amplification device, carries out controller hardware at ring test or power hardware at ring test.

Signal lag compensation method in hardware-in-loop simulation system of the present invention, build simulation hardware circuit, output detections amount, the overall delay time of computing hardware, calculates required compensation of delay angle, according to required compensation of delay angle compiling delay compensation module, by delay compensation module, compensation of delay conversion is carried out to detection limit, obtain the detection limit after compensation of delay, according to the detection limit after compensation of delay, carry out hardware in loop detection experiment.In whole process, required compensation of delay angle is accurately calculated by the overall delay time of computing hardware, and according to required compensation of delay angle, delay compensation module is compiled, guarantee that final compensation of delay converts accurate, namely signal lag high-accuracy compensation in hardware-in-loop simulation system can be realized, in addition, the equipment that whole scheme does not need extra high-speed a/d conversion chip and microprocessor etc. with high costs, implementation cost is cheap.

As shown in Figure 3, wherein in an embodiment, before step S400 also in steps

S500: export after D/A conversion is carried out to the detection limit after compensation of delay.

Export after analog to digital conversion is carried out to the detection limit after compensation of delay.

Wherein in an embodiment, describedly calculate required compensation of delay angle according to the overall delay time of hardware and be specially:

According to the overall delay time of hardware, utilize formula △ θ=n ω △ T to calculate required compensation of delay angle, in formula, n is overtone order, and ω is first-harmonic angular frequency, and △ T is the overall delay time of hardware.

Wherein in an embodiment, described detection limit is three-phase voltage or three-phase current.

As shown in Figure 4, signal lag bucking-out system in a kind of hardware-in-loop simulation system, comprising:

Delay time computing module 100, for building the simulation hardware circuit in hardware-in-loop simulation system, output detections amount, the overall delay time of computing hardware;

Collector 200, for calculating required compensation of delay angle according to the overall delay time of hardware, according to delay compensation module in required compensation of delay angle compiling hardware-in-loop simulation system;

Conversion module 300, for by delay compensation module, carries out compensation of delay conversion to detection limit, obtains the detection limit after compensation of delay;

Tentative module 400, for according to the detection limit after compensation of delay, carries out hardware in loop detection experiment.

Signal lag bucking-out system in hardware-in-loop simulation system of the present invention, delay time computing module 100 builds simulation hardware circuit, output detections amount, the overall delay time of computing hardware, collector 200 calculates required compensation of delay angle, according to required compensation of delay angle compiling delay compensation module, conversion module 300 passes through delay compensation module, compensation of delay conversion is carried out to detection limit, obtain the detection limit after compensation of delay, tentative module 400, according to the detection limit after compensation of delay, carries out hardware in loop detection experiment.In whole process, required compensation of delay angle is accurately calculated by the overall delay time of computing hardware, and according to required compensation of delay angle, delay compensation module is compiled, guarantee that final compensation of delay converts accurate, namely signal lag high-accuracy compensation in hardware-in-loop simulation system can be realized, in addition, the equipment that whole system does not need extra high-speed a/d conversion chip and microprocessor etc. with high costs, implementation cost is cheap.

As shown in Figure 5, wherein in an embodiment, described detection limit is three-phase current, and described conversion module 300 specifically comprises:

Matrixing unit 320, for by delay compensation module, obtains the special transformation matrix adding required compensation of delay angle;

Linear transformation unit 340, the special transformation matrix at required compensation of delay angle is added for basis, three-phase static coordinate system/two-phase rotating coordinate system conversion is carried out to detection limit, according to instantaneous reactive power theory, calculates the DC component of harmonic wave active current and reactive current;

Quadratic transformation unit 360, for the special transformation matrix by required for the write of the DC component of harmonic wave active current and reactive current compensation of delay angle, carries out two-phase rotating coordinate system/three-phase static coordinate system conversion, obtains the detection limit after compensation of delay.

Wherein in an embodiment, in described hardware-in-loop simulation system, signal lag bucking-out system also comprises:

D/A converter module 500, exports after the detection limit after compensation of delay being carried out to D/A conversion.

Wherein in an embodiment, described collector 200 calculates required compensation of delay angle according to the overall delay time of hardware and is specially:

According to the overall delay time of hardware, utilize formula △ θ=n ω △ T to calculate required compensation of delay angle, in formula, n is overtone order, and ω is first-harmonic angular frequency, and △ T is the overall delay time of hardware.

Wherein in an embodiment, described detection limit is three-phase voltage or three-phase current.

In order to further explain technical scheme and the beneficial effect thereof of signal lag compensation method and system in hardware-in-loop simulation system of the present invention in detail, below talent explain with an instantiation.

Step 1: build Power Electronic Circuit in real-time simulation software, by the magnitude of current ia that Power Electronic Circuit exports, ib, ic export, and computing hardware is at delay time summation △ T such as loop systems communication, sampling and calculating.

Step 2: in the middle of the real-time simulation software of hardware in loop system, draws the offset angle △ θ of needs according to delay time, △ θ=n ω △ T, n is overtone order, and ω is first-harmonic angular frequency, and △ T is delay time.Delay compensation module is compiled in the middle of real-time simulation software.

Step 3: in the middle of the real-time simulation software of hardware in loop system, detection electric current in the middle of step 1 is passed through delay compensation module, first, the instantaneous value e of a phase voltage after n frequency multiplication by phase-locked loop pll and just, cosine circuit for generating obtains and this instantaneous value e synchronous sinusoidal signal sin nwt and corresponding cosine signal cos nwt, thus obtains transformation matrix C _n:

$C_n=\left[\begin{array}{cc}-\sin nwt& \cos nwt\\ \cos nwt& \sin nwt\end{array}\right];$

Three-phase current ia, ib, ic are through known 3S/2R (three-phase static coordinate system/two-phase rotating coordinate system) transformation matrix C ₃₂, be transformed into the current i of static α, β two phase coordinate system _α, i _β:

$\left[\begin{array}{c}{i}_{\mathrm{\α}}\\ i_{\mathrm{\β}}\end{array}\right]=C_{32}\left[\begin{array}{c}{i}_a\\ i_b\\ i_c\end{array}\right]$

$C_{32}=\sqrt{\frac{2}{3}}\left[\begin{array}{ccc}1& \frac{1}{2}& \frac{1}{2}\\ 0& \frac{\sqrt{3}}{2}& \frac{\sqrt{3}}{2}\end{array}\right];$

Biphase current i _α, i _βthrough transformation matrix C _nobtain active current and the reactive current component of this nth harmonic electric current under two phase coordinate systems:

$\left[\begin{array}{c}{i}_{pn}\\ i_{qn}\end{array}\right]=C_n\left[\begin{array}{c}{i}_{\mathrm{\α}}\\ i_{\mathrm{\β}}\end{array}\right]=C_n.C_{32}.\left[\begin{array}{c}{i}_a\\ i_b\\ i_c\end{array}\right];$

This i _pn, i _qnthe DC component of nth harmonic active current and reactive current is drawn again through low-pass filtering

${\stackrel{\‾}{i}}_{\left(k\right)pn}=\frac{\mathrm{\Δ}s}{T+\mathrm{\Δ}s}{i}_{\left(k\right)\mathrm{pn}}+\frac{T}{T+\mathrm{\Δ}s}{\stackrel{\‾}{i}}_{(k-1)pn}$

${\stackrel{\‾}{i}}_{\left(k\right)qn}=\frac{\mathrm{\Δ}s}{T+\mathrm{\Δ}s}{i}_{\left(k\right)qn}+\frac{T}{T+\mathrm{\Δ}s}{\stackrel{\‾}{i}}_{(k-1)qn};$

T is time constant filter, and △ s is the sampling time, and k is the moment;

Should through adding the special transformation Matrix C of offset angle △ θ _{△ θ}obtain two phase coordinate system i _{α n}, $i_{\mathrm{\β}n}:\left[\begin{array}{c}{i}_{\mathrm{\α}n}\\ i_{\mathrm{\β}n}\end{array}\right]=C_{\mathrm{\Δ}\mathrm{\θ}}\left[\begin{array}{c}\stackrel{\‾}{i_{pn}}\\ \stackrel{\‾}{i_{qn}}\end{array}\right]={\left[\begin{array}{cc}-\sin (nwt+\mathrm{\Δ}\mathrm{\θ})& \cos (nwt+\mathrm{\Δ}\mathrm{\θ})\\ \cos (nwt+\mathrm{\Δ}\mathrm{\θ})& \sin (nwt+\mathrm{\Δ}\mathrm{\θ})\end{array}\right]}^{-1}\·\left[\begin{array}{c}\stackrel{\‾}{i_{pn}}\\ \stackrel{\‾}{i_{qn}}\end{array}\right],$ Wherein △ θ=n ω △ T;

As required, i _{α n}, i _{β n}through known 2R/3S (two-phase rotating coordinate system/three-phase static coordinate system) transformation matrix C ₂₃finally obtain the n-th subharmonic current $\left[\begin{array}{c}{i}_{an}\\ i_{bn}\\ i_{cn}\end{array}\right]=C_{23}\left[\begin{array}{c}{i}_{\mathrm{\α}n}\\ i_{\mathrm{\β}n}\end{array}\right],$ Wherein C ₂₃c ₃₂inverse matrix transformed after, by each periodic signal combination after superposition export compensate after three-phase current;

Step 4: in the middle of the real-time simulation software of hardware in loop system, is exported the magnitude of current in the middle of step 3 after compensation of delay link by D/A port.

Step 5: in the middle of the closed-loop system of hardware in loop, by exporting the magnitude of current after compensation of delay in the middle of step 4, being transferred to master control set, being provided sample rate current to controller hardware in loop systems; Or be transferred to power amplification device, as command signal, control power amplification device amplification instruction signal, be applied to tested actual device, carry out power hardware at ring test.

In transformation matrices, offset angle △ θ is added when utilizing the two-phase based on instantaneous reactive power theory to rotate to the conversion of two-phase static coordinate, can be good at compensating the amount of delay in the middle of hardware in loop system, thus improve stability and the precision of hardware-in-loop simulation system.

The above embodiment only have expressed several embodiment of the present invention, and it describes comparatively concrete and detailed, but can not therefore be construed as limiting the scope of the patent.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.

Claims (10)

1. a signal lag compensation method in hardware-in-loop simulation system, is characterized in that, comprise step:

Build the simulation hardware circuit in hardware-in-loop simulation system, output detections amount, the overall delay time of computing hardware;

Required compensation of delay angle is calculated, according to delay compensation module in required compensation of delay angle compiling hardware-in-loop simulation system according to the overall delay time of hardware;

By delay compensation module, compensation of delay conversion is carried out to detection limit, obtain the detection limit after compensation of delay;

According to the detection limit after compensation of delay, carry out hardware in loop detection experiment.

2. signal lag compensation method in hardware-in-loop simulation system according to claim 1, it is characterized in that, described detection limit is three-phase current, described in pass through delay compensation module, carry out compensation of delay conversion to detection limit, the detection limit obtained after compensation of delay specifically comprises step:

By delay compensation module, obtain the special transformation matrix adding required compensation of delay angle;

According to the special transformation matrix adding required compensation of delay angle, three-phase static coordinate system/two-phase rotating coordinate system conversion is carried out to detection limit, according to instantaneous reactive power theory, calculates the DC component of harmonic wave active current and reactive current;

By the special transformation matrix at required for the write of the DC component of harmonic wave active current and reactive current compensation of delay angle, carry out two-phase rotating coordinate system/three-phase static coordinate system conversion, obtain the detection limit after compensation of delay.

3. signal lag compensation method in hardware-in-loop simulation system according to claim 1 and 2, is characterized in that, described according to the detection limit after described compensation of delay, before carrying out hardware in loop detection experiment also in steps:

Export after D/A conversion is carried out to the detection limit after compensation of delay.

4. signal lag compensation method in hardware-in-loop simulation system according to claim 1 and 2, is characterized in that, describedly calculates required compensation of delay angle according to the overall delay time of hardware and is specially:

According to the overall delay time of hardware, utilize formula Δ θ=n ω Δ T to calculate required compensation of delay angle, in formula, n is overtone order, and ω is first-harmonic angular frequency, and Δ T is the overall delay time of hardware.

5. signal lag compensation method in hardware-in-loop simulation system according to claim 1, is characterized in that, described detection limit is three-phase voltage or three-phase current.

6. a signal lag bucking-out system in hardware-in-loop simulation system, is characterized in that, comprising:

Delay time computing module, for building the simulation hardware circuit in hardware-in-loop simulation system, output detections amount, the overall delay time of computing hardware;

Collector, for calculating required compensation of delay angle according to the overall delay time of hardware, according to delay compensation module in required compensation of delay angle compiling hardware-in-loop simulation system;

Conversion module, for by delay compensation module, carries out compensation of delay conversion to detection limit, obtains the detection limit after compensation of delay;

Tentative module, for according to the detection limit after compensation of delay, carries out hardware in loop detection experiment.

7. signal lag bucking-out system in hardware-in-loop simulation system according to claim 6, is characterized in that, described detection limit is three-phase current, and described conversion module specifically comprises:

Matrixing unit, for by delay compensation module, obtains the special transformation matrix adding required compensation of delay angle;

Linear transformation unit, for according to the special transformation matrix adding required compensation of delay angle, carries out three-phase static coordinate system/two-phase rotating coordinate system conversion to detection limit, according to instantaneous reactive power theory, calculates the DC component of harmonic wave active current and reactive current;

Quadratic transformation unit, for the special transformation matrix by required for the write of the DC component of harmonic wave active current and reactive current compensation of delay angle, carries out two-phase rotating coordinate system/three-phase static coordinate system conversion, obtains the detection limit after compensation of delay.

8. signal lag bucking-out system in the hardware-in-loop simulation system according to claim 6 or 7, is characterized in that, also comprise:

D/A converter module, exports after the detection limit after compensation of delay being carried out to D/A conversion.

9. signal lag bucking-out system in the hardware-in-loop simulation system according to claim 6 or 7, is characterized in that, described collector calculates required compensation of delay angle according to the overall delay time of hardware and is specially:

According to the overall delay time of hardware, utilize formula Δ θ=n ω Δ T to calculate required compensation of delay angle, in formula, n is overtone order, and ω is first-harmonic angular frequency, and Δ T is the overall delay time of hardware.

10. signal lag bucking-out system in hardware-in-loop simulation system according to claim 6, is characterized in that, described detection limit is three-phase voltage or three-phase current.