CN104883188A - Fully digitalized scintillation type analog-to-digital converter - Google Patents
Fully digitalized scintillation type analog-to-digital converter Download PDFInfo
- Publication number
- CN104883188A CN104883188A CN201510220289.2A CN201510220289A CN104883188A CN 104883188 A CN104883188 A CN 104883188A CN 201510220289 A CN201510220289 A CN 201510220289A CN 104883188 A CN104883188 A CN 104883188A
- Authority
- CN
- China
- Prior art keywords
- time delay
- gate
- input
- differential
- delay chain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
The invention belongs to the technical field of integrated circuits, and concretely provides a fully digitalized scintillation type analog-to-digital converter. The converter comprises differential signal sampling maintenance arrays formed by two three-state gates connected in parallel and decoupling capacitors, (2<N>-1) differential delay line pairs formed by NAND gate/NOT gates and decoupling capacitors and having built-in reference voltages, and a latch array. Differential signals pass across the two identical sampling maintenance arrays, each DDLP corresponds to a pair of differential reference voltages, the differential signals control the DDLPs to generate different delays during a maintenance period, the delay of delay lines is determined by the plurality of NAND gate/NOT gates, and fine tuning is achieved through the decoupling capacitors. Then, a comparison step is performed by the latch array, the delays of two output rising edges of the DDLPs are obtained, and digital comparison outputs of thermometer codes are obtained. The fully digitalized scintillation type analog-to-digital converter has a good analog-to-digital conversion property at high speed, areas and power consumption can be reduced, and also the design complexity is minimized.
Description
Technical field
The invention belongs to technical field of integrated circuits, be specifically related to a kind of Flash ADC of full digital starting.
Background technology
Along with the continuous progress of technique, due to the impact of short-channel effect, analog circuit can not realize effectively scaled, and power consumption is also larger, it relies on the experience of designer strongly simultaneously, lack suitable high-efficient automatic design tool, and traditional analog to digital converter, no matter be successively comparative structure, or flicker type structure, pipeline organization, has quite most simulation part, it reduces the design efficiency of analog to digital converter.Digital circuit then can make up the deficiency of above-mentioned analog circuit, makes full use of the advantage that technique advanced technologies is brought.
As shown in Figure 3, differential input signal compares respectively by four input difference comparators and the differential reference voltage through electric resistance partial pressure the structure of conventional Flash pattern number converter, obtains thermometer-code comparative result.Here use more resistance, add area, use a large amount of analog comparator simultaneously, while increasing area, also spend a large amount of power consumption.
For solving the waste of analog to digital converter in power consumption and area that traditional analog realizes, and improve design automation degree and the efficiency of analog to digital converter, the present invention proposes a kind of digital Flash ADC building realization, each module in conventional Flash pattern number converter is all replaced with the unit in digital standard cell library, completes the full digital starting of analog to digital converter.Sampling hold circuit uses three-state gate array and decoupling capacitance array (201) to complete, comparator part then adopts the DDLP array (202) be made up of NAND gate/not gate/decoupling capacitance, and each DDLP compares the thermometer-code Output rusults producing correspondence through latch.
Summary of the invention
The Flash ADC of the full digital starting that the object of the present invention is to provide a kind of area little, low in energy consumption.
The Flash ADC of the full digital starting that the present invention proposes, its structure comprises: the differential signal be made up of two groups of triple gates in parallel and decoupling capacitance is sampled and kept array (201), and what be made up of NAND gate/not gate and decoupling capacitance has (2 of use built-in reference voltage
n-1) individual differential delay chain is to (Differential Delay Line Pair, hereinafter referred to as DDLP) array (202), and latch arrays; Differential signal keeps array through two identical samplings, due to corresponding a pair differential reference voltage of each DDLP, differential signal controls corresponding DDLP and produces different delayed time during keeping, and the time delay of time delay chain is determined by several NAND gate and not gate, and realize fine setting through decoupling capacitance; Compare through latch again, obtain the time delay size of two output rising edges of DDLP, thus the numeral obtaining thermometer-code compares output.
In the present invention, differential signal sampling hold circuit (201) mainly adopts triple gate and decoupling capacitance to realize, as shown in Figure 1, primarily of 12 metal-oxide-semiconductor M
1~ M
12circuit connects to form; Wherein, NMOS tube M
1and M
2composition inverter, obtains inputting the anti-phase of enable signal OE; NMOS tube M
3, M
4, M
5, M
6composition NOR gate, this NOR gate be input as the anti-phase of OE and input signal I, the output of NOR gate is as PMOS M
12grid control signal; By NMOS tube M
7, M
8, M
9, M
10the NAND gate of composition, enable signal OE and input signal I is input to by NMOS tube M
7, M
8, M
9, M
10in the NAND gate of composition, the output of NAND gate is as PMOS M
11grid control signal; PMOS M
11and M
12common drain as the output of whole triple gate; Input I place connects high level, and Enable Pin OE place connects clock, and inputs signal to be sampled by output PMOS, the sampling of property performance period under the control of OE; The effect that whole triple gate realizes is, when OE is low level, exports floating; When OE is high level, exports and follow input I.Here triple gate be used as the connection of sample circuit and operation principle as follows, input I meets high voltage VDD, is red line in such M signal line Mid(figure) be low level always, 3 NMOS tube M
4, M
7, M
12whole shutoff, NMOS tube M
10all the time conducting; The Enable Pin OE incoming clock of triple gate, clock is added in PMOS M after oppositely
11grid, input signal vin to be sampled by PMOS M
11source class periodically sampled and kept under the control of OE.According to the requirement to sampling hold circuit driving force, adopt several Fig. 1 structures to form sampling array, connect some decoupling capacitances after sampling array and make holding capacitor.
In the present invention, differential signal is first converted to corresponding delayed data by DDLP array (202) and compares.The design of DDLP is, for the differential reference voltage vrefp that a pair is specified, vrefn, design two time delay chains: time delay chain A and time delay chain B, make input vip, vin be respectively corresponding reference voltage vrefp, during vrefn, the output rising edge of time delay chain arrives simultaneously.Like this, the input being greater than vrefp(now time delay chain B when the input of time delay chain A is less than vrefn), the time delay of time delay chain A is just less than time delay chain B, the rising edge exported comparatively time delay chain B more early arrives, two output signals are latched by respective latch, and the comparative result obtained is " 1 ", and vice versa.All reference voltages are designed all adopting this thinking, that is, to the Flash ADC of N position, needs design (2
n-1) individual DDLP.But owing to being difference realization, maximum (2
n-1-1) individual reference voltage is pair with minimum (2
n-1-1) each reference voltage is to being symmetrical, like this, as long as emulation draws maximum 2
n-1individual reference voltage to the DDLP of correspondence, remaining (2
n-1-1) individual DDLP, only need exchange the input signal of correspondence.
In the present invention, the time delay of time delay chain is made up of two parts, as shown in Figure 2.First each time delay chain is in series by several basic delay units, to determine the scope of its time delay.Basic delay unit is connected to form successively by NAND gate and not gate, as shown in Fig. 2 top, and the NMOS tube N of ground connection in NAND gate
2with one of them PMOS P
2grid all meet input control signal In, and all the other NMOS tube N
1with PMOS P
1grid meets clock Clock.Input control signal In remains on larger level, to make PMOS P
2turn off and NMOS tube N always
2conducting always, such Clock to export time delay by NMOS tube N
2grid voltage, namely In control.If In increases, cross NMOS tube N
2electric current also increase, the upset of output Clock is also rapider.Vice versa.Not gate after NAND gate exports and input homophase to ensure.During the series connection of several such elementary cells, each elementary cell shares input control signal In, and inputs the output that Clock is previous elementary cell.The superposition of each like this unit time delay is the time delay of whole time delay chain.Connect decoupling capacitance after time delay chain, can realize finely tuning time delay, to make DDLP accurately meet design requirement, comparison and the latch of certain precision can be realized.
The present invention uses triple gate unit and decoupling capacitance to build sampling hold circuit; Differential input signal to obtaining different time delays, then compares two time delay sizes through latch respectively by the differential delay chain of several accurate simulations, completes and right the comparing of corresponding differential reference voltage, obtains corresponding thermometer-code.The time delay of time delay chain is determined primarily of NAND gate/non-door chain, and is finely tuned by decoupling capacitance, to meet the requirement being preset in the differential reference voltage of differential delay chain centering.For the Flash ADC of N position, according to often pair of differential reference voltage, emulation obtains corresponding differential delay chain pair, so differential delay chain is (2 to number
n-1).This digital N position Flash ADC built is without the need to input reference voltage, and its reference voltage is built in (2
n-1) individual differential delay chain centering, can realize good analog-to-digital conversion performance at the higher speeds, saves area, power consumption, also greatly reduces design complexities simultaneously.
Accompanying drawing explanation
Fig. 1 is the connected mode of the triple gate realizing sampling hold circuit.
Fig. 2 is the implementation of DDLP.
Fig. 3 is the implementation of conventional Flash pattern number converter.
Fig. 4 is general structure of the present invention diagram.
Embodiment
Below the Flash ADC of a kind of full digital starting proposed in the present invention is described further.
The Flash ADC of the full digital starting that the present invention proposes, its feature has three, be respectively: the sampling hold circuit (201) be made up of triple gate/decoupling capacitance array, the comparator configuration (202) inputted without reference voltage be made up of DDLP array, by NAND gate/not gate coarse adjustment time delay, the time delay chain implementation (Fig. 2) of decoupling capacitance fine setting time delay.
The power consumption caused for solution traditional analog or modulus mixed analog to digital converter and the waste of area, and improve the Automation Design efficiency, the present invention proposes a kind of Flash ADC of full digital starting.The Flash ADC of this full digital starting, compared with conventional Flash pattern number converter, is characterized in that all circuit modules all use the digital units in standard cell lib to realize.First, for the sampling hold circuit that traditional analog realizes, the substitute is triple gate here.
Fig. 1 is the tri-state gate circuit in standard cell lib.M
1and M
2composition inverter, obtains inputting the anti-phase of enable signal OE.M
3, M
4, M
5, M
6composition NOR gate, this NOR gate be input as the anti-phase of OE and input signal I.The output of NOR gate is as M
12grid control signal.OE and input signal I is input to by M simultaneously
7, M
8, M
9, M
10in the NAND gate of composition, the output of NAND gate is as M
11grid control signal.M
11and M
12common drain as the output of whole triple gate.The effect that whole triple gate realizes is, when OE is low level, exports floating; When OE is high level, exports and follow input I.Here triple gate be used as the connection on sampled point road and operation principle as follows, input I meets high voltage VDD, is red line in such M signal line Mid(figure) be low level always, 3 NMOS tube M
4, M
7, M
12whole shutoff, NMOS tube M
10all the time conducting; The Enable Pin OE incoming clock of triple gate, clock is added in PMOS M after oppositely
11grid, input signal to be sampled by PMOS M
11periodically sampled and kept under the control of OE.According to the requirement to sampling hold circuit driving force, need to adopt several Fig. 1 structures to form sampling array, connect some decoupling capacitances after sampling array and make holding capacitor.Secondly, comparator here adopts several DDLP to realize.The corresponding differential reference voltage pair of each DDLP, comprise two time delay chains, the condition of the design demand fulfillment of two time delay chains is, when input signal is respectively corresponding reference voltage pair, the output rising edge of two time delay chains arrives simultaneously.Like this, subsequent conditioning circuit only need compare the comparative result that time delay that DDLP two exports successively can obtain input differential signal and corresponding reference voltage indirectly, obtains corresponding thermometer-code.DDLP time delay chain structure is as Fig. 2.The determination of time delay chain time delay adopts coarse adjustment+fine setting two steps, and the basic delay unit that the former is made up of several NAND gate/not gates forms, and the latter is completed by decoupling capacitance.The connection that basic delay unit is middle NAND gate as shown in Fig. 2 top, the NMOS tube N of ground connection
2with one of them PMOS P
2grid all meet input control signal In, and remaining tubing N
1and P
1grid meets clock Clock.Input control signal In remains on larger level, to make P
2turn off and N always
2conducting always, such Clock to export time delay by N
2grid voltage, namely In control.If In increases, cross N
2electric current also increase, the upset of output Clock is also rapider.Vice versa.Connecing not gate after NAND gate is export and input homophase to ensure.During the series connection of several such elementary cells, each elementary cell shares input control signal In, and inputs the output that Clock is previous elementary cell.The superposition of each like this unit time delay realizes the coarse delay of whole time delay chain.The reference voltage of this DDLP comparative structure is preset and is built in two time delay chains, without the need to outside input reference voltage.
What the DDLP time delay chain that the present invention adopts adopted is two input nand gates in java standard library, and the corresponding module in multi input NAND gate or high threshold voltage (HVT)/low threshold voltage (LVT) storehouse also can be adopted to realize time delay chain.
In the present invention, the control of input control signal to time delay chain time delay makes negative correlation, also can adopt positively related control thinking, as long as keep the monotonic of time delay and input signal.
The present invention uses the rising edge time delay of clock as comparing foundation, and trailing edge also can be adopted as time-delay conversion and the foundation compared.
Claims (3)
1. a Flash ADC for full digital starting, is characterized in that structure comprises:
The differential signal be made up of two groups of triple gates in parallel and decoupling capacitance is sampled and is kept array (201); What be made up of NAND gate/not gate and decoupling capacitance has (2 of use built-in reference voltage
n-1) individual differential delay chain is to (hereinafter referred to as DDLP) array (202); And latch arrays; Wherein:
Differential signal keeps array through two identical samplings, corresponding a pair differential reference voltage of each DDLP, differential signal controls corresponding DDLP and produces different delayed time during keeping, and the time delay of time delay chain is determined by several NAND gate and not gate, and realizes fine setting through decoupling capacitance; Compare through latch again, obtain the time delay size of two output rising edges of DDLP, thus the numeral obtaining thermometer-code compares output.
2. the Flash ADC of full digital starting according to claim 1, is characterized in that described differential signal sampling keeps array (201) mainly to adopt triple gate and decoupling capacitance to realize; Tri-state gate circuit is by 12 metal-oxide-semiconductor M
1~ M
12circuit connects to form; Wherein, metal-oxide-semiconductor M
1and M
2composition inverter, obtains inputting the anti-phase of enable signal OE; Metal-oxide-semiconductor M
3, M
4, M
5, M
6composition NOR gate, this NOR gate be input as the anti-phase of OE and input signal I, the output of NOR gate is as PMOS M
12grid control signal; By metal-oxide-semiconductor M
7, M
8, M
9, M
10composition NAND gate, enable signal OE and input signal I is input to by metal-oxide-semiconductor M
7, M
8, M
9, M
10in the NAND gate of composition, the output of NAND gate is as PMOS M
11grid control signal; Metal-oxide-semiconductor M
11and M
12common drain as the output of whole triple gate; Input I place connects high level, and Enable Pin OE place connects clock, and inputs signal to be sampled by output PMOS, the sampling of property performance period under the control of OE; Form sampling array by several tri-state gate circuits, connect some decoupling capacitances after sampling array and make holding capacitor.
3. the Flash ADC of full digital starting according to claim 1, it is characterized in that in described DDLP, for differential reference voltage vrefp, vrefn that a pair is specified, be designed with two time delay chains: time delay chain A and time delay chain B, input vip, vin is made to be respectively corresponding differential reference voltage vrefp, during vrefn, the output rising edge of time delay chain arrives simultaneously; Like this, when the input of time delay chain A is greater than vrefp, the time delay of time delay chain A is just less than time delay chain B, the rising edge comparatively time delay chain B more early arrival of output, and two output signals are latched by respective latch, and the comparative result obtained is " 1 ", and vice versa; All reference voltages are designed all adopting this thinking, that is, to the Flash ADC of N position, design (2
n-1) individual DDLP;
Wherein, the time delay of time delay chain is made up of two parts; First each time delay chain is in series by several basic delay units, to determine the scope of its time delay; Basic delay unit is connected to form successively by NAND gate and not gate, the NMOS tube N of ground connection in NAND gate
2with one of them PMOS P
2grid all meet input control signal In, and NMOS tube N
1with PMOS P
1grid meets clock Clock; Input control signal In remains on larger level, to make PMOS P
2turn off and NMOS tube N always
2conducting always, such Clock to export time delay by NMOS tube N
2grid voltage, namely In control; During several above-mentioned elementary cell series connection, each elementary cell shares input control signal In, and inputs the output that Clock is previous elementary cell; The superposition of each like this unit time delay is the time delay of whole time delay chain; Decoupling capacitance is connect, to realize finely tuning time delay after time delay chain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510220289.2A CN104883188B (en) | 2015-05-04 | 2015-05-04 | A kind of Flash ADC of full digital starting |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510220289.2A CN104883188B (en) | 2015-05-04 | 2015-05-04 | A kind of Flash ADC of full digital starting |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104883188A true CN104883188A (en) | 2015-09-02 |
| CN104883188B CN104883188B (en) | 2018-04-03 |
Family
ID=53950536
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510220289.2A Active CN104883188B (en) | 2015-05-04 | 2015-05-04 | A kind of Flash ADC of full digital starting |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104883188B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106027055A (en) * | 2016-05-16 | 2016-10-12 | 中国科学技术大学先进技术研究院 | Low-power-consumption two-step flicker type analog to digital converter |
| CN112542954A (en) * | 2020-12-16 | 2021-03-23 | 南京微盟电子有限公司 | Adaptive soft drive control circuit suitable for DCM |
| CN112564511A (en) * | 2020-12-16 | 2021-03-26 | 南京微盟电子有限公司 | Self-adaptive soft drive control circuit suitable for CCM |
| CN112737339A (en) * | 2020-12-16 | 2021-04-30 | 南京微盟电子有限公司 | Self-adaptive soft drive control circuit |
-
2015
- 2015-05-04 CN CN201510220289.2A patent/CN104883188B/en active Active
Non-Patent Citations (2)
| Title |
|---|
| CHEN HUABIN等: "An analog front end with a 12-bit 3.2-MS/s SAR ADC for a power line communication system", 《JOURNAL OF SEMICONDUCTORS》 * |
| 代国宪等: "一种具有2-bit/cycle结构的400-MS/s 8-bit逐次逼近型模数转换器设计", 《复旦学报（自然科学版）》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106027055A (en) * | 2016-05-16 | 2016-10-12 | 中国科学技术大学先进技术研究院 | Low-power-consumption two-step flicker type analog to digital converter |
| CN106027055B (en) * | 2016-05-16 | 2019-05-07 | 中国科学技术大学先进技术研究院 | A kind of low-power consumption two-step Flash ADC |
| CN112542954A (en) * | 2020-12-16 | 2021-03-23 | 南京微盟电子有限公司 | Adaptive soft drive control circuit suitable for DCM |
| CN112564511A (en) * | 2020-12-16 | 2021-03-26 | 南京微盟电子有限公司 | Self-adaptive soft drive control circuit suitable for CCM |
| CN112737339A (en) * | 2020-12-16 | 2021-04-30 | 南京微盟电子有限公司 | Self-adaptive soft drive control circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104883188B (en) | 2018-04-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104617957B (en) | Asynchronous gradual approaching A/D converter | |
| CN102843136B (en) | A kind of high-speed, high precision low-power consumption dynamic comparer offset correction method on a large scale | |
| CN104967451B (en) | Gradual approaching A/D converter | |
| CN102355266B (en) | A kind of successive approximation register analog-digital converter | |
| CN105306059B (en) | Successive approximation analog-to-digital converter device | |
| CN104883188B (en) | A kind of Flash ADC of full digital starting | |
| CN105322966B (en) | Improve the capacitors exchange and averaging method of the gradually-appoximant analog-digital converter linearity | |
| CN109687872B (en) | High-speed digital logic circuit for SAR _ ADC and sampling regulation method | |
| CN104811203A (en) | 2bits per circle high-speed successive approximation type analog-digital converter | |
| CN102769470B (en) | Current steering digital-analog converter with time domain error correction function | |
| CN104779954B (en) | Gradual approaching A/D converter and its less digit correction method based on error detection | |
| CN103560768B (en) | Duty ratio adjusting circuit | |
| CN104993831B (en) | Time-interleaved Pipeline SAR type adc circuits | |
| CN106067817A (en) | 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate gradual approaching A/D converter | |
| CN102832941B (en) | A kind of can the gradual approaching A/D converter of pre-detection comparator input range | |
| CN104485957A (en) | Pipeline analog-to-digital converter | |
| CN103427841B (en) | A kind of system and method improving row parallel single-slope ADC switching rate | |
| CN105070318A (en) | High-speed shift register applied to successive approximation type analog-to-digital converter | |
| CN106341133A (en) | Dual-channel time interleaved asynchronous assembly line flash analog-to-digital converter | |
| CN104038220A (en) | 16-bit pipelined analog-digital converter | |
| CN102386925A (en) | Flash type analog to digital converter based on digital front desk correction and analog to digital conversion method | |
| CN102075192A (en) | High speed digital-analog conversion circuit and operating method thereof | |
| CN106160745A (en) | Analog-digital commutator and initial method thereof | |
| CN105119601B (en) | A kind of multi-center selection circuit being suitable for A/D converter with high speed and high precision | |
| CN106160744A (en) | A kind of high speed dynamic latch comparator applied in low voltage environment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |