CN104882471A - Deep groove isolation structure and preparation method thereof - Google Patents
Deep groove isolation structure and preparation method thereof Download PDFInfo
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- CN104882471A CN104882471A CN201410072259.7A CN201410072259A CN104882471A CN 104882471 A CN104882471 A CN 104882471A CN 201410072259 A CN201410072259 A CN 201410072259A CN 104882471 A CN104882471 A CN 104882471A
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- isolation structure
- deep trench
- semiconductor substrate
- groove isolation
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Abstract
The invention relates to a deep groove isolation structure and a preparation method thereof. The preparation method comprises the steps of supplying a semiconductor substrate in which a shallow groove isolation structure is formed; patterning the shallow groove isolation structure and the semiconductor substrate, thereby forming the deep groove in the shallow groove isolation structure and the semiconductor substrate; forming an oxide protecting layer on the side wall of the deep groove; and filling the deep groove by a semiconductor material, thereby forming the deep groove isolation structure. The deep groove isolation which is prepared according to the method of the invention is surrounded by the shallow groove isolation structure, thereby improving isolation effect of the deep groove isolation structure, reducing a technological aligning requirement, reducing number of technological processes, and improving a technological realizability.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to a kind of deep trench isolation structure and preparation method thereof.
Background technology
Along with the integration (integration) of the inner member of integrated circuit constantly promotes, due to Distance Shortened between adjacent elements, thus the possibility of electronic jamming improves each other, for this reason, suitable isolation structure must be had, to avoid interfering with each other between element.
Generally speaking, particularly for high voltage device, in order to the isolated high voltage device being arranged in low concentration deep-well region or low concentration polysilicon layer, deep trench (deep trench) must be used to reach required isolated degree.
Usually the groove of the degree of depth more than 3 μm is called deep trench, deep groove structure obtains applying comparatively widely in semiconductor technology now, deep trench isolation structure is mainly used in high-power integrated BCD circuit or smart power technology (smart power technology), the isolation that wherein deep trench is good can make various high-low voltage device such as simulate, numeral, high pressure and EE etc. integrate, and can not cause EMI(electromagnetic interference) interference.Such as, deep trench can be used as isolation structure with the electronic device of isolated different operating voltage.
In prior art, the preparation method of deep trench isolation as is shown in figs. la to ld; first Semiconductor substrate is provided; active area 102 is formed in described Semiconductor substrate; to form various active device in described active area 102; then in described active area 102, etching forms deep trench 10; the sidewall of described deep trench forms oxide skin(coating) 103; described oxide skin(coating) is as protective layer; then in described deep trench 10, fill the polycrystalline silicon material 104 of doping; to form described deep trench isolation, finally in described active area, form fleet plough groove isolation structure.Further, the back side of described Semiconductor substrate is also formed with conductive material layer 101, and as preferably, described conductive material layer 101 is polysilicon material layer.
Although above-mentioned process is simple, but along with constantly reducing of device, the top isolating problem of described deep trench isolation becomes the problem needing to overcome, require at the top of deep trench isolation to be that the polycrystalline silicon material 104 of filling doping in active area 102 and described deep trench 10 is had good isolation, at the edge of STI, active area 102 district is also had to have the risk of electric leakage; Be subject to the restriction of STI pattern, inevitably have the region that narrow on active area 102 and fleet plough groove isolation structure top, the region as described in Fig. 1 d circle, causes active area 102 bad with the polycrystalline silicon material zone isolation of deep trench.
Therefore, need to be improved further, to eliminate the problems referred to above the preparation method of current described deep trench isolation structure.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
The present invention, in order to overcome current existing problems, provides a kind of preparation method of deep trench isolation structure, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with fleet plough groove isolation structure;
Fleet plough groove isolation structure described in patterning and described Semiconductor substrate, to form deep trench in described fleet plough groove isolation structure and described Semiconductor substrate;
The sidewall of described deep trench forms protective oxide film;
Semi-conducting material is selected to fill described deep trench, to form deep trench isolation structure.
As preferably, described deep trench is positioned at the middle part of described fleet plough groove isolation structure, with the top making described fleet plough groove isolation structure surround described deep trench.
As preferably, be formed with active area in described Semiconductor substrate, described deep trench isolation structure is positioned at described active area.
As preferably, select after semi-conducting material fills described deep trench, also comprise the step of planarization further.
As preferably, the polysilicon of doping selected by described semi-conducting material.
Present invention also offers a kind of deep trench isolation structure, comprising:
Semiconductor substrate;
Fleet plough groove isolation structure, is arranged in described Semiconductor substrate;
Deep trench isolation, be embedded in described fleet plough groove isolation structure and described Semiconductor substrate, described fleet plough groove isolation structure is around the top surrounding described deep trench isolation.
As preferably, be also formed with active area in described Semiconductor substrate, described fleet plough groove isolation structure and described deep trench isolation are arranged in described active area.
As preferably, described deep trench isolation comprises the protective oxide film be positioned on deep trench sidewall and the semi-conducting material being positioned at center.
The present invention isolates bad problem to solve deep trench isolation structural top in prior art, provide a kind of new preparation method, first in described Semiconductor substrate, fleet plough groove isolation structure is formed in the process, then in described isolation structure and described Semiconductor substrate, deep trench is formed, then form sidewall oxide layer and fill the polysilicon adulterated, to form described deep trench isolation structure, the deep trench isolation prepared by described method is surrounded by described fleet plough groove isolation structure, enhance the isolation effect of described deep trench isolation structure, technique reduces alignment request, decrease processing step, adding technique can degree of realization.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
Fig. 1 a-1d is the preparation process schematic diagram of deep trench isolation structure in prior art;
The preparation process schematic diagram of deep trench isolation structure described in Fig. 2 a-2d the present invention one specific embodiment;
The process chart of deep trench isolation structure described in Fig. 3 the present invention one specific embodiment.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed description is proposed, so that deep trench isolation structure of the present invention and preparation method to be described.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should give it is noted that term used here is only to describe specific embodiment, and be not intended to restricted root according to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative be also intended to comprise plural form.In addition, it is to be further understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.Should be understood that, providing these embodiments to be of the present inventionly disclose thorough and complete to make, and the design of these exemplary embodiments fully being conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerate the thickness in layer and region, and use the element that identical Reference numeral represents identical, thus will omit description of them.
The present invention, in order to solve problems of the prior art, provides a kind of method preparing deep trench isolation structure newly, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with fleet plough groove isolation structure;
Fleet plough groove isolation structure described in patterning and the described Semiconductor substrate of part, to form deep trench in described fleet plough groove isolation structure and the described Semiconductor substrate of part;
The sidewall of described deep trench forms protective oxide film;
Semi-conducting material is selected to fill described deep trench, and semi-conducting material described in planarization, to form deep trench isolation structure.
Embodiment 1
Below in conjunction with the preparation method of Fig. 2 a-2d to the structure of deep trench isolation described in the embodiment of the invention.
First, perform step 201, Semiconductor substrate is provided, in described Semiconductor substrate, forms fleet plough groove isolation structure 203.
Particularly, as shown in Figure 2 a, provide Semiconductor substrate, described Semiconductor substrate can be at least one in following mentioned material: stacked silicon (SSOI) etc. on silicon, silicon-on-insulator (SOI), insulator.Further, the back side of described Semiconductor substrate is also formed with conductive material layer 201, and as preferably, described conductive material layer 201 is polysilicon material layer.
Further, described Semiconductor substrate can be defined active area 202.This active area 202 can also include other active device, conveniently, do not indicate in shown figure.
In described active area 202, form fleet plough groove isolation structure 203, described shallow trench isolation can select method conventional in prior art from the formation method of 203, such as first, forms the first oxide skin(coating) and the first nitride layer on a semiconductor substrate successively.Then, perform dry etch process, etch to form groove to the first nitride layer, the first oxide skin(coating) and Semiconductor substrate successively.Particularly, the figuratum photoresist layer of tool can be formed on the first nitride layer, with this photoresist layer for mask carries out dry etching to the first nitride layer, with by design transfer to the first nitride layer, and with photoresist layer and the first nitride layer for mask etches the first oxide skin(coating) and Semiconductor substrate, to form groove.Certainly other method can also be adopted to form groove, because this technique is thought known in the art, be therefore no longer described further.
Then, in groove, fill shallow trench isolated material, to form fleet plough groove isolation structure.Particularly, can form shallow trench isolated material on the first nitride layer He in groove, described shallow trench isolated material can be silica, silicon oxynitride and/or other existing advanced low-k materials; Perform chemical mechanical milling tech and stop on the first nitride layer, to be formed, there is fleet plough groove isolation structure 203.
Perform step 202, the active area of fleet plough groove isolation structure 204 and described Semiconductor substrate described in patterning, to form deep trench 20 in described fleet plough groove isolation structure 204 and described Semiconductor substrate.
Particularly, as shown in Figure 2 b, described fleet plough groove isolation structure 204 and described Semiconductor substrate form the mask layer of patterning, in described mask layer, define the position of described deep trench and the critical size of opening.
In an embodiment, described fleet plough groove isolation structure 204 and described Semiconductor substrate form hard mask layer, its material is agraphitic carbon, chemical vapour deposition (CVD) can be adopted, plasma enhanced chemical vapor deposition forms amorphous carbon layer, hard mask layer is formed dielectric anti-reflective coating (DARC), its material is silicon oxynitride, the method that chemical gas can be adopted to deposit prepares dielectric anti-reflective coating, the object of deposition formation dielectric anti-reflective coating is the reflectivity in order to reduce silicon nitride layer, dielectric anti-reflective coating is formed the photoresist layer of patterning.
According to photoresist etching dielectrics antireflecting coating, the hard mask layer successively of patterning.Wherein, etching gas can adopt the gas based on chlorine or the gas based on hydrogen bromide or both mists.Adopt dry etch process, dry method etch technology includes but not limited to: reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.
Dry etching is carried out preferably by one or more RIE step.The range of flow of etching gas can be 0 ~ 200 cc/min (sccm), and reative cell internal pressure can be 5 ~ 20 millis millimetres of mercury (mTorr).Then, the photoresist layer of patterning, dielectric anti-reflective coating and hard mask layer is removed, to form opening.
Wherein, original position cineration technics (In-situ Asher) is used to remove the photoresist of patterning, dielectric anti-reflective coating and hard mask layer, the gas that cineration technics adopts is preferably oxygen, concrete, silicon semiconductor substrate is inserted in reactive ion etching device, by additional heater such as Halogen lamp LED, in the chamber of direct heating reactive ion etching device, the temperature range of heating is 60 DEG C ~ 250 DEG C, then, use oxygen-containing gas to supply in the chamber of heated reactive ion etching device, described oxygen-containing gas is O
2, O
3, H
2o, N
2o, CH
3oH or its combination in any.The flow of oxygen-containing gas asks 4000 ~ 8000 cc/min (sccm), and ashing power is 300 watts ~ 1200 watts, has also passed into nitrogen and hydrogen simultaneously.
Then, according to the opening etch semiconductor substrates formed in described hard mask layer, to form deep trench 20.The etching agent of usual employing is fluorine-containing gas, such as CF
4or CHF
3.Dry etching can be adopted, such as the combination in any of reactive ion etching, ion beam etching, plasma etching, laser ablation or these methods.Single lithographic method can be used, or also can use more than one lithographic method.Etching gas comprises HBr, Cl
2, CH
2f
2, O
2one or several gases, and some add gases as nitrogen, argon gas.The range of flow of described etching gas can be 0 ~ 150 cc/min (sccm), and reative cell internal pressure can be 3 ~ 50 millitorrs (mTorr), is to carry out plasma etching under the condition of 600W ~ 1500W at radio-frequency power.
As preferably, described deep trench 20 is positioned at the middle part of described fleet plough groove isolation structure, the described deep trench isolation structure formed to make subsequent technique is surrounded by described fleet plough groove isolation structure, isolates bad problem to avoid deep trench isolation structural top in prior art.
Further, described deep trench is positioned at the center of described fleet plough groove isolation structure, is positioned on the cross section central axis of described fleet plough groove isolation structure.
Perform step 203, the sidewall of described deep trench 20 forms protective oxide film 204.
Particularly, as shown in Figure 2 c, the sidewall of described deep trench 20 forms protective oxide film 204, the oxide that wherein said protective oxide film 204 can select this area conventional, be preferably SiO2.
The formation method of described protective oxide film 204 can the conventional deposition such as CVD, ALD or PVD be formed; then optionally the oxide of described semiconductor substrate surface and the formation of described deep trench 20 bottom deposit is removed in etching; only retain the oxide be positioned on described deep trench sidewall, to form described protective oxide film.
Or described protective oxide film 204 can also by the described semi-conducting material exposed in deep trench described in thermal oxidation 20, to form described protective oxide film 204.In a specific embodiment of the present invention; thermal oxidation (thermal oxidation) technique is adopted to form described protective oxide film 204; thermal oxidation technology can be film by wet hot oxidation technique or xeothermic oxidation technology; alternatively; by oxygen source, as at molecular oxygen or/and carry out thermal oxidation technology in the atmosphere of ozone.
It should be noted that, the method for above-mentioned execution thermal oxidation technology is exemplary, is not limited to described method, as long as this area additive method can realize described object, all can be applied to the present invention, not repeat them here.
Perform step 204, select semi-conducting material 205 to fill described deep trench 20, to form deep trench isolation structure.
Particularly, as shown in Figure 2 d, select semi-conducting material 205 in this step, fill described deep trench 20, then planarisation step is performed, semi-conducting material described in planarization is to described fleet plough groove isolation structure 203, and to form described deep trench isolation, described deep trench isolation structure is surrounded by described fleet plough groove isolation structure.
In an embodiment of the present invention, described semi-conducting material 205 (that is, has from every cubic centimetre about 1 × 10 including but not limited to the polysilicon of silicon, amorphous silicon, polysilicon, doping and polysilicon-Ge alloy material
18to about 1 × 10
22the doping content of individual foreign atom) and polycide (polycide) material (polysilicon/metal silicide laminated material of doping).
Similarly, any one formation previous materials of several methods can also be adopted.Limiting examples comprises chemical vapor deposition method, Technology for Heating Processing or physical gas-phase deposition.Usually, described grid material comprise have thickness from about 50 dusts the polycrystalline silicon material to the doping of about 1500 dusts.
The formation method of described semi-conducting material 205 can select low-pressure chemical vapor phase deposition (LPCVD) technique.The process conditions forming described polysilicon layer comprise: reacting gas is silane (SiH
4), the range of flow of described silane can be 100 ~ 200 cc/min (sccm), as 150sccm; In reaction chamber, temperature range can be 700 ~ 750 degrees Celsius; Reaction chamber internal pressure can be 250 ~ 350mTorr, as 300mTorr; Also can comprise buffer gas in described reacting gas, described buffer gas can be helium (He) or nitrogen, and the range of flow of described helium and nitrogen can be 5 ~ 20 liters/min (slm), as 8slm, 10slm or 15slm.
Then perform planarisation step, flattening method conventional in field of semiconductor manufacture can be used to realize the planarization on surface.The limiting examples of this flattening method comprises mechanical planarization method and chemico-mechanical polishing flattening method.Chemico-mechanical polishing flattening method is more conventional.
The present invention isolates bad problem to solve deep trench isolation structural top in prior art, provide a kind of new preparation method, first in described Semiconductor substrate, fleet plough groove isolation structure is formed in the process, then in described isolation structure and described Semiconductor substrate, deep trench is formed, then form sidewall oxide layer and fill the polysilicon adulterated, to form described deep trench isolation structure, the deep trench isolation structure prepared by described method is surrounded by described fleet plough groove isolation structure, enhance the isolation effect of described deep trench isolation structure, technique reduces alignment request, decrease processing step, adding technique can degree of realization.
Embodiment 2
Present invention also offers a kind of deep trench isolation structure, comprising:
Fleet plough groove isolation structure, is arranged in described Semiconductor substrate;
Deep trench isolation structure, is embedded in described fleet plough groove isolation structure and described Semiconductor substrate, and described fleet plough groove isolation structure is around surrounding described deep trench isolation structure.
Described Semiconductor substrate is also formed with active area, and described fleet plough groove isolation structure and described deep trench isolation structure are arranged in described active area.
With reference to Fig. 3, illustrated therein is the process chart that the present invention prepares described deep trench isolation structure, for schematically illustrating the flow process of whole manufacturing process.
Step 201 provides Semiconductor substrate, is formed with fleet plough groove isolation structure in described Semiconductor substrate;
Fleet plough groove isolation structure described in step 202 patterning and described Semiconductor substrate, to form deep trench in described fleet plough groove isolation structure and described Semiconductor substrate;
Step 203 forms protective oxide film on the sidewall of described deep trench;
Step 204 selects semi-conducting material to fill described deep trench, to form deep trench isolation structure.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (8)
1. a preparation method for deep trench isolation structure, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with fleet plough groove isolation structure;
Fleet plough groove isolation structure described in patterning and described Semiconductor substrate, to form deep trench in described fleet plough groove isolation structure and described Semiconductor substrate;
The sidewall of described deep trench is formed protective oxide film (204);
Semi-conducting material is selected to fill described deep trench, to form deep trench isolation structure.
2. method according to claim 1, is characterized in that, described deep trench is positioned at the middle part of described fleet plough groove isolation structure, with the top making described fleet plough groove isolation structure surround described deep trench.
3. method according to claim 1, is characterized in that, is formed with active area in described Semiconductor substrate, and described deep trench isolation structure is positioned at described active area.
4. method according to claim 1, is characterized in that, selects after semi-conducting material fills described deep trench, also comprises the step of planarization further.
5. method according to claim 1, is characterized in that, the polysilicon of doping selected by described semi-conducting material.
6. a deep trench isolation structure, comprising:
Semiconductor substrate;
Fleet plough groove isolation structure, is arranged in described Semiconductor substrate;
Deep trench isolation, be embedded in described fleet plough groove isolation structure and described Semiconductor substrate, described fleet plough groove isolation structure is around the top surrounding described deep trench isolation.
7. deep trench isolation structure according to claim 6, is characterized in that, is also formed with active area in described Semiconductor substrate, and described fleet plough groove isolation structure and described deep trench isolation are arranged in described active area.
8. deep trench isolation structure according to claim 7, is characterized in that, described deep trench isolation comprises the protective oxide film be positioned on deep trench sidewall and the semi-conducting material being positioned at center.
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