CN104868916A - Analog to digital converter and control method thereof - Google Patents
Analog to digital converter and control method thereof Download PDFInfo
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- CN104868916A CN104868916A CN201510315854.3A CN201510315854A CN104868916A CN 104868916 A CN104868916 A CN 104868916A CN 201510315854 A CN201510315854 A CN 201510315854A CN 104868916 A CN104868916 A CN 104868916A
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Abstract
The invention discloses an analog to digital converter and a control method thereof. The analog to digital converter comprises a switched capacitor network, a comparator and a successive approximation logical circuit. The working period of the analog to digital converter comprises a sampling stage and a quantification stage; at the sampling stage, the first input end of the comparator is disconnected from the switched capacitor network; and at the quantification stage, the first input end of the comparator is connected with the switched capacitor network. Through adoption of the analog to digital converter, a parasitic capacitor at the input end of the comparator is prevented from participating into sampling of input analog voltage, so that the influence of the parasitic capacitor on the linearity of the analog to digital converter is lowered remarkably, and the linearity of a system is enhanced.
Description
Technical field
The present invention relates to electronic circuit field, particularly, relate to a kind of analog to digital converter and the control method thereof that are applicable to MEMS (micro electro mechanical system).
Background technology
MEMS (micro electro mechanical system) (Micro Election Mechanical System, MEMS) utilizes micrometer/nanometer technical foundation, micrometer/nanometer material carried out to the technology designing processing and manufacturing test and control.Mechanical component, optical system driver part, electric-control system are all integrated in a minimum integral unit by MEMS (micro electro mechanical system).Therefore, in its signal processing, need to consider chip area and power problems.In the analog to digital converter (ADC) that MEMS (micro electro mechanical system) adopts, gradual approaching A/D converter (Successive Approximation Register Analog to DigitalConverter, SAR ADC) is desirable selection.
The circuit structure of SAR ADC is varied, roughly can be divided into three kinds: the calibration of voltage marking, electric current, electric charge calibration.Wherein electric charge calibration type is the type that application is more at present, and it utilizes electric capacity to complete binary chop algorithm (binary search) by Charge scaling, and therefore power consumption is generally smaller.
Electric charge demarcation type SAR ADC of the prior art comprises four parts: the first switch, comparator, switched capacitor network and SAR logic control circuit.The first end of the first switch is connected to input, and the second end is connected to switched capacitor network.The in-phase input end of comparator is connected to the second end of the first switch, and inverting input is connected to common-mode voltage.SAR logic control circuit controls the on off state of the first switch and switched capacitor network.In multiple clock cycle, by analog voltage compared with reference voltage, from highest significant position to least significant bit, determine the digital value of the analog signal of input by turn.
Non-linear is the index weighing SAR ADC dynamic property most critical.The design feature of electric charge demarcation type SARADC determines the parasitic capacitance of the input of comparator by the part as capacitance network, take part in the sampling to input analog signal and Charge scaling below.The comparator less for size and the larger system of capacitance network, even the parasitic capacitance of comparator is nonlinear, also can ignore the impact of the linearity performance of entirety.
But the low-power consumption small size of MEMS itself is two limiting factors of most critical.In the SAR ADC being applied to MEMS, adopt smaller capacitive network when meeting capacitance mismatch.As a result, the linearity performance of parasitic non-linear capacitance on entirety of comparator input terminal has significant impact, and this causes the deterioration in accuracy of analog to digital converter.
Summary of the invention
In view of this, the object of this invention is to provide a kind of analog to digital converter and the control method thereof that can improve the linearity.
According to a first aspect of the invention, the present invention proposes a kind of analog to digital converter, comprise: switched capacitor network, described switched capacitor network comprises multiple electric capacity, the first end of described multiple electric capacity is connected to public first node to receive input analog voltage, second end of described multiple electric capacity switches independently of one another between the first reference voltage and the second reference voltage, and the first reference voltage is different with the numerical value of the second reference voltage; Comparator, the first input end of described comparator is connected to first node, and the second input receives common-mode voltage; Approach by inchmeal logical circuit, the input of described Approach by inchmeal logical circuit is connected to the output of described comparator, output provides the output digit signals corresponding with input analog voltage, wherein, the work period of described analog to digital converter comprises sample phase and quantization stage, in sample phase, and the first input end of described comparator and the separated of first node, in quantization stage, the first input end of described comparator is connected with between first node.
Preferably, described analog to digital converter also comprises: the first switch, and the first end of described first switch receives input analog voltage, and the second end of described first switch is connected to first node; And second switch, the first end of described second switch is connected to the second end of described first switch, and the second end of described second switch is connected to the first input end of described comparator.
Preferably, described first switch and described second switch disconnect and closed respectively under the control of the first clock signal and the second clock signal, and described second clock signal is the inversion signal of described first clock signal.
Preferably, described analog to digital converter performs the action of sample phase during the first level of the first clock signal, the action of quantization stage is performed during the second electrical level of the first clock signal, first level is one in high level and low level, and second electrical level is another in high level and low level.
Preferably, the minimum resolution of described analog to digital converter is:
Δf(Vx)*V
COM/2
n*C-V
REF/2
n，
Wherein, V
rEF=V
rEFP-V
rEFM, V
rEFPand V
rEFPrepresent described first reference voltage and described second reference voltage respectively, V
cOMrepresent described common-mode voltage, n represents the figure place of described analog to digital converter, and f (Vx) represents the first input end parasitic capacitance of described comparator, and C represents the position of minimum capacitance of the described multiple switching capacity in described switched capacitor network.
Preferably, in described quantization stage, under the control of the 3rd clock signal, clock cycle produces comparative result to described comparator one by one, described Approach by inchmeal logical circuit produces control signal according to comparative result, described multiple electric capacity in described switched capacitor network is connected respectively to one of the first reference voltage and the second reference voltage according to control signal, makes described Approach by inchmeal logical circuit produce output digit signals by turn accordingly with the clock cycle of the 3rd clock signal.
Preferably, described analog to digital converter also comprises clock circuit, for generation of the first clock signal, the second clock signal and the 3rd clock signal.
Preferably, the electric capacity in described switched capacitor network is the metal-insulating layer-metal capacitor of CMOS technology.
According to a second aspect of the invention, the present invention proposes a kind of control method of analog to digital converter, and described analog to digital converter comprises switched capacitor network, comparator and Approach by inchmeal logical circuit; Described analog to digital converter comprises sampling and quantizes two working stages; The control method of described analog to digital converter comprises: in sample phase, is disconnected by the input of switched capacitor network with comparator; At quantization stage, switched capacitor network is connected with the input of comparator.
Analog to digital converter according to an embodiment of the invention, avoiding parasitic capacitance to participate in the sampling of input analog voltage by adding second switch and the second clock signal, significantly reducing the impact of parasitic capacitance on the analog to digital converter linearity, improve system linearity degree.
Accompanying drawing explanation
By referring to the description of accompanying drawing to the embodiment of the present invention, above-mentioned and other objects, features and advantages of the present invention will be more clear, in the accompanying drawings:
Fig. 1 illustrates the schematic circuit of the electric charge demarcation type SAR ADC of 8 of prior art;
The electric charge demarcation type SAR ADC of 8 of the prior art that Fig. 2 illustrates in Fig. 1 counts the equivalent circuit diagram of parasitic capacitance Cp;
Fig. 3 illustrates the impact of parasitic capacitance Cp on the transfer function of the electric charge demarcation type SAR ADC of 8 of prior art;
Fig. 4 illustrates the schematic circuit of the embodiment of electric charge demarcation type SAR ADC according to an embodiment of the invention;
Fig. 5 illustrates the analogous diagram of the transfer function of the embodiment of electric charge demarcation type SAR ADC according to an embodiment of the invention in Fig. 4.
Embodiment
Based on embodiment, present invention is described below, but the present invention is not restricted to these embodiments.In hereafter details of the present invention being described, detailedly describe some specific detail sections.Do not have the description of these detail sections can understand the present invention completely for a person skilled in the art yet.In order to avoid obscuring essence of the present invention, known method, process, flow process, element and circuit do not describe in detail.In addition, it should be understood by one skilled in the art that the accompanying drawing provided at this is all for illustrative purposes, and accompanying drawing is not necessarily drawn in proportion.
Should be appreciated that in the following description, " circuit " refers to the galvanic circle connected and composed by electrical connection or electromagnetism by least one element or electronic circuit.When " being connected to " another element when claiming element or circuit or claiming element/circuit " to be connected to " between two nodes, it can be directly couple or be connected to another element or can there is intermediary element, the connection between element can be physically, in logic or its combine.On the contrary, " be directly coupled to " when claiming element or " being directly connected to " another element time, mean that both do not exist intermediary element.Unless the context clearly requires otherwise, similar words such as " comprising ", " comprising " otherwise in whole specification and claims should be interpreted as the implication that comprises instead of exclusive or exhaustive implication; That is, be the implication of " including but not limited to ".In describing the invention, it is to be appreciated that term " first ", " second " etc. are only for describing object, and instruction or hint relative importance can not be interpreted as.In addition, in describing the invention, except as otherwise noted, the implication of " multiple " is two or more.
Fig. 1 illustrates the circuit diagram of the electric charge demarcation type SAR ADC of 8 of prior art.With reference to Fig. 1, the electric charge demarcation type SAR ADC of such as 8 comprises: comparator U1, the first switch S
sH, switched capacitor network 100, SAR logic control circuit U2.
The in-phase input end of comparator U1 is via the first switch S
sHbe connected to input analog voltage, inverting input connects common-mode voltage V
cOM.The output of comparator U1 connects the input of SAR logic control circuit U2.SAR logic control circuit U2 exports output digit signals Dout.
Switched capacitor network 100 comprises electric capacity C0 to electric capacity C8, and selector switch S0 is to selector switch S8.A pole plate of electric capacity C0 to electric capacity C8 is connected to the in-phase input end of comparator U1 respectively, and another pole plate connects selector switch S0 respectively to selector switch S8.Under the control of SAR logic control circuit U2, selector switch S0 to selector switch S8 connects Differential Input reference voltage V respectively
rEFP, V
rEFMin one.The size of electric capacity C0 to electric capacity C8 is respectively C, C, 2C, 2
2c, 2
3c, 2
4c, 2
5c, 2
6c, 2
7c.
Electric capacity C0 to electric capacity C8 is generally metal-insulator-metal (Metal Insulator Metal, the MIM) electric capacity adopting CMOS technology.In the electric charge calibration type SAR ADC of current main flow, bottom crown sampling and top crown is divided into again to sample two kinds.Bottom crown sampling is widely applied as traditional charge type SAR structure, and top crown sampling is applied more in high speed, low-power consumption, low-voltage field.Illustrate that it realizes principle for the charge type SAR ADC of the top crown sampling structure of 8 in this article.
In top crown sampling structure, the top crown of electric capacity C0 to electric capacity C8 connects selector switch S0 to S8 respectively, and the bottom crown of electric capacity C0 to electric capacity C8 is connected to the in-phase input end of comparator U1 respectively.Input analog voltage Vin is by the first switch S
sHbe connected to the bottom crown of electric capacity C0 to electric capacity C8.First switch S
sHdisconnect under the control of the first clock signal and close.
In sample phase, the first switch S
sHclosed, selector switch S8 connects differential input voltage V
rEFP, selector switch S0 to selector switch S7 connects differential input voltage V
rEFM.Now, the electric charge summation that the bottom crown of electric capacity C0 to electric capacity C8 accumulates is:
Q＝128C*(Vin-V
REFP)+128C*(Vin-V
REFM) (1)。
At quantization stage, the first switch S
sHdisconnect, first switch S 0 to switch S 8 hold mode is constant, and the voltage of X node remains Vin.Comparator U1 compares Vin and V
cOM, the threshold value compared is V
cOM, comparative result determines the highest significant position MSB of the output digit signals Dout of SAR ADC.If Vin is less than V
cOM, the highest significant position MSB of output digit signals Dout is that switch S 7 is connected to V by 0, SAR logic control circuit U2
rEFP.According to charge conservation, now the voltage of X node is Vin+ (V
rEFP-V
rEFM)/4, that comparator U1 compares is Vin+ (V
rEFP-V
rEFM)/4 and V
cOM.The scope of input analog voltage Vin is [V
cOM-(V
rEFP-V
rEFM)/2:V
cOM+ (V
rEFP-V
rEFM)/2], this time comparative result determines the secondary high significance bit of the output digit signals Dout of SARADC, and threshold value is V
cOM-(V
rEFP-V
rEFM)/4.In like manner, if Vin < is V
cOM-(V
rEFP-V
rEFM)/4, the 3rd step relatively in selector switch S6 is connected to V
rEFP, the threshold value that the 3rd step compares is V
cOM-3* (V
rEFP-V
rEFM)/8.
If input analog voltage is enough little, such as, close to the lower limit of input range, then determine output digit signals Dout from highest significant position by turn to least significant bit.Vin successively and V
cOM, V
cOM-(V
rEFP-V
rEFM)/4, V
cOM-3* (V
rEFP-V
rEFMthe threshold values such as)/8 compare.Until threshold value V
cOM-(2
7-1) * (V
rEFP-V
rEFM)/2
8, determine the least significant bit LSB of output digit signals Dout.
If the analog signal Vin of input is less than V
cOM-(2
7-1) * (V
rEFP-V
rEFM)/2
8, then the digital signal Dout=00000000 exported, minimum resolution is (V
rEFP-V
rEFM)/2
8, transmission curve is straight line.Conveniently analyze, [000000000:11111111] simulation is turned to [-(V
rEFP-V
rEFM)/2:(V
rEFP-V
rEFM)/2], the desirable transmission curve Vout=Vin-V in Fig. 3 can be obtained
cOM.
More than discussing is under being the hypothesis of ideal state based on capacitance network and comparator U1, and in fact the parameter of real produced device all exists certain nonideality on absolute value and consistency.In the switched capacitor network of this top crown sampling structure, the parasitic capacitance Cp of the X node of the input of comparator U1 is exactly to the highstrung parameter of the entire system linearity.
Fig. 2 is the equivalent circuit diagram that electric charge demarcation type SAR ADC in Fig. 1 considers parasitic capacitance Cp.From above-mentioned derivation, parasitic capacitance Cp can not affect the comparative result of the first step, namely comparator U1 compare or Vin and V
cOM.Follow-up relatively in, parasitic capacitance Cp take part in electric charge distribute, therefore the voltage of X node will be subject to the impact of parasitic capacitance Cp.If parasitic capacitance Cp is fixed capacity, so everybody compare threshold of the output digit signals of SAR ADC also can linear change.As shown in Figure 3, when parasitic capacitance Cp linear change, the change that the input-output curve of SAR ADC only can demonstrate gain does not affect its linearity, and system gain can be calibrated.
But, the input of actual comparator U1 is the grid of MOSFET, in whole SARADC comparison procedure, this MOSFET is often between each states such as cut-off region, sub-threshold region, linear zone, saturation region and switches, and between each state, gate capacitance change is nonlinear.Especially, when this transistor size is larger, non-linear being enough to of parasitic capacitance Cp affects the non-linear of whole system.As shown in Figure 3, when parasitic capacitance Cp nonlinear change, the linearity of the input-output curve of SAR ADC is subject to a significant impact.X point voltage is close to V
cOMnear, input pipe is more close to saturation region, and its parasitic capacitance Cp is larger, and the slope deriving transfer function is larger, and the closer to threshold value two ends, the slope of transfer function is less.
Fig. 4 illustrates the circuit diagram of the embodiment of 8 electric charge demarcation type SAR ADC according to an embodiment of the invention, and this SAR ADC comprises: comparator U1, the first switch S
sH, switched capacitor network 100, switch S 10, SAR logic control circuit U2.Wherein, electric capacity Cp is the parasitic capacitance of the input of comparator U1.
The in-phase input end of comparator U1 is via the first switch S
sHbe connected to input analog voltage, inverting input connects common-mode voltage V
cOM.The output of comparator U1 connects the input of SAR logic control circuit U2.SAR logic control circuit U2 exports output digit signals Dout.
Switched capacitor network 100 comprises electric capacity C0 to electric capacity C8, and selector switch S0 is to selector switch S8.Electric capacity C0 to electric capacity C8 is the MIM capacitor adopting CMOS technology, and adopt top crown sampling structure, the top crown of electric capacity C0 to electric capacity C8 connects selector switch S0 to S8 respectively, and the bottom crown of electric capacity C0 to electric capacity C8 is connected to the in-phase input end of comparator U1 respectively.Input analog voltage Vin is by the first switch S
sHbe connected to the bottom crown of electric capacity C0 to electric capacity C8.First switch disconnects and closes under the control of the first clock signal.Selector switch S0 to selector switch S8 connects Differential Input reference voltage V respectively under the control of SAR logic control circuit U2
rEFP, V
rEFMin one.The size of electric capacity C0 to electric capacity C8 is respectively C, C, 2C, 2
2c, 2
3c, 2
4c, 2
5c, 2
6c, 2
7c.
The bottom crown of electric capacity C0 to electric capacity C8 connects the in-phase input end of comparator U1 by switch S 10.Switch S 10 closed and disconnected under the control of the second clock signal, wherein, the second clock signal is the inversion signal of the first clock signal.
In sample phase, the first switch S
sHclosed, switch S 10 disconnects.Parasitic capacitance Cp does not participate in sampling.
At quantization stage, the first switch S
sHdisconnect, switch S 10 closes.SAR ADC completes binary chop and input analog voltage is converted to output digit signals Dout.
The first above-mentioned clock signal and the second clock signal can be produced by the clock circuit of the clock circuit of analog to digital converter self or outside.
The reason being improved the system linear degree of analog to digital converter by switch S 10 and the second clock signal is described below in detail:
First the situation not having switch S 10 and the second clock signal is considered.Due to the parasitic gate electric capacity that parasitic capacitance Cp is MOSFET, its size changes along with the conducting state of MOSFET, and grid voltage determines the conducting state of MOSFET, and therefore the size of Cp is grid voltage, also be the function of the voltage Vx of X node, i.e. Cp=f (Vx).Equally, according to X nod charge total amount conservation, after the impact counting parasitic capacitance Cp, often walking the threshold value frequency length compared with input analog voltage is
Wherein, V
rEF=V
rEFP-V
rEFMsample phase, Vx=Vin, the size of parasitic capacitance Cp when f (Vin) is input analog voltage sampling, f (Vx) is the size of the parasitic capacitance Cp in Charge scaling process, and its value changes along with the voltage Vx of X node in each selector switch S0 to S7 handoff procedure.According to the characteristic of SAR ADC, the voltage of comparator two input is constantly close, in a SAR cycle period, often more once, the range shorter half of Vx, the voltage of Vx enough ensures that comparator is in normal operating conditions (but not by district), and the f (Vx) that is in formula (2) relatively f (Vin) can regard a stable electric capacity substantially as.Conveniently analyze, we only consider the transmission curve under f (Vin).Now, minimum resolution is: V
rEF/ 2
8* [1+f (Vin)/256C], its transfer function is Vout=[1+f (Vin)/256C] * (Vin-V
cOM), clearly due to the function that f (Vin) is with Vin change, therefore Vout and Vin is no longer simple linear relationship.Because the excursion of Vin is too large, inevitably have some Vin and cause parasitic capacitance Cp to be in on-fixed value, as shown in Figure 3, Vin is at V
cOMnear, MOSFET is closer to saturation region, and minimum resolution is less than normal, and the slope of transmission curve is bigger than normal, away from V
cOMregion, MOSFET may be in cut-off region or linear zone, and Cp is less, and minimum resolution is comparatively large, and the slope of transmission curve is less than normal, linearity severe exacerbation.
In analog to digital converter according to an embodiment of the invention, in sample phase, participate in the electric capacity only had in switched capacitor network 100 of sampling, parasitic capacitance Cp does not participate in sampling, therefore eliminates the non-linear interference to sampled signal of parasitic capacitance Cp.Often walking the threshold value frequency length compared with input analog voltage is
Therefore, minimum resolution is: Δ f (Vx) * V
cOM/ 256C-V
rEF/ 2
8, because f (Vx) substantially constant, therefore Δ f (Vx) * V
cOM/ 256C can be very little, therefore the very close V ideally of minimum resolution
rEF/ 2
8.
Fig. 5 illustrates the analogous diagram of the transfer function of the embodiment of electric charge demarcation type SAR ADC according to an embodiment of the invention.As shown in Figure 5, transmission curve is straight line, and electric charge demarcation type SAR ADC essentially eliminates the non-linear effects that parasitic capacitance Cp causes according to an embodiment of the invention.
According to the control method of analog to digital converter of the present invention, this analog to digital converter comprises switched capacitor network, comparator and Approach by inchmeal logical circuit.Analog to digital converter comprises sampling and quantizes two working stages.The control method of analog to digital converter of the present invention comprises: in sample phase, is disconnected by the input of switched capacitor network with comparator; At quantization stage, switched capacitor network is connected with the input of comparator.
Analog to digital converter according to an embodiment of the invention, avoiding parasitic capacitance to participate in the sampling of input analog voltage by adding second switch and the second clock signal, significantly reducing the impact of parasitic capacitance on the analog to digital converter linearity, improve system linearity degree.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, to those skilled in the art, the present invention can have various change and change.All do within spirit of the present invention and principle any amendment, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. an analog to digital converter, comprising:
Switched capacitor network, described switched capacitor network comprises multiple electric capacity, the first end of described multiple electric capacity is connected to public first node to receive input analog voltage, second end of described multiple electric capacity switches independently of one another between the first reference voltage and the second reference voltage, and the first reference voltage is different with the numerical value of the second reference voltage;
Comparator, the first input end of described comparator is connected to first node, and the second input receives common-mode voltage;
Approach by inchmeal logical circuit, the input of described Approach by inchmeal logical circuit is connected to the output of described comparator, and output provides the output digit signals corresponding with input analog voltage,
Wherein, the work period of described analog to digital converter comprises sample phase and quantization stage, in sample phase, and the first input end of described comparator and the separated of first node, in quantization stage, the first input end of described comparator is connected with between first node.
2. analog to digital converter according to claim 1, also comprises:
First switch, the first end of described first switch receives input analog voltage, and the second end of described first switch is connected to first node; And
Second switch, the first end of described second switch is connected to the second end of described first switch, and the second end of described second switch is connected to the first input end of described comparator.
3. analog to digital converter according to claim 2, wherein, described first switch and described second switch disconnect and closed respectively under the control of the first clock signal and the second clock signal, and described second clock signal is the inversion signal of described first clock signal.
4. analog to digital converter according to claim 3, wherein, the minimum resolution of described analog to digital converter is:
Δf(Vx)*V
COM/2
n*C-V
REF/2
n，
Wherein, V
rEF=V
rEFP-V
rEFM, V
rEFPand V
rEFPrepresent described first reference voltage and described second reference voltage respectively, V
cOMrepresent described common-mode voltage, n represents the figure place of described analog to digital converter, and f (Vx) represents the first input end parasitic capacitance of described comparator, and C represents the position of minimum capacitance of the described multiple switching capacity in described switched capacitor network.
5. analog to digital converter according to claim 3, wherein, described analog to digital converter performs the action of sample phase during the first level of the first clock signal, the action of quantization stage is performed during the second electrical level of the first clock signal, first level is one in high level and low level, and second electrical level is another in high level and low level.
6. analog to digital converter according to claim 5, wherein, in described quantization stage, under the control of the 3rd clock signal, clock cycle produces comparative result to described comparator one by one, described Approach by inchmeal logical circuit produces control signal according to comparative result, described multiple electric capacity in described switched capacitor network is connected respectively to one of the first reference voltage and the second reference voltage according to control signal, makes described Approach by inchmeal logical circuit produce output digit signals by turn accordingly with the clock cycle of the 3rd clock signal.
7. analog to digital converter according to claim 6, wherein, described analog to digital converter also comprises clock circuit, for generation of the first clock signal, the second clock signal and the 3rd clock signal.
8. analog to digital converter according to claim 1, wherein, the electric capacity in described switched capacitor network is the metal-insulating layer-metal capacitor of CMOS technology.
9. a control method for analog to digital converter, described analog to digital converter comprises switched capacitor network, comparator and Approach by inchmeal logical circuit; Described analog to digital converter comprises sampling and quantizes two working stages; The control method of described analog to digital converter comprises: in sample phase, is disconnected by the input of switched capacitor network with comparator; At quantization stage, switched capacitor network is connected with the input of comparator.
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| CN111313903A (en) * | 2018-05-31 | 2020-06-19 | 深圳市汇顶科技股份有限公司 | Successive Approximation Register (SAR) analog-to-digital converter (ADC) dynamic range extension |
| CN114448438A (en) * | 2022-04-02 | 2022-05-06 | 杰创智能科技股份有限公司 | Successive approximation type analog-to-digital converter |
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| CN106657833A (en) * | 2016-11-04 | 2017-05-10 | 刘强 | Column level ADC (Analog to Digital Converter) circuit for CMOS (Complementary Metal-Oxide-Semiconductor Transistor) image sensor |
| CN109728812A (en) * | 2017-10-30 | 2019-05-07 | 亚德诺半导体无限责任公司 | Noise shaping analog-digital converter |
| CN109728812B (en) * | 2017-10-30 | 2023-04-14 | 亚德诺半导体国际无限责任公司 | Noise shaping analog-to-digital converter |
| CN111313903A (en) * | 2018-05-31 | 2020-06-19 | 深圳市汇顶科技股份有限公司 | Successive Approximation Register (SAR) analog-to-digital converter (ADC) dynamic range extension |
| CN111313903B (en) * | 2018-05-31 | 2023-09-22 | 深圳市汇顶科技股份有限公司 | Successive Approximation Register (SAR) analog-to-digital converter (ADC) dynamic range extension |
| CN110912545A (en) * | 2019-12-04 | 2020-03-24 | 电子科技大学 | Low input signal crosstalk multi-path time division multiplexing SAR ADC circuit system |
| CN114448438A (en) * | 2022-04-02 | 2022-05-06 | 杰创智能科技股份有限公司 | Successive approximation type analog-to-digital converter |
| CN114448438B (en) * | 2022-04-02 | 2022-07-15 | 杰创智能科技股份有限公司 | Successive approximation type analog-to-digital converter |
| CN117997314A (en) * | 2024-04-01 | 2024-05-07 | 成都铭科思微电子技术有限责任公司 | Common mode stabilizing circuit of switch capacitance type comparator |
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