CN104866457A

CN104866457A - On-chip multi-core processor static architecture based on shared cache

Info

Publication number: CN104866457A
Application number: CN201510302580.4A
Authority: CN
Inventors: 李嵩; 褚廷斌; 黄乐天; 袁正希
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2015-06-04
Filing date: 2015-06-04
Publication date: 2015-08-26
Anticipated expiration: 2035-06-04
Also published as: CN104866457B

Abstract

The invention discloses an on-chip multi-core processor static architecture based on a shared cache comprising n nodes, wherein n is an even number, which is more than 0, and the nodes comprise n/2 class-A nodes and n/2 class-B nodes; each class-A node comprises a processing core, a local privately-owned cache L1 and a router R; each class-B node comprises a processing core, a local privately-owned cache L1, a router R and a shared cache l2bank; the nodes communicate with each other via the routers; the class-A nodes and the class-B nodes are distributed at intervals; the capacity of the shared cache l2bank is twice as the shared cache in a universal framework. The on-chip multi-core processor static architecture based on the shared cache provided by the invention saves hardware expenditure and area of the last level cache on the basis of not adding access delay of a whole on-chip network and congestion extent of the whole on-chip network to save static power consumption of the cache.

Description

A kind of chip multi-core processor static framework based on shared buffer memory

Technical field

The present invention relates to a kind of chip multi-core processor static framework based on shared buffer memory.

Background technology

As shown in Figure 1, a kind of conventional network-on-chip polycaryon processor framework, we are with 16 conventional cores, second level cache is example, this conventional structure is made up of 16 nodes, each node includes the router R for communicating, the shared buffer memory l2bank of process core core and a local private cache L1 and larger area, because this structure is carried out data interaction based on the mechanism of shared buffer memory and communicate, and the area of shared buffer memory l2bank shared by whole network-on-chip is very large, therefore its power consumption impact brought is also very large, especially the ratio shared by quiescent dissipation.

From Fig. 1, we can see, each processor core core is connected with a shared buffer memory l2bank, due in the process of routine access, read and write data the data read and write possibly and store in the shared buffer memory l2bank at relative distance processor core core place far away, so when doing Static Design, the average number of hops mean distance of shared buffer memory l2bank (core access) and in the process of data interaction, the congestion problems (guaranteeing fairness) of whole network is all the factor needing to consider, the requirement that data store is increasing, the area of shared buffer memory l2bank is also increasing, thus its quiescent dissipation accounts for the ratio of whole network-on-chip also in the trend increasingly increased, therefore adopt this generic structure also to become a very important problem due to power problems that shared buffer memory l2bank area is excessive brought.

Summary of the invention

The object of the invention is to overcome the deficiencies in the prior art, a kind of chip multi-core processor static framework based on shared buffer memory is provided, do not increase whole network-on-chip access time delay, do not increase on the basis of Congestion Level SPCC of whole network-on-chip, save hardware spending and the area of afterbody high-speed cache, save the quiescent dissipation of high-speed cache.

The object of the invention is to be achieved through the following technical solutions: a kind of chip multi-core processor static framework based on shared buffer memory, it comprises n node, n be greater than 0 even number, described node comprises n/2 category-A node and n/2 category-B node; Described category-A node comprises process core core, local private cache L1 and router R; Described category-B node comprises process core core, local private cache L1, router R and shared buffer memory l2bank; Communicated by router between described node; Described category-A node becomes batch (-type) to distribute with category-B node; The capacity of described shared buffer memory l2bank is the twice of the shared buffer memory in generic structure.

Described node number is 16, comprises the category-A node described in 8 and the category-B node described in 8.

Described local private cache L1 comprises instruction buffer and data buffer storage.

The invention has the beneficial effects as follows: (1) can ensure that the mean distance of accessing shared buffer memory l2bank is the same with the mean distance of generic structure, thus additionally can not increase the access time delay of whole network-on-chip.

(2) the present invention is in design process of hardware, each shared buffer memory l2bank structure is identical with traditional, only storage space adds one times, and the decreased number of shared buffer memory l2bank is original half, the i.e. shared buffer memory capacity of whole afterbody high-speed cache and the identical of generic structure, is used for meeting the needs that data store; But decrease the l2bank of half, it also reduce the peripheral hardware expense of half, the number of such as amplifier and code translator we decrease half, therefore its hardware design area also can reduce to some extent, and the quiescent dissipation of high-speed cache also can reduce.

(3) node comprising shared buffer memory l2bank becomes batch (-type) to distribute with the node not comprising shared buffer memory l2bank, in the process of data interaction, can guarantee fairness, can not bring the problem of network congestion.

Accompanying drawing explanation

Fig. 1 is conventional network-on-chip polycaryon processor configuration diagram;

Fig. 2 is structural representation of the present invention.

Embodiment

Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail, but protection scope of the present invention is not limited to the following stated.

As shown in Figure 2, a kind of chip multi-core processor static framework based on shared buffer memory, it comprises n node, n be greater than 0 even number, described node comprises n/2 category-A node and n/2 category-B node; Described category-A node comprises process core core, local private cache L1 and router R; Described category-B node comprises process core core, local private cache L1, router R and shared buffer memory l2bank; Communicated by router between described node; Described category-A node becomes batch (-type) to distribute with category-B node; The capacity of described shared buffer memory l2bank is the twice of the shared buffer memory in generic structure.

As can be seen from Figure 2, do not comprise the category-A node of shared buffer memory l2bank and comprise the distribution situation of shared buffer memory l2bankB category node, 16 Node distribution shown in the figure are four lines four row, no matter from laterally or longitudinally, all comprise a category-B node between every two category-A nodes, between every two category-B nodes, all comprise a category-A node; The batch (-type) distribution that Here it is mentions hereinbefore.

Claims

1. based on a chip multi-core processor static framework for shared buffer memory, it is characterized in that: it comprises n node, n be greater than 0 even number, described node comprises n/2 category-A node and n/2 category-B node; Described category-A node comprises process core core, local private cache L1 and router R; Described category-B node comprises process core core, local private cache L1, router R and shared buffer memory l2bank; Communicated by router between described node; Described category-A node becomes batch (-type) to distribute with category-B node; The capacity of described shared buffer memory l2bank is the twice of the shared buffer memory in generic structure.

2. a kind of chip multi-core processor static framework based on shared buffer memory according to claim 1, is characterized in that: described node number is 16, comprises the category-A node described in 8 and the category-B node described in 8.

3. a kind of chip multi-core processor static framework based on shared buffer memory according to claim 1, is characterized in that: described local private cache L1 comprises instruction buffer and data buffer storage.